TWI590349B - Chip package and chip packaging process - Google Patents
Chip package and chip packaging process Download PDFInfo
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- TWI590349B TWI590349B TW105113070A TW105113070A TWI590349B TW I590349 B TWI590349 B TW I590349B TW 105113070 A TW105113070 A TW 105113070A TW 105113070 A TW105113070 A TW 105113070A TW I590349 B TWI590349 B TW I590349B
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- wafer
- line carrier
- encapsulant
- conductive
- conductive layer
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- 238000012858 packaging process Methods 0.000 title claims description 12
- 239000008393 encapsulating agent Substances 0.000 claims description 78
- 239000004020 conductor Substances 0.000 claims description 50
- 238000000034 method Methods 0.000 claims description 23
- 238000005553 drilling Methods 0.000 claims description 5
- 238000009713 electroplating Methods 0.000 claims description 5
- 238000000227 grinding Methods 0.000 claims description 3
- 239000000084 colloidal system Substances 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 73
- 239000010410 layer Substances 0.000 description 58
- 229910000679 solder Inorganic materials 0.000 description 30
- 238000004519 manufacturing process Methods 0.000 description 21
- 239000012792 core layer Substances 0.000 description 14
- 239000000463 material Substances 0.000 description 9
- 238000004891 communication Methods 0.000 description 7
- 238000004806 packaging method and process Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
本發明是有關於一種晶片封裝體及晶片封裝製程,且特別是有關於一種具有導電柱的晶片封裝體及晶片封裝製程。The present invention relates to a chip package and a chip package process, and more particularly to a chip package having a conductive pillar and a wafer package process.
在半導體產業中,積體電路(Integrated Circuits, IC)的生產,主要分為三個階段:晶圓(wafer)的製造、積體電路的製作以及晶片的封裝(Package)等。其中,晶片係經由晶圓製作、電路設計、光罩製作、電路製作以及切割晶圓等步驟而完成,而每一顆由晶圓切割所形成的晶片,在經由晶片上之接點與外部訊號電性連接後,可再以封裝膠體材料將晶片包覆,其封裝之目的在於防止晶片受到濕氣、熱量、雜訊的影響,並提供晶片與外部電路之間電性連接的媒介,如此即完成積體電路的生產。In the semiconductor industry, the production of integrated circuits (ICs) is mainly divided into three stages: the manufacture of wafers, the fabrication of integrated circuits, and the packaging of wafers. The wafer is completed by steps of wafer fabrication, circuit design, mask fabrication, circuit fabrication, and wafer dicing, and each wafer formed by wafer dicing is connected to the external signal via the wafer. After electrical connection, the wafer can be coated with a package of colloidal materials, the purpose of which is to prevent the wafer from being affected by moisture, heat, noise, and to provide a medium for electrical connection between the wafer and an external circuit, that is, Complete the production of integrated circuits.
在通訊元件的製造過程中,在以封裝膠體將通訊晶片包覆之後,須進一步製作外部天線,此外部天線的製作包括形成外部天線本身以及連接於外部天線與通訊晶片之間的接觸導體。一般而言,前述的接觸導體通常是在封裝膠體製作完成之後以雷射鑽孔搭配導電材料的填入進行製作。In the manufacturing process of the communication component, after the communication chip is covered with the encapsulant, an external antenna is further fabricated. The external antenna is formed by forming an external antenna itself and a contact conductor connected between the external antenna and the communication chip. In general, the aforementioned contact conductors are usually fabricated by filling a laser with a conductive material after the encapsulation is completed.
然而,因為封裝膠體過厚且雷射的能量不易控制,所以以雷射鑽孔方式於封裝膠體中形成接觸開口面臨了製程裕度(process window)不足的問題。因此,外部天線與通訊晶片之間的電性連接有可能會出現開路或電氣特性不佳等問題,進而導致通訊元件的封裝良率無法有效被提升。因此,如何進一步提升通訊元件的封裝良率,實已成目前亟欲解決的課題。However, since the encapsulant is too thick and the energy of the laser is difficult to control, forming a contact opening in the encapsulant by laser drilling faces a problem of insufficient process window. Therefore, the electrical connection between the external antenna and the communication chip may cause problems such as an open circuit or poor electrical characteristics, and the package yield of the communication component may not be effectively improved. Therefore, how to further improve the packaging yield of communication components has become a problem that is currently being solved.
本發明提供多種晶片封裝體以及多種晶片封裝製程。The present invention provides a variety of chip packages and a variety of wafer packaging processes.
本發明提供一種晶片封裝製程,其包括下列步驟。提供一線路載板,此線路載板上具有一導電柱。將一晶片置於線路載板上,其中晶片透過至少一焊線與線路載板電性連接。於線路載板上形成一封裝膠體,以包覆晶片及導電柱。移除部分的封裝膠體,以暴露出導電柱的一頂面。於封裝膠體上形成與導電柱頂面連接的一導電層,此導電層透過線路載板與晶片電性連接。於線路載板上形成多個外部端子,此外部端子與晶片在線路載板的不同側的,且外部端子透過線路載板與晶片電性連接。The present invention provides a wafer packaging process that includes the following steps. A line carrier is provided, the line carrier having a conductive post. A wafer is placed on the line carrier, wherein the wafer is electrically connected to the line carrier through at least one bonding wire. An encapsulant is formed on the line carrier to cover the wafer and the conductive post. A portion of the encapsulant is removed to expose a top surface of the conductive post. A conductive layer is formed on the encapsulant and connected to the top surface of the conductive pillar, and the conductive layer is electrically connected to the wafer through the wiring carrier. A plurality of external terminals are formed on the line carrier, the external terminals and the wafer are on different sides of the line carrier, and the external terminals are electrically connected to the wafer through the line carrier.
本發明提供一種晶片封裝體,其包括一線路載板、一晶片、一封裝膠體、一導電層以及多個外部端子。線路載板具有一導電柱。晶片配置於線路載板上,並且透過至少一焊線與線路載板電性連接。封裝膠體配置於線路載板上,其中封裝膠體包覆晶片及導電柱,且導電柱的一頂面暴露於封裝膠體外。導電層配置於封裝膠體上以與導電柱的頂面連接,其中導電層透過線路載板與晶片電性連接。外部端子與晶片位於線路載板的不同側,且外部端子透過線路載板與晶片電性連接。The invention provides a chip package comprising a circuit carrier, a wafer, an encapsulant, a conductive layer and a plurality of external terminals. The line carrier has a conductive post. The wafer is disposed on the line carrier and electrically connected to the line carrier through at least one bonding wire. The encapsulant is disposed on the line carrier, wherein the encapsulant encapsulates the wafer and the conductive post, and a top surface of the conductive post is exposed to the outside of the encapsulant. The conductive layer is disposed on the encapsulant to be connected to the top surface of the conductive pillar, wherein the conductive layer is electrically connected to the wafer through the wiring carrier. The external terminals and the wafer are on different sides of the line carrier, and the external terminals are electrically connected to the wafer through the line carrier.
在本發明的一實施例中,移除部分的封裝膠體的方法包括研磨。In an embodiment of the invention, the method of removing a portion of the encapsulant comprises grinding.
在本發明的一實施例中,形成導電層的方法包括電鍍。In an embodiment of the invention, a method of forming a conductive layer includes electroplating.
在本發明的一實施例中,導電柱與晶片位於線路載板的同側,且導電柱的高度大於晶片的厚度。In an embodiment of the invention, the conductive post and the wafer are on the same side of the line carrier, and the height of the conductive post is greater than the thickness of the wafer.
本發明提供另一種晶片封裝製程,其包括下列步驟。提供一線路載板,此線路載板上具有一導電柱。將一晶片置於線路載板,其中晶片透過至少一焊線與線路載板電性連接。於線路載板上形成一封裝膠體,以包覆晶片及導電柱。移除部分的封裝膠體,以於封裝膠體內形成一開口,且此開口暴露出導電柱的一頂面。於開口中填入一接觸導體。於封裝膠體上形成與接觸導體頂面連接的一導電層,此導電層透過接觸導體及線路載板與晶片電性連接。The present invention provides another wafer packaging process that includes the following steps. A line carrier is provided, the line carrier having a conductive post. A wafer is placed on the line carrier, wherein the wafer is electrically connected to the line carrier through at least one bonding wire. An encapsulant is formed on the line carrier to cover the wafer and the conductive post. A portion of the encapsulant is removed to form an opening in the encapsulant, and the opening exposes a top surface of the conductive post. A contact conductor is filled in the opening. A conductive layer is formed on the encapsulant and connected to the top surface of the contact conductor. The conductive layer is electrically connected to the wafer through the contact conductor and the line carrier.
本發明提供另一種晶片封裝體,其包括一線路載板、一接觸導體、一晶片、一封裝膠體、一導電層以及多個外部端子。線路載板具有一導電柱。接觸導體配置於導電柱上。晶片配置於線路載板上,並且與線路載板電性連接。封裝膠體配置於線路載板上,其中封裝膠體包覆晶片、導電柱及接觸導體,且接觸導體的一頂面暴露於封裝膠體外。導電層配置於封裝膠體上以與接觸導體的頂面連接,其中導電層透過接觸導體及線路載板與晶片電性連接。外部端子與晶片位於線路載板的不同側,且外部端子透過線路載板與晶片電性連接。The invention provides another chip package comprising a circuit carrier, a contact conductor, a wafer, an encapsulant, a conductive layer and a plurality of external terminals. The line carrier has a conductive post. The contact conductor is disposed on the conductive post. The wafer is disposed on the line carrier and electrically connected to the line carrier. The encapsulant is disposed on the line carrier, wherein the encapsulant covers the wafer, the conductive post and the contact conductor, and a top surface of the contact conductor is exposed outside the encapsulant. The conductive layer is disposed on the encapsulant to be connected to the top surface of the contact conductor, wherein the conductive layer is electrically connected to the wafer through the contact conductor and the line carrier. The external terminals and the wafer are on different sides of the line carrier, and the external terminals are electrically connected to the wafer through the line carrier.
在本發明的另一實施例中,移除部分的封裝膠體以於封裝膠體內形成開口的方法包括雷射鑽孔。In another embodiment of the invention, a method of removing a portion of the encapsulant to form an opening in the encapsulant comprises laser drilling.
在本發明的另一實施例中,形成導電層的方法包括電鍍。In another embodiment of the invention, a method of forming a conductive layer includes electroplating.
在本發明的另一實施例中,更包括於線路載板上形成多個外部端子,其中外部端子與晶片位於線路載板的不同側,且外部端子透過線路載板與晶片電性連接。In another embodiment of the present invention, the method further includes forming a plurality of external terminals on the line carrier, wherein the external terminals and the wafer are on different sides of the line carrier, and the external terminals are electrically connected to the wafer through the line carrier.
在本發明的另一實施例中,導電柱、接觸導體與晶片位於線路載板的同側。In another embodiment of the invention, the conductive posts, contact conductors, and wafers are on the same side of the line carrier.
基於上述,本發明上述實施例在形成封裝膠體之前先於線路載板上形成導電柱,此製程順序可以提升晶片封裝製程的封裝良率。此外,由於導電柱的製作早於封裝膠體的形成,因此封裝膠體的厚度不會影響到導電柱的製作良率。Based on the above, the above embodiment of the present invention forms a conductive pillar on the wiring carrier before forming the encapsulant, and the process sequence can improve the packaging yield of the wafer packaging process. In addition, since the fabrication of the conductive pillars is earlier than the formation of the encapsulant, the thickness of the encapsulant does not affect the fabrication yield of the conductive pillars.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
圖1A至圖1D是依照本發明第一實施例的一種晶片封裝體的製造流程示意圖。首先,請參照圖1A,提供一已形成有導電柱220的線路載板210,其中線路載板210具有第一表面210a以及第二表面210b,且導電柱220位於線路載板210之第一表面210a上。具體而言,線路載板210包括一核心層212、導體C、第一接墊212a、第二接墊212b、第一防焊層214a以及第二防焊層214b,其中核心層212為硬質或可撓性之介電材料,第一接墊212a與第二接墊212b分別位於核心層212的二相對表面S1、S2上,且第一接墊212a分別與透過嵌於核心層212中的導體C與對應的第二接墊212b電性連接。第一防焊層214a與第二防焊層214b分別覆蓋於核心層212的二相對表面S1、S2上,並暴露出第一接墊212a與第二接墊212b。在一實施例中,導電柱220位於線路載板210的核心層212之表面S1上,且導電柱220例如是嵌於第一防焊層214a中。然而,本揭露不限定導電柱220必須嵌於第一防焊層214a中。換言之,在其他實施例中,導電柱220可以是配置於線路載板210(即第一防焊層214a)的第一表面210a上。或者,導電柱220除了可嵌於第一防焊層214a中,還可進一步嵌於或延伸至核心層212中。1A to 1D are schematic views showing a manufacturing process of a chip package in accordance with a first embodiment of the present invention. First, referring to FIG. 1A, a circuit carrier 210 having a conductive pillar 220 formed thereon, wherein the wiring carrier 210 has a first surface 210a and a second surface 210b, and the conductive pillar 220 is located on the first surface of the wiring carrier 210. On 210a. Specifically, the line carrier 210 includes a core layer 212, a conductor C, a first pad 212a, a second pad 212b, a first solder resist layer 214a, and a second solder resist layer 214b, wherein the core layer 212 is hard or For the flexible dielectric material, the first pads 212a and the second pads 212b are respectively located on the opposite surfaces S1 and S2 of the core layer 212, and the first pads 212a and the conductors embedded in the core layer 212 are respectively C is electrically connected to the corresponding second pad 212b. The first solder resist layer 214a and the second solder resist layer 214b respectively cover the opposite surfaces S1 and S2 of the core layer 212, and expose the first pads 212a and the second pads 212b. In one embodiment, the conductive pillars 220 are located on the surface S1 of the core layer 212 of the line carrier 210, and the conductive pillars 220 are embedded, for example, in the first solder resist layer 214a. However, the present disclosure does not limit that the conductive pillars 220 must be embedded in the first solder resist layer 214a. In other words, in other embodiments, the conductive pillars 220 may be disposed on the first surface 210a of the line carrier 210 (ie, the first solder resist layer 214a). Alternatively, the conductive pillars 220 may be embedded or extended into the core layer 212 in addition to being embedded in the first solder mask layer 214a.
在本實施例中,線路載板210例如是具有單層線路之印刷電路板或具有多層線路之印刷電路板。前述的線路載板210可為硬質線路載板或可撓性線路載板。第一接墊212a及第二接墊212b的材料例如是銅、鎳、金、錫或上述之組合,第一防焊層214a以及第二防焊層214b的材料例如是環氧樹酯或其他防焊材質,而導電柱220的材料例如是銅或銅合金。In the present embodiment, the line carrier 210 is, for example, a printed circuit board having a single layer of wiring or a printed circuit board having a plurality of layers. The aforementioned line carrier 210 may be a hard line carrier or a flexible line carrier. The materials of the first pads 212a and the second pads 212b are, for example, copper, nickel, gold, tin or a combination thereof, and the materials of the first solder resist layer 214a and the second solder resist layer 214b are, for example, epoxy resin or other materials. The solder resist material, and the material of the conductive pillar 220 is, for example, copper or a copper alloy.
接著,請參考圖1B,將晶片230置於線路載板210的第一表面210a上,以使晶片230與導電柱220位於線路載板230的同一側,接著,透過至少一焊線240使晶片230與線路載板210上的第一接墊212a電性連接。Next, referring to FIG. 1B, the wafer 230 is placed on the first surface 210a of the line carrier 210 such that the wafer 230 and the conductive post 220 are on the same side of the line carrier 230, and then the wafer is passed through at least one bonding wire 240. 230 is electrically connected to the first pad 212a on the line carrier 210.
如圖1B所示,前述之導電柱220、晶片230及焊線240皆位於線路載板210的同一側。在一實施例中,晶片230配置於防焊層214a的表面上。在完成晶片230與線路載板210的接合之後,晶片230會透過線路載板210內之導體C與導電柱220電性連接。As shown in FIG. 1B, the conductive pillar 220, the wafer 230 and the bonding wire 240 are all located on the same side of the line carrier 210. In an embodiment, the wafer 230 is disposed on the surface of the solder resist layer 214a. After the bonding of the wafer 230 and the line carrier 210 is completed, the wafer 230 is electrically connected to the conductive post 220 through the conductor C in the line carrier 210.
在完成晶片230與線路載板210的接合之後,接著,於線路載板210上形成封裝膠體250,以包覆導電柱220及晶片230。具體而言,前述的封裝膠體250除了包覆導電柱220及晶片230之外,可進一步包覆焊線240以及被防焊層214a所暴露的第一接墊212a。在本實施例中,晶片230例如通訊晶片,焊線240例如金線,而封裝膠體250例如是以射出成型(mold injection)的方式製作,且晶片230的厚度及焊線240弧高決定了所欲形成之封裝膠體250的厚度T1。此處,封裝膠體250的厚度T1足以覆蓋住導電柱220的頂面220a。After the bonding of the wafer 230 to the line carrier 210 is completed, an encapsulant 250 is then formed on the line carrier 210 to encapsulate the conductive pillars 220 and the wafers 230. Specifically, the foregoing encapsulant 250 can further cover the bonding wire 240 and the first pad 212a exposed by the solder resist layer 214a, in addition to the conductive pillar 220 and the wafer 230. In this embodiment, the wafer 230 is, for example, a communication chip, the bonding wire 240 is, for example, a gold wire, and the encapsulant 250 is formed by, for example, injection molding, and the thickness of the wafer 230 and the arc height of the bonding wire 240 determine the height. The thickness T1 of the encapsulant 250 to be formed. Here, the thickness T1 of the encapsulant 250 is sufficient to cover the top surface 220a of the conductive pillar 220.
在完成封裝膠體250的製作之後,本實施例可於線路載板210的第二表面210b上形成外部端子216,其中外部端子216與被防焊層214b所暴露出的第二接墊214電性連接。舉例而言,外部端子216可為焊球、凸塊等,且晶片230可透過焊線240、第一接墊212a、導體C、第二接墊212b以及外部端子216與外部元件電性連接。After the fabrication of the encapsulant 250 is completed, the embodiment can form an external terminal 216 on the second surface 210b of the line carrier 210, wherein the external terminal 216 is electrically connected to the second pad 214 exposed by the solder resist layer 214b. connection. For example, the external terminal 216 can be a solder ball, a bump, or the like, and the wafer 230 can be electrically connected to the external component through the bonding wire 240, the first pad 212a, the conductor C, the second pad 212b, and the external terminal 216.
然後,請參考圖1C,移除部分的封裝膠體250,直到導電柱220的頂面220a被暴露。在本實施例中,封裝膠體250可藉由研磨製程、蝕刻製程或其他製程進行薄化,以形成封裝膠體250’。值得注意的是,當厚度為T1之封裝膠體250被薄化而成為封裝膠體250’時,封裝膠體250’的厚度為T2。。Then, referring to FIG. 1C, a portion of the encapsulant 250 is removed until the top surface 220a of the conductive post 220 is exposed. In this embodiment, the encapsulant 250 can be thinned by a polishing process, an etching process, or other processes to form the encapsulant 250'. It is to be noted that when the encapsulant 250 having a thickness T1 is thinned to become the encapsulant 250', the encapsulant 250' has a thickness T2. .
請參考圖1D,在形成封裝膠體250’之後,接著於封裝膠體250’上形成一導電層270,此導電層270與導電柱220的頂面220a連接,使導電層270透過導電柱220、線路載板210與晶片230電性連接。此外,在本實施例中,形成導電層270的方法例如是電鍍、濺鍍或其他適當的成膜製程,導電層270的材料例如是金屬。在本實施例中,導電層270可作為天線層。Referring to FIG. 1D, after forming the encapsulant 250', a conductive layer 270 is formed on the encapsulant 250'. The conductive layer 270 is connected to the top surface 220a of the conductive pillar 220, and the conductive layer 270 is transmitted through the conductive pillar 220 and the wiring. The carrier 210 is electrically connected to the wafer 230. Further, in the present embodiment, the method of forming the conductive layer 270 is, for example, electroplating, sputtering, or other suitable film forming process, and the material of the conductive layer 270 is, for example, a metal. In the present embodiment, the conductive layer 270 can function as an antenna layer.
在本實施例中,如圖1C與圖1D所示,由於導電柱220可預先行製作並設置於線路載板210上,因此本實施例可精準地控制導電柱220的頂面220a之平整度,以使頂面220a與薄化後的封裝膠體250’的頂面切齊(實質上共平面),進而使得後續形成之導電層270能夠順利地與導電柱220的頂面220a電性連接。在導電柱220的頂面220a之平整度獲得良好控制的情況下,導電層270與導電柱220的頂面220a會形成良好的歐姆接觸,使得整體的封裝信賴性獲得提升。In this embodiment, as shown in FIG. 1C and FIG. 1D, since the conductive post 220 can be pre-made and disposed on the line carrier 210, the embodiment can accurately control the flatness of the top surface 220a of the conductive post 220. The top surface 220a is aligned with the top surface of the thinned encapsulant 250' (substantially coplanar), so that the subsequently formed conductive layer 270 can be electrically connected to the top surface 220a of the conductive post 220. In the case where the flatness of the top surface 220a of the conductive pillar 220 is well controlled, the conductive layer 270 forms a good ohmic contact with the top surface 220a of the conductive pillar 220, so that the overall package reliability is improved.
經過上述製程後即可大致上完成本實施例之晶片封裝體200的製作。上述之晶片封裝體200包括線路載板210、導電柱220、晶片230、焊線240、封裝膠體250’、導電層270及外部端子216。線路載板210具有第一表面210a以及第二表面210b,且導電柱220、晶片230、焊線240、封裝膠體250’及導電層270位於線路載板210之第一表面210a上,外部端子216位於線路載板210之第二表面210b上。在一實施例中,線路載板210包括一核心層212、導體C、第一接墊212a、第二接墊212b、第一防焊層214a以及第二防焊層214b,第一接墊212a與第二接墊212b分別位於核心層212的二相對表面S1、S2上,且第一接墊212a分別與透過嵌於核心層212中的導體C與對應的第二接墊212b電性連接。晶片230透過至少一焊線240與被防焊層214a所暴露出的第一接墊214電性連接。外部端子216與被防焊層214b所暴露出的第二接墊214電性連接。因此,晶片230透過至少一焊線240、第一接墊212a、導體C、第二接墊212b以及外部端子216與外部元件電性連接。封裝膠體250’配置於線路載板上,除了包覆晶片230及導電柱220,可進一步包覆焊線240以及被防焊層214a所暴露的第一接墊212a,並使導電柱220暴露出導電柱220的一頂面220a。導電層270配置於封裝膠體250’上,使導電層270接觸導電柱220的一頂面220a,且透過導電柱220、線路載板210與晶片230電性連接。After the above process, the fabrication of the chip package 200 of the present embodiment can be substantially completed. The chip package 200 described above includes a wiring carrier 210, a conductive pillar 220, a wafer 230, a bonding wire 240, an encapsulant 250', a conductive layer 270, and an external terminal 216. The line carrier 210 has a first surface 210a and a second surface 210b, and the conductive post 220, the wafer 230, the bonding wire 240, the encapsulant 250' and the conductive layer 270 are located on the first surface 210a of the line carrier 210, and the external terminal 216 Located on the second surface 210b of the line carrier 210. In one embodiment, the line carrier 210 includes a core layer 212, a conductor C, a first pad 212a, a second pad 212b, a first solder resist layer 214a, and a second solder resist layer 214b. The first pad 212a The second pads 212b are respectively disposed on the opposite surfaces S1 and S2 of the core layer 212, and the first pads 212a are electrically connected to the conductors C embedded in the core layer 212 and the corresponding second pads 212b. The wafer 230 is electrically connected to the first pad 214 exposed by the solder resist layer 214a through at least one bonding wire 240. The external terminal 216 is electrically connected to the second pad 214 exposed by the solder resist layer 214b. Therefore, the wafer 230 is electrically connected to the external component through the at least one bonding wire 240, the first pad 212a, the conductor C, the second pad 212b, and the external terminal 216. The encapsulant 250 ′ is disposed on the line carrier board. In addition to the packaged wafer 230 and the conductive post 220 , the bonding wire 240 and the first pad 212 a exposed by the solder resist layer 214 a may be further covered and the conductive post 220 is exposed. A top surface 220a of the conductive post 220. The conductive layer 270 is disposed on the encapsulant 250', and the conductive layer 270 is in contact with a top surface 220a of the conductive post 220, and is electrically connected to the wafer 230 through the conductive post 220 and the line carrier 210.
以下將以不同的實施例來說明晶片封裝體的製造流程。在此必須說明的是,下述實施例延用前述實施例的元件標號與部分內容,其中採用相同的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可以參考前述實施例,下述實施例不再重述。The manufacturing process of the chip package will be described below in different embodiments. It is to be noted that the following embodiments are to be given the same or similar elements in the foregoing embodiments, and the same reference numerals are used to denote the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.
圖2A至圖2D是依照本發明第二實施例的一種晶片封裝體的製造流程示意圖。首先,請參照圖1A、圖1B、圖2A以及圖2B,本實施例中具有導電柱220’的線路載板210與圖1A及圖1B中所繪示之具有導電柱220的線路載板210相似,二者之間不同之處在於:本實施例(圖2A及圖2B)中形成於線路載板210上的導電柱220’較導電柱220(圖1A與圖1B)為短。2A to 2D are schematic views showing a manufacturing process of a chip package in accordance with a second embodiment of the present invention. First, referring to FIG. 1A, FIG. 1B, FIG. 2A and FIG. 2B, the line carrier 210 having the conductive pillars 220' in this embodiment and the line carrier 210 having the conductive pillars 220 illustrated in FIGS. 1A and 1B are used. Similarly, the difference between the two is that the conductive post 220' formed on the line carrier 210 in this embodiment (Figs. 2A and 2B) is shorter than the conductive post 220 (Figs. 1A and 1B).
然後,請參考圖2C,在完成封裝膠體251的製作之後,在封裝膠體251中形成接觸開口252,此接觸開口252暴露出導電柱220’的頂面220a。接著,於接觸開口252中填入接觸導體260,此處,接觸導體260與導電柱220’電性連接。本實施例可藉由蝕刻、研磨鑽孔、雷射鑽孔或其他製程於封裝膠體251中形成接觸開口252。此外,接觸導體260的材料例如是錫膏、銀漿、或其他融點低於導電柱220’材料的導電物質。Then, referring to FIG. 2C, after the fabrication of the encapsulant 251 is completed, a contact opening 252 is formed in the encapsulant 251, which exposes the top surface 220a of the conductive post 220'. Next, a contact conductor 260 is filled in the contact opening 252, where the contact conductor 260 is electrically connected to the conductive post 220'. This embodiment can form the contact opening 252 in the encapsulant 251 by etching, grinding drilling, laser drilling or other processes. Further, the material of the contact conductor 260 is, for example, a solder paste, a silver paste, or other conductive material having a lower melting point than the material of the conductive post 220'.
在本實施例中,如圖2B與圖2C所示,由於導電柱220’可預先製作並設置於線路載板210上,因此本實施例在形成封裝膠體251中的接觸開口252時,將可有效減少封裝膠體251中接觸開孔252的深寬比(aspect ratio),使得製程時間縮短,進而增加產能。In this embodiment, as shown in FIG. 2B and FIG. 2C, since the conductive post 220' can be pre-made and disposed on the line carrier 210, the present embodiment will be formed when the contact opening 252 in the encapsulant 251 is formed. Effectively reducing the aspect ratio of the contact opening 252 in the encapsulant 251, the process time is shortened, thereby increasing the throughput.
請參考圖2D,在填入接觸導體260後,接著於封裝膠體251上形成一導電層270,以使導電層270透過接觸導體260、導電柱220以及線路載板210而與晶片230電性連接。Referring to FIG. 2D, after the contact conductor 260 is filled, a conductive layer 270 is formed on the encapsulant 251 to electrically connect the conductive layer 270 to the wafer 230 through the contact conductor 260, the conductive post 220, and the line carrier 210. .
在本實施例中,如圖2C與圖2D所示,前述的接觸導體260於填入開口後,接觸導體260會有一頂面260a,其中頂面260a不會被封裝膠體251所包覆,進而使得後續形成之導電層270能夠順利地與接觸導體260的頂面260a電性連接。In this embodiment, as shown in FIG. 2C and FIG. 2D, after the contact conductor 260 is filled in the opening, the contact conductor 260 has a top surface 260a, wherein the top surface 260a is not covered by the encapsulant 251, and further The subsequently formed conductive layer 270 can be electrically connected to the top surface 260a of the contact conductor 260 smoothly.
經過上述製程後即可大致上完成本實施例之晶片封裝體200’的製作。上述之晶片封裝體200’包括線路載板210、導電柱220、晶片230、焊線240、封裝膠體251、接觸導體260、導電層270及外部端子216。線路載板210具有第一表面210a以及第二表面210b,且導電柱220、晶片230、焊線240、封裝膠體251、接觸導體260及導電層270位於線路載板210之第一表面210a上,外部端子216位於線路載板210之第二表面210b上。在一實施例中,線路載板210包括一核心層212、導體C、第一接墊212a、第二接墊212b、第一防焊層214a以及第二防焊層214b,第一接墊212a與第二接墊212b分別位於核心層212的二相對表面S1、S2上,且第一接墊212a分別與透過嵌於核心層212中的導體C與對應的第二接墊212b電性連接。晶片230透過至少一焊線240與被防焊層214a所暴露出的第一接墊214電性連接。外部端子216與被防焊層214b所暴露出的第二接墊214電性連接。因此,晶片230透過至少一焊線240、第一接墊212a、導體C、第二接墊212b以及外部端子216與外部元件電性連接。封裝膠體251配置於線路載板210上,除了包覆晶片230、接觸導體260及導電柱220,可進一步包覆焊線240以及被防焊層214a所暴露的第一接墊212a,並使接觸導體260暴露出接觸導體260的一頂面260a。導電層270配置於封裝膠體251上,使導電層270接觸接觸導體260,且透過導電柱220、線路載板210與晶片230電性連接。After the above process, the fabrication of the chip package 200' of the present embodiment can be substantially completed. The chip package 200' described above includes a wiring carrier 210, a conductive pillar 220, a wafer 230, a bonding wire 240, an encapsulant 251, a contact conductor 260, a conductive layer 270, and an external terminal 216. The line carrier 210 has a first surface 210a and a second surface 210b, and the conductive post 220, the wafer 230, the bonding wire 240, the encapsulant 251, the contact conductor 260, and the conductive layer 270 are located on the first surface 210a of the line carrier 210. The external terminal 216 is located on the second surface 210b of the line carrier 210. In one embodiment, the line carrier 210 includes a core layer 212, a conductor C, a first pad 212a, a second pad 212b, a first solder resist layer 214a, and a second solder resist layer 214b. The first pad 212a The second pads 212b are respectively disposed on the opposite surfaces S1 and S2 of the core layer 212, and the first pads 212a are electrically connected to the conductors C embedded in the core layer 212 and the corresponding second pads 212b. The wafer 230 is electrically connected to the first pad 214 exposed by the solder resist layer 214a through at least one bonding wire 240. The external terminal 216 is electrically connected to the second pad 214 exposed by the solder resist layer 214b. Therefore, the wafer 230 is electrically connected to the external component through the at least one bonding wire 240, the first pad 212a, the conductor C, the second pad 212b, and the external terminal 216. The encapsulant 251 is disposed on the line carrier 210. In addition to the package wafer 230, the contact conductor 260 and the conductive post 220, the bonding wire 240 and the first pad 212a exposed by the solder resist layer 214a may be further covered and contacted. Conductor 260 exposes a top surface 260a of contact conductor 260. The conductive layer 270 is disposed on the encapsulant 251 such that the conductive layer 270 contacts the contact conductor 260 and is electrically connected to the wafer 230 through the conductive post 220 and the line carrier 210.
綜上所述,本發明上述實施例在形成封裝膠體之前先於線路載板上形成導電柱,此製程順序可以提升晶片封裝製程的封裝良率。此外,由於導電柱的製作早於封裝膠體的形成,因此封裝膠體的厚度不會影響到導電柱的製作良率。In summary, the above embodiment of the present invention forms a conductive pillar on the line carrier before forming the package, and the process sequence can improve the package yield of the wafer package process. In addition, since the fabrication of the conductive pillars is earlier than the formation of the encapsulant, the thickness of the encapsulant does not affect the fabrication yield of the conductive pillars.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
200、200’‧‧‧晶片封裝體200, 200'‧‧‧ chip package
210‧‧‧線路載板210‧‧‧Line carrier
210a‧‧‧第一表面210a‧‧‧ first surface
210b、 210b‧‧‧第二表面210b, 210b‧‧‧ second surface
S1、S2‧‧‧表面S1, S2‧‧‧ surface
212a‧‧‧第一接墊212a‧‧‧first mat
212b‧‧‧第二接墊212b‧‧‧second mat
214a‧‧‧第一防焊層214a‧‧‧First solder mask
214b‧‧‧第二防焊層214b‧‧‧Second solder mask
C‧‧‧導體C‧‧‧ conductor
216‧‧‧外部端子216‧‧‧External terminals
220、220’‧‧‧導電柱220, 220'‧‧‧ conductive column
H、H’‧‧‧高度H, H’‧‧‧ Height
220a‧‧‧頂面220a‧‧‧ top
230‧‧‧晶片230‧‧‧ wafer
240‧‧‧焊線240‧‧‧welding line
250、250’、251‧‧‧封裝膠體250, 250', 251‧‧ ‧ encapsulant
252‧‧‧接觸開口252‧‧‧Contact opening
T1、T2、T3‧‧‧厚度T1, T2, T3‧‧‧ thickness
260‧‧‧接觸導體260‧‧‧Contact conductor
260a‧‧‧頂面260a‧‧‧ top
270‧‧‧導電層270‧‧‧ Conductive layer
圖1A至圖1D是依照本發明第一實施例的一種晶片封裝體的製造流程示意圖。 圖1D是依照本發明第一實施例的晶片封裝體的剖面示意圖。 圖2A至圖2D是依照本發明第二實施例的一種晶片封裝體的製造流程示意圖。 圖2D是依照本發明第二實施例的晶片封裝體的剖面示意圖。1A to 1D are schematic views showing a manufacturing process of a chip package in accordance with a first embodiment of the present invention. 1D is a schematic cross-sectional view of a chip package in accordance with a first embodiment of the present invention. 2A to 2D are schematic views showing a manufacturing process of a chip package in accordance with a second embodiment of the present invention. 2D is a schematic cross-sectional view of a chip package in accordance with a second embodiment of the present invention.
200‧‧‧晶片封裝體 200‧‧‧ chip package
210‧‧‧線路載板 210‧‧‧Line carrier
212‧‧‧核心層 212‧‧‧ core layer
210a‧‧‧第一表面 210a‧‧‧ first surface
210b‧‧‧第二表面 210b‧‧‧ second surface
S1、S2‧‧‧表面 S1, S2‧‧‧ surface
212a‧‧‧第一接墊 212a‧‧‧first mat
212b‧‧‧第二接墊 212b‧‧‧second mat
214a‧‧‧第一防焊層 214a‧‧‧First solder mask
214b‧‧‧第二防焊層 214b‧‧‧Second solder mask
216‧‧‧外部端子 216‧‧‧External terminals
220‧‧‧導電柱 220‧‧‧conductive column
220a‧‧‧頂面 220a‧‧‧ top
230‧‧‧晶片 230‧‧‧ wafer
240‧‧‧焊線 240‧‧‧welding line
250‧‧‧封裝膠體 250‧‧‧Package colloid
270‧‧‧導電層 270‧‧‧ Conductive layer
C‧‧‧導體 C‧‧‧ conductor
H‧‧‧高度 H‧‧‧ Height
T2‧‧‧厚度 T2‧‧‧ thickness
Claims (11)
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TW105113070A TWI590349B (en) | 2016-04-27 | 2016-04-27 | Chip package and chip packaging process |
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