TWI556368B - Chip package structure and manufacturing method thereof - Google Patents

Description

Chip package structure and manufacturing method thereof

The present invention relates to a chip package structure, and more particularly to a chip package structure and a method of fabricating the same.

Semiconductor packaging technology includes many package types. Among them, the quad flat no-lead (QFN) package belonging to the quad flat package series has a short signal transmission path and a relatively fast signal transmission speed, so it is always a low pin number (low). Pin count) One of the mainstream of the configuration type.

Generally, in the manufacturing process of a quad flat no-lead package, the wafer is first placed on the lead frame, and the wafer is electrically connected to the wafer by wire bonding or flip chip bonding. Lead frame. Thereafter, the chip disposed on the lead frame and the electrical contacts between the wafer and the lead frame are covered by the encapsulant. In the above package structure, when the lead frame is disposed on the circuit board or other electronic components, the wafer can only be electrically connected to the circuit board or other electronic components through the lead frame. In other words, existing quad flat no-lead packages exist externally to the board or other The number of terminals of the sub-element is insufficient.

For example, it is currently known to form a plurality of solder balls on a wafer to increase the number of terminals externally connected to a circuit board or other electronic component in a quad flat no-lead package. In order to expose the solder balls to the outside of the package rubber as an external terminal, the encapsulation colloid covering the solder balls and the lead frame is further removed by mechanical grinding, so that the solder ball can expose a part of the cross-sectional area for subsequent connection. Terminal used. Although, by forming a plurality of solder balls on the wafer and exposing the solder balls to the outside of the package, the purpose of increasing the number of external terminals of the quad flat no-lead package can be achieved, however, in order to avoid formation of the solder balls. Bridging, so there should be a large pitch between any two adjacent solder balls. In addition, the size of the solder balls has a certain degree of limitation, otherwise the solder balls will be formed on the wafer. The case where any two adjacent solder balls are interconnected. Under the strict requirements of micro-pitch, the above packaging technology and package structure do not meet the requirements of fine pitch of high-density semiconductor package.

The present invention provides a chip package structure and a method of fabricating the same to meet the micro-pitch requirements of high-density semiconductor packages.

The present invention provides a wafer package structure including a wafer, a lead frame, and an encapsulant. The wafer has an active surface and a plurality of first conductive pillars and a plurality of second conductive pillars on the active surface. The leadframe has multiple internal pins. The wafer is placed on the lead frame. In the wafer configuration area of the lead frame, each of the first conductive posts is bonded to the pair The inner pins are intended, and each of the second conductive posts is located between the inner pins. The ends of the respective first conductive pillars and the ends of the respective second conductive pillars are respectively provided with a conductive material. An encapsulant-coated wafer, the first conductive pillars, the second conductive pillars, and the inner leads, wherein the encapsulant has a plurality of openings corresponding to the second conductive pillars to expose the second conductive portions A portion of the conductive material at the end of the column.

The present invention provides a method of fabricating a chip package structure, which includes the following step. First, a wafer is provided. This wafer has an active surface. Then, a plurality of first conductive pillars and a plurality of second conductive pillars are formed on the active surface, and a conductive material is further formed at an end of each of the first conductive pillars and an end of each of the second conductive pillars. Next, a lead frame is provided. This leadframe has multiple internal pins. The wafers are disposed on the leadframe such that the respective first conductive pillars are bonded to the corresponding inner leads in the wafer configuration region of the leadframe, and each of the second conductive pillars is located between the inner leads. Next, an encapsulant is formed to encapsulate the wafer, the first conductive pillars, the second conductive pillars, and the inner leads. Thereafter, a plurality of openings are formed in the encapsulant to expose portions of the electrically conductive material at the ends of the respective second electrically conductive posts.

The present invention provides a method of fabricating a chip package structure, which includes the following step. First, a wafer is provided. This wafer has an active surface. Then, a plurality of first conductive pillars and a plurality of second conductive pillars are formed on the active surface, and a first conductive material is further formed at the ends of the respective first conductive pillars. Next, a lead frame is provided. This leadframe has multiple internal pins. Next, the wafer is placed on the lead frame such that each of the first conductive posts is bonded to the corresponding inner lead in the wafer configuration area of the lead frame, and each of the second conductive posts is located between the inner leads. Forming an encapsulant to coat the wafer, These first conductive pillars, the second conductive pillars, and the inner leads. Next, a plurality of openings are formed in the encapsulant to expose the ends of the respective second conductive posts. Thereafter, a second conductive material is formed in each of the openings to connect the ends of the corresponding second conductive pillars, wherein each of the openings is filled with a corresponding second conductive material.

Based on the above, the present invention first forms a plurality of first conductive pillars and a plurality of second conductive pillars on the active surface of the wafer, wherein the first conductive pillars are used as connection leadframes, and the second conductive pillars are used as subsequent connections. External terminal for external electronic components. After bonding the respective first conductive posts to the corresponding inner leads of the leadframe, the respective second conductive posts having a height higher than the first conductive posts may extend to the hollow defined by the inner leads and substantially The bottom of the lead frame is not exceeded. Then, after the wafer, the first conductive pillar, the second conductive pillar and the inner lead are covered by the encapsulant, the encapsulant covering the end of each of the second conductive pillars is removed to form a plurality of openings, thereby exposing each The end of the second conductive post. Thereafter, the lead frame is disposed on the circuit board, and the conductive material or the combination of the conductive material and the solder in each of the openings is reflowed to form a conductive contact between the electrically connected circuit board and the corresponding second conductive post.

In other words, the wafer package structure obtained through the above manufacturing process may be electrically connected to the circuit board through the lead frame and the second conductive pillar formed on the active surface, and any two adjacent first conductive pillars and the first There may be a small spacing between the two conductive pillars or between any two adjacent second conductive pillars, so that the chip package structure can not only increase the number of external terminals thereof, but also meet the requirements of the fine pitch of the high-density semiconductor package.

In order to make the above features and advantages of the present invention more apparent, the following is a special The embodiments are described in detail below in conjunction with the drawings.

100, 100A‧‧‧ chip package structure

110‧‧‧ wafer

111‧‧‧Active surface

112‧‧‧Back

113‧‧‧ side surface

120‧‧‧First conductive column

121, 131‧‧‧ end

130‧‧‧Second conductive column

140, 141‧‧‧ conductive materials

140a, 141a, 141b‧‧‧ conductive contacts

150‧‧‧ lead frame

151‧‧‧ pin

152‧‧‧ wafer configuration area

153‧‧‧镂空部

154‧‧‧ bottom

160‧‧‧Package colloid

161‧‧‧Opening

170‧‧‧ solder

180‧‧‧ boards

191‧‧‧ tin

192‧‧‧ solder paste

D1, D2‧‧‧ spacing

1A to 1F are schematic diagrams showing a manufacturing process of a chip package structure according to an embodiment of the present invention.

2A to 2F are schematic diagrams showing a manufacturing process of a chip package structure according to an embodiment of the present invention.

1A to 1F are diagrams showing fabrication of a chip package structure according to an embodiment of the present invention; FIG. 1B also illustrates a bottom view of the plurality of first conductive pillars and the second conductive pillars after the active surface of the wafer. Referring first to FIG. 1A, a wafer 110 is provided in which the wafer 110 has an active surface 111, a back surface relative to the active surface 111, and a side surface 113 connecting the active surface 111 and the back surface. Next, referring to FIG. 1B, a plurality of first conductive pillars 120 and a plurality of second conductive pillars 130 are formed on the active surface 111, and conductive materials 140 and second portions are further formed at the end portions 121 of the respective first conductive pillars 120. The end 131 of the conductive post 130 further forms a conductive material 141. Generally, the first conductive pillars 120 and the second conductive pillars 130 can be formed on the active surface 111 by sputtering, printing, electroplating, electroless plating or electrochemical deposition (ECD), and the conductive material 140 and the conductive material are electrically conductive. The material 141 can be formed on the end portion 121 of the corresponding first conductive pillar 120 and the corresponding portion by plating or printing, respectively. The ends 131 of the two conductive pillars 130.

Here, each of the first conductive pillars 120 is closer to the side surface 113 than each of the second conductive pillars 130. In other words, the first conductive pillars 120 are disposed near the periphery of the wafer, and the second conductive pillars 130 are disposed at the center of the wafer with respect to the first conductive pillars 120. Therefore, the first conductive pillars 120 are, for example, circumferentially disposed on the first The circumference of the two conductive pillars 130. In detail, the first conductive pillar 120 is mainly used as the connecting lead frame 150 (shown in FIG. 1C ), and the second conductive pillar 130 is used as an external terminal for connecting the external electronic components, so each of the first conductive pillars 120 The height is, for example, lower than the height of each of the second conductive pillars 130. On the other hand, the spacing D1 between any two adjacent first conductive pillars 120 and the second conductive pillars 130 or the spacing D2 between any two adjacent second conductive pillars 130 is, for example, between 50 micrometers and 200 micrometers. between. Compared with the prior art, a plurality of solder balls are formed on a wafer to improve the number of terminals of the quad flat no-lead package externally connected to the circuit board or other electronic components, and the present embodiment forms a plurality of layers on the active surface 111. A conductive pillar 120 and a plurality of second conductive pillars 130 can be arranged between any two adjacent first conductive pillars 120 and second conductive pillars 130 or between two adjacent second conductive pillars 130 Small spacing to meet the micro-pitch requirements of high-density semiconductor packages.

In the present embodiment, the first conductive pillar 120 and the second conductive pillar 130 are each composed of, for example, copper or a copper alloy, but the invention is not limited thereto. In other embodiments, other conductive metals or metal alloys, such as metals such as gold, silver, and nickel, may be used to form the first conductive pillars 120 and the second conductive pillars 130. On the other hand, the conductive material 140 and the conductive material 141 are each composed of, for example, tin or a tin alloy, but the present invention It is not limited to this. In other embodiments, other conductive metals or metal alloys may be used to form the conductive material 140 and the end 131 of the corresponding second conductive pillar 130 at the end 121 of the corresponding first conductive pillar 120 to form a conductive portion. Material 141.

Next, referring to FIG. 1C, a lead frame 150 is provided, wherein the lead frame 150 There are a plurality of inner leads 151 (two are schematically shown), and a wafer arrangement area 152 is commonly defined through the upper surfaces of the plurality of inner leads 151 to collectively receive the wafer 110 and on the respective inner leads 151. The hollow portion 153 is formed by a half etching process to the lower surface of the end portion in the direction in which the wafer 110 extends. Next, the active surface 111 of the wafer 110 faces the lead frame 150 and aligns the respective first conductive posts 120 to the corresponding inner leads 151. Thereafter, the wafer 110 is fixed to the lead frame 150 through a reflow process. At this time, each of the first conductive pillars 120 is bonded to the corresponding inner lead 151 in the wafer arrangement region 152 of the lead frame 150. In detail, the method of bonding the respective first conductive pillars 120 to the corresponding inner leads 151 may include a heat bonding manner such as reflow soldering or ultrasonic thermocompression, wherein the first conductive pillars 120 are located in FIG. 1B. The conductive material 140 of the end portion 121 forms a conductive contact 140a electrically connected to each of the first conductive pillars 120 and the corresponding inner lead 151.

Since each of the second conductive pillars 130 has a higher height than each of the first conductive pillars The height of 120, so after each of the first conductive pillars 120 is bonded to the corresponding inner lead 151, each of the second conductive pillars 130 extends to the hollow portion 153 of the lead frame 150 defined by the inner leads 151. . That is, each of the second conductive pillars 130 will extend from the active surface 111 to the hollow 153 and substantially not beyond the bottom 154 of the leadframe 150. In another embodiment, the height of the first conductive pillar 120 and the second conductive The height of the pillars 130 may be the same height, and the conductive material on the second conductive pillars 130 is thicker than the conductive material on the first conductive pillars 120, so that the second conductive pillars 130 and the conductive materials on the ends 131 thereof The overall height is higher than the overall height of the first conductive pillar 120 and the conductive material on the end portion 121 thereof, so that after the wafer 110 is disposed on the lead frame 150, the conductive material on the second conductive pillar 130 and the end portion 131 thereof is extended to the hollow portion. 153.

Next, referring to FIG. 1D, an encapsulant 160 is formed to encapsulate the wafer 110, the first conductive pillars 120, the second conductive pillars 130, and the inner leads 150. In more detail, the encapsulant 160 encloses the conductive contacts 140a between the respective first conductive pillars 120 and the corresponding inner leads 151, and fills the entire hollow portion 153, and thus will be located at each of the second conductive pillars 130. The conductive material 141 of the end portion 131 is covered. Then, a portion of the encapsulant 160 covering the end 131 of each of the second conductive pillars 130 is removed by, for example, laser drilling to form a plurality of openings 161 corresponding to the ends 131 of the respective second conductive pillars 130. Thereby exposing portions of the conductive material 141 at the ends 131 of the respective second conductive pillars 130.

Referring to FIG. 1E, solder 170 is filled in each of the openings 161, wherein the solder 170 may be made of the same material as the conductive materials 140, 141, such as solder or flux, and fill the respective openings 161.

In the upper plate process, a predetermined amount of tin material 191 may be further formed on the bottom of the lead frame 150, for example, by electroplating. Referring to FIG. 1E and FIG. 1F, a circuit board 180 is provided and the lead frame 150 is disposed on the circuit board 180. At this time, the lead frame 150 is located, for example, between the wafer 110 and the circuit board 180. Then, go back The soldering process is such that the solder 191 located at the bottom of the lead frame 150 is electrically connected to the corresponding conductive contacts 141a on the circuit board 180, and the solder 170, the conductive material 141 and the circuit board 180 located in the respective openings 161. The conductive contacts 141b provided corresponding to the respective openings 161 form an electrical connection. It is to be noted that, as shown in FIG. 1E, the solder bumps 192 may be separately disposed on the conductive contacts 141a, 141b of the circuit board 180, thereby forming a better bond with the lead frame 150. So far, the wafer package structure 100 of the present embodiment has been substantially completed.

In this embodiment, since the wafer 110 of the chip package structure 100 is separable The second conductive pillar 130 formed on the active surface 111 is electrically connected to the circuit board 180, and any two adjacent first conductive pillars 120 and the second conductive pillars 130 are adjacent to each other. The second conductive pillars 130 can have a small pitch between them, so the chip package structure 100 can not only increase the number of external terminals thereof, but also meet the requirements of the fine pitch of the high-density semiconductor package. In addition, the first conductive pillar 120 and the second conductive pillar 130 are made of a metal having a high hardness (for example, copper) by electroplating, so that a metal pillar having a small size and a high melting point can be manufactured. It will be like the problem that the traditional solder ball is easy to overflow when it is welded back and the bridge is short-circuited.

Other embodiments are listed below for illustration. Must be stated here It is to be noted that the following embodiments use the same reference numerals and the parts of the foregoing embodiments, and the same reference numerals are used to refer to the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.

2A to 2F are diagrams showing fabrication of a chip package structure according to an embodiment of the present invention; Schematic diagram of the process. Referring to FIG. 2A and FIG. 2B , in the embodiment, a plurality of first conductive pillars 120 and a plurality of second conductive pillars 130 are formed on the active surface 111 of the wafer 110 and the wafer package structure 100 of the above embodiment. It is roughly the same and will not be described here. The difference is that in the fabrication step shown in FIG. 2B, a conductive material is not formed at the end 131 of each of the second conductive pillars.

Next, referring to FIG. 2C, the first conductive pillars 120 are aligned with the corresponding inner leads 151 to place the wafer 110 on the lead frame 150. At this time, each of the first conductive pillars 120 is bonded to the corresponding inner lead 151 in the wafer arrangement region 152 of the lead frame 150. Then, the conductive material 140 at the end 121 of each of the first conductive pillars 120 as shown in FIG. 2B is reflowed to form conductive contacts 140a electrically connected to the respective first conductive pillars 120 and the corresponding inner leads 151.

Next, referring to FIG. 2D, an encapsulant 160 is formed to encapsulate the wafer 110, the first conductive pillars 120, the second conductive pillars 130, and the inner leads 150. In more detail, the encapsulant 160 encloses the conductive contacts 140a between the respective first conductive pillars 120 and the corresponding inner leads 151, and fills the hollow portions 153, thereby the ends of the respective second conductive pillars 130. 131 is covered. Then, a portion of the encapsulant 160 covering the end 131 of each of the second conductive pillars 130 is removed by, for example, laser drilling to form a plurality of openings 161 corresponding to the ends 131 of the respective second conductive pillars 130. Thereby, the ends 131 of the respective second conductive pillars 130 are exposed.

Next, referring to FIG. 2E, the conductive material 141 is formed in each of the openings 161 by electroplating or printing, for example, the conductive material 141 may be tin or tin alloy, fill each opening 161 and connect the corresponding second conductive pillars 130. End 131. On In the board process, a predetermined amount of tin material 191 may be further formed on the bottom of the lead frame 150, for example, by electroplating. Referring to FIG. 2E and FIG. 2F, the lead frame 150 is disposed on the circuit board 180, and a reflow process is performed to form the solder 191 located at the bottom of the lead frame 150 and the corresponding conductive contacts 141a on the circuit board 180. The electrical connection, and the conductive material 141 in each of the openings 161 are electrically connected to the conductive contacts 141b on the circuit board 180 corresponding to the respective openings 161. It is to be noted that, as shown in FIG. 2E, solder paste 192 may be separately disposed on the conductive contacts 141a, 141b of the circuit board 180, thereby forming a better bond with the lead frame 150. So far, the wafer package structure 100A of the present embodiment has been substantially completed.

In summary, the present invention first forms a plurality of numbers on the active surface of the wafer. A conductive pillar and a plurality of second conductive pillars, wherein the first conductive pillar is used as a connecting lead frame, and the second conductive pillar is used as an external terminal for subsequently connecting external electronic components. After bonding the respective first conductive posts to the corresponding inner leads of the leadframe, the respective second conductive posts having a height higher than the first conductive posts may extend to the hollow defined by the inner leads and substantially The bottom of the lead frame is not exceeded. Then, after the wafer, the first conductive pillar, the second conductive pillar and the inner lead are covered by the encapsulant, the encapsulant covering the end of each of the second conductive pillars is removed to form a plurality of openings, thereby exposing each The end of the second conductive post. Thereafter, the lead frame is disposed on the circuit board, and the conductive material or the combination of the conductive material and the solder in each of the openings is reflowed to form a conductive contact between the electrically connected circuit board and the corresponding second conductive post.

In other words, the wafer package structure obtained through the above manufacturing process can be electrically connected to the lead frame and the second conductive post formed on the active surface. Connected to the circuit board, and between any two adjacent first conductive pillars and second conductive pillars or between any two adjacent second conductive pillars, there may be a small spacing, so that the chip package structure can not only improve its external connection The number of terminals can also meet the requirements of the fine pitch of high-density semiconductor packages.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

110‧‧‧ wafer

120‧‧‧First conductive column

130‧‧‧Second conductive column

131‧‧‧End

140a‧‧‧Electrical contacts

141‧‧‧Electrical materials

150‧‧‧ lead frame

151‧‧‧ pin

153‧‧‧镂空部

160‧‧‧Package colloid

161‧‧‧Opening

Claims (12)

A chip package structure comprising: a wafer having an active surface and a plurality of first conductive pillars and a plurality of second conductive pillars on the active surface; a leadframe having a plurality of inner leads, the wafer being disposed on In the lead frame, in the wafer arrangement area of the lead frame, each of the first conductive posts is bonded to the corresponding inner lead, and each of the second conductive posts is located between the inner leads, wherein each of the first leads An end of a conductive pillar and an end of each of the second conductive pillars are respectively provided with a conductive material; and an encapsulant covering the wafer, the first conductive pillars, the second conductive pillars, and the inner leads a foot, wherein the encapsulant has a plurality of openings corresponding to the second conductive pillars to expose portions of the conductive material on the end of each of the second conductive pillars. The chip package structure of claim 1, wherein the height of each of the first conductive pillars is lower than the height of each of the second conductive pillars. The chip package structure of claim 1, further comprising: a circuit board, wherein the lead frame is disposed on the circuit board, wherein each of the second conductive posts is electrically connected to the circuit through the corresponding conductive material board. The chip package structure of claim 1, wherein the inner leads define a hollow portion of the lead frame, and each of the second conductive posts extends from the active surface into the hollow portion. The chip package structure of claim 1, wherein the first conductive pillars are disposed adjacent to a periphery of the wafer, and the second conductive pillars are opposite to the first conductive pillars. The electric post is placed in the center of the wafer. The wafer package structure of claim 1, wherein a spacing between any two adjacent first conductive pillars and the second conductive pillar or any two adjacent second conductive pillars is 50 Micron to 200 microns. A method of fabricating a chip package structure includes: providing a wafer having an active surface; forming a plurality of first conductive pillars and a plurality of second conductive pillars on the active surface, and each of the first conductive pillars The end portion and the end of each of the second conductive pillars further form a conductive material; a lead frame is provided, the lead frame has a plurality of inner leads; the wafer is disposed on the lead frame, and each of the first conductive pillars is disposed Bonding to the corresponding inner lead in a wafer arrangement region of the lead frame, and each of the second conductive posts is located between the inner leads; forming an encapsulant to encapsulate the wafer, the a conductive pillar, the second conductive pillars and the inner leads; and a plurality of openings formed in the encapsulant to expose portions of the conductive material at the end of each of the second conductive pillars. The method of fabricating a chip package structure according to claim 7, wherein the method of bonding the first conductive pillars to the corresponding inner leads in the wafer configuration region of the lead frame comprises: reflow soldering The conductive material of the end portion of each of the first conductive pillars is formed to electrically connect each of the first conductive pillars with a corresponding conductive contact of the inner lead. The method of fabricating a chip package structure according to claim 7, wherein after the portion of the conductive material at the end of each of the second conductive posts is exposed to the corresponding opening, the method further comprises: filling in a solder is disposed in each of the openings; a circuit board is disposed, and the lead frame is disposed on the circuit board; and the solder and the conductive material located in each of the openings are reflowed to form an electrical connection to the circuit board And a corresponding conductive contact of the second conductive pillar. A method of fabricating a chip package structure includes: providing a wafer having an active surface; forming a plurality of first conductive pillars and a plurality of second conductive pillars on the active surface, and each of the first conductive pillars The end portion further forms a first conductive material; a lead frame is provided, the lead frame has a plurality of inner leads; the wafer is disposed on the lead frame, and each of the first conductive posts is disposed on a wafer of the lead frame The region is bonded to the corresponding inner lead, and each of the second conductive pillars is located between the inner leads; forming an encapsulant to cover the wafer, the first conductive pillars, and the second a conductive pillar and the inner leads; forming a plurality of openings in the encapsulant to expose ends of each of the second conductive pillars; and forming a second conductive material in each of the openings to connect the corresponding The end of the second conductive pillar, wherein each of the openings is filled by the corresponding second conductive material. The manufacturer of the chip package structure as described in claim 10 of the patent application scope The method of bonding the first conductive pillars to the corresponding inner leads in the wafer configuration region of the leadframe includes: reflowing the first conductive traces at the ends of each of the first conductive pillars And a material to form a conductive contact electrically connecting each of the first conductive pillars and the corresponding inner lead. The method of fabricating a chip package structure according to claim 10, wherein after the openings are filled by the corresponding second conductive material, the method further comprises: providing a circuit board, and placing the lead frame on the lead frame And the second conductive material in each of the openings is reflowed to form a conductive contact electrically connected to the circuit board and the corresponding second conductive pillar.