KR100961308B1 - Semiconductor package - Google Patents

Abstract

The present invention relates to a semiconductor package, and a technical problem to be solved is to improve the area of the input / output pattern that is limited when a plurality of stacked semiconductor devices are electrically connected through an interposer and stacked. .

To this end, the present invention provides at least one electrically connecting the first circuit board, the first semiconductor die formed on the first circuit board, the interposer and the interposer formed on the first semiconductor die, and the first circuit board. A first semiconductor device having a first conductive wire and a second semiconductor device formed on top of the first semiconductor device and having a second circuit die formed on top of the second circuit board and a second circuit board electrically connected to the interposer; A semiconductor package comprising a.

Interposers, Package-on-Packages, Semiconductor Dies, Conductive Wires, Semiconductor Packages

Description

Semiconductor Package {SEMICONDUCTOR PACKAGE}

The present invention relates to a semiconductor package, and more particularly, to a semiconductor package, in which a plurality of stacked semiconductor devices are electrically connected through an interposer so that the area of an input / output pattern is limited when the semiconductor devices are stacked. It is about.

With the development of the electronic industry, the demand for high functionalization and miniaturization of electronic components is increasing rapidly. In order to cope with such a demand, one electronic device is mounted on a conventional printed circuit board, and thus a stack package board that stacks and mounts a plurality of electronic devices on one board appears.

In the evolution of the design of package substrates, in order to meet the demand for high speed and high integration, a system in package (SiP) was created. Such SiP is a package in package and a package on package. Are being developed in various forms.

Furthermore, among the various methods of forming a package substrate as the R & D and the demand for the method for realizing the high performance and high density package substrate required in the market, the package on package ( Package on Package (PoP) has emerged as an alternative.

In order to further improve the performance of the PoP, there has been a demand for mounting two or more semiconductor dies in a situation where one semiconductor die is mounted in a top package and a bottom package. However, when two or more semiconductor dies are mounted in the TOP package and the Bottom package, the number of input / output connection terminals between the TOP package and the Bottom package is increased. As the area is limited compared to the number of output / output terminals, the semiconductor package becomes fine pitch, causing problems in connecting the input / output connection terminals between the top package and the bottom package. .

SUMMARY OF THE INVENTION The present invention is to overcome the above-mentioned conventional problems, and an object of the present invention is that a plurality of stacked semiconductor devices are electrically connected through an interposer, so that when the semiconductor devices are stacked, an area of an input / output pattern is limited. It is to provide a semiconductor package that can be improved.

In addition, another object of the present invention is to provide a semiconductor package which can manufacture a semiconductor package having a small size and high functionality by stacking a semiconductor device including a plurality of semiconductor die.

In order to achieve the above object, a semiconductor package according to the present invention includes a first circuit board, a first semiconductor die formed on an upper portion of the first circuit board, an interposer formed on the first semiconductor die, and the interposer; A first semiconductor device having at least one first conductive wire electrically connecting the first circuit board and a second circuit board formed on top of the first semiconductor device and electrically connected to the interposer and the second circuit board; And a second semiconductor device having a second semiconductor die formed on top of the circuit board.

The first circuit board of the first semiconductor device comprises a first insulating layer comprising a first flat surface and a second flat surface opposite to the first surface, and formed on the first surface of the first insulating layer. At least one first wiring pattern electrically connected to the interposer through a semiconductor die or the conductive wire, at least one second wiring pattern formed on a second surface of the first insulating layer, and the first insulating layer. At least one first conductive via penetrating between the first and second surfaces may be electrically connected to the first wiring pattern and the second wiring pattern.

A first circuit board of the first semiconductor device to expose a portion of the first wiring pattern formed on the first surface of the first insulating layer to be electrically connected to the first semiconductor die or the first conductive wire The method may further include a first solder mask and a second solder mask exposing a portion of the second wiring pattern formed on the second surface of the first insulating layer.

The external semiconductor device may further include an external solder ball welded to the second wiring pattern of the first semiconductor device and electrically connected to the first semiconductor device.

The first semiconductor device may further include a first encapsulant that encapsulates an upper portion of the first circuit board, the first semiconductor die, the interposer, and the first conductive wire.

The first semiconductor device is formed inwardly from the top of the first encapsulant, further comprising at least one second conductive via electrically connecting between the interposer and the second circuit board of the second semiconductor device. Can be formed.

The first semiconductor die of the first semiconductor device has a first flat surface and a flat second surface as an opposite surface of the first surface, on which the interposer is seated. At least one conductive bump may be formed.

The interposer of the first semiconductor device is formed on a first surface of the second insulating layer and a second insulating layer formed of a flat first surface and a second flat surface as an opposite surface of the first surface. It may include at least one third wiring pattern electrically connected to the device or the first circuit board.

The first conductive wire may be formed between the third wiring pattern of the interposer and the first circuit board to electrically connect the third wiring pattern and the first circuit board.

The interposer may further include a third solder mask that exposes a portion of the third wiring pattern formed on the first surface of the second insulating layer to be electrically connected to the second semiconductor device or the first circuit board. have.

The second semiconductor die of the second semiconductor device may have a first flat surface and a flat second surface as an opposite surface of the first surface, and at least one bond pad may be formed on the first surface.

The second circuit board of the second semiconductor device has a third insulating layer formed of a first flat surface and a second flat surface opposite to the first surface, and formed on the first surface of the third insulating layer. At least one fourth wiring pattern electrically connected to the bond pad of the second semiconductor die, at least one fifth wiring pattern formed on the second surface of the third insulating layer, and the first surface and the first surface of the third insulating layer. At least one third conductive via may be formed to penetrate between two surfaces to electrically connect the fourth wiring pattern and the fifth wiring pattern.

A fourth solder mask and the third circuit board, wherein the second circuit board of the second semiconductor device exposes a portion of the fourth wiring pattern formed on the first surface of the third insulating layer to be electrically connected to the second semiconductor die. The semiconductor device may further include a fifth solder mask that exposes a portion of the fifth wiring pattern formed on the second surface of the insulating layer to be electrically connected to the interposer.

The second semiconductor device may further include a solder ball formed on the fifth wiring pattern of the second circuit board to electrically connect between the second circuit board and the interposer of the first semiconductor device.

The second semiconductor device may further include a plurality of second conductive wires electrically connecting between the bond pad of the second semiconductor die and the fourth wiring pattern.

The device may further include a second encapsulant for encapsulating the upper portion of the second circuit board, the second semiconductor die, and the second conductive wire.

As described above, in the semiconductor package according to the present invention, a plurality of stacked semiconductor devices are electrically connected through an interposer, so that the area of the input / output pattern is limited when the semiconductor devices are stacked.

In addition, the semiconductor package according to the present invention as described above can be prevented by forming an interposer between the stacked semiconductor devices as the semiconductor package is a fine pitch and the adjacent solder ball is short-circuited.

In addition, as described above, the semiconductor package according to the present invention can stack a semiconductor device including a plurality of semiconductor dies, thereby manufacturing a semiconductor package having miniaturization and high functionality.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the present invention. Here, parts having similar configurations and operations throughout the specification are denoted by the same reference numerals.

Referring to FIG. 1, a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention is illustrated.

As shown in FIG. 1, the semiconductor package 10 includes a first semiconductor device 100 and a second semiconductor device 200.

First, the first semiconductor device 100 may include a first circuit board 110 including a first wiring pattern 112 and a second wiring pattern 116, and a first wiring pattern 112 of the first circuit board 110. A first semiconductor die 120 electrically connected to the first semiconductor die 120, and formed on the first surface 120a of the first insulating layer 111 on the first semiconductor die 12. An interposer 130 including a 132, a first conductive wire 140 electrically connecting the first circuit board 110 and the interposer 130, and an upper portion of the first circuit board 110. And a first encapsulant 150 encapsulating the first semiconductor die 120, the interposer 130, and the first conductive wire 140, and a second of the first circuit board 110. The external solder ball 160 is electrically connected to the wiring pattern 116. The first wiring pattern 112 of the first circuit board 110 is connected to the interposer through the first conductive wire 140. 13 It is electrically connected to the third wiring pattern 132 of 0).

The first circuit board 110 may include a first insulating layer 111, at least one first wiring pattern 112 formed on the first insulating layer 111, and the first wiring pattern 112. A first solder mask 114 exposing a portion, at least one second wiring pattern 116 formed on a surface opposite to a surface on which the first wiring pattern 112 is formed in the first insulating layer 111, and the first A second solder mask 118 exposing a portion of the second wiring pattern 116 and at least one first conductive via 119 electrically connecting the first wiring pattern 112 and the second wiring pattern 116. ) May be included.

The first insulating layer 111 has a flat first surface 111a and a flat second surface 111b as an opposite surface of the first surface 111a.

The first wiring pattern 112 is formed on the first surface 111a of the first insulating layer 111 and the third wiring pattern 132 of the first semiconductor die 120 or the interposer 130. ) Is electrically connected. Copper (Cu), titanium (Ti), nickel (Ni), palladium (Pd), and the like may be used for the first wiring pattern 112, but the metal material is not limited thereto.

The first solder mask 114 is formed at a predetermined thickness on the outer circumference of the first wiring pattern 112 on the first surface 111a of the first insulating layer 111 to form the first wiring pattern 112. ) From the external environment. The first solder mask 114 prevents the position of the conductive bumps 125 from being changed when the conductive bumps 125 of the first semiconductor die 120 are welded to the first wiring patterns 112. . The first solder mask 114 may be formed of any one selected from conventional polyimide, epoxy, BCB (Benzo Cyclo Butene), PBO (Poly Benz Oxazole), and equivalents thereof. It is not intended to limit.

The second wiring pattern 116 is formed on the second surface 111b of the first insulating layer 111 and is electrically connected to the external solder ball 160. Since the second wiring pattern 116 may be made of the same material as the first wiring pattern 112, description of the material is omitted.

The second solder mask 118 is formed to have a predetermined thickness on the outer circumference of the second wiring pattern 116 on the second surface 111b of the first insulating layer 111 to form the second wiring pattern 116. ) From the external environment. The second solder mask 118 prevents the position of the external solder ball 160 from being changed when the external solder ball 160 is welded to the second wiring pattern 116. Since the second solder mask 118 may be made of the same material as the first solder mask 114, a description of the material is omitted.

The first conductive via 119 penetrates between the first surface 111a and the second surface 111b of the first insulating layer 111 to form a first surface 111a of the first insulating layer 111. The first wiring pattern 112 formed on the second wiring pattern 116 formed on the second surface 111b of the first insulating layer 111 is electrically connected to each other.

The first semiconductor die 120 has a flat first surface 120a and a flat second surface 120b as an opposite surface of the first surface 120a, and is formed at least on the second surface 120b. One conductive bump 125 is included. The conductive bumps 125 of the first semiconductor die 120 are electrically connected to the first wiring patterns 112 of the first circuit board 110. The conductive bumps 125 may be formed using any one selected from metal materials such as tin / lead (Pb / Sn), leadless tin (Leadless Sn), and the like, but the material is not limited thereto. . In FIG. 1, the first semiconductor die 120 is illustrated as two semiconductor dies arranged in a horizontal direction. However, at least one of the first semiconductor die 120 may be arranged in a horizontal direction. At least one or more may be stacked, and the present invention does not limit the number and arrangement of the first semiconductor dies 120.

The interposer 130 is formed on the first surface 120a of the first semiconductor die 120 to electrically connect the first circuit board 110 and the second semiconductor device 200. The interposer 130 exposes a second insulating layer 131, at least one third wiring pattern 132 and a portion of the third wiring pattern 132 formed on the second insulating layer 131. The third solder mask 134 may be included.

The second insulating layer 131 includes a flat first surface 131a and a flat second surface 131b as an opposite surface of the first surface 131a.

The third wiring pattern 132 is formed on the first surface 131a of the second insulating layer 131, and the first wiring pattern of the second semiconductor device 200 or the first circuit board 110. Is electrically connected to 112. Since the third wiring pattern 132 may be made of the same material as the first wiring pattern 112 of the first semiconductor device 100, description of the material is omitted.

The third solder mask 134 is formed at a predetermined thickness on the outer circumference of the third wiring pattern 132 on the first surface 131a of the second insulating layer 131, so that the third wiring pattern 132 is formed. ) From the external environment. The third solder mask 134 may prevent the position of the solder ball 350 from being changed when the solder ball 350 of the second semiconductor device 200 is welded to the third wiring pattern 132. have. Since the third solder mask 134 may be made of the same material as the first solder mask 114, a description of the material is omitted.

The first conductive wire 140 electrically connects the first wiring pattern 112 of the first circuit board 100 and the third wiring pattern 132 of the interposer 130 to each other. The first conductive wire 140 is made of any one of gold (Au), aluminum (Al), and copper (Cu) or an alloy thereof, but is not limited thereto. The first conductive wire 140 is preferably formed of gold (Au), and the ductility and electrical conductivity are higher than that of other metals, so that the first conductive wire 140 may be thinly formed. This is because the conductivity is high and easy at the time of wire bonding.

The first encapsulant 150 protects the first circuit board 110, the first semiconductor die 120, the interposer 130, and the first conductive wire 140 from an external environment. Encapsulate them for this purpose. That is, the first encapsulant 150 is formed on the first surface 111a of the first insulating layer 111 in the first circuit board 110 and the first wiring pattern 112 and the first solder mask. 114, the first semiconductor die 120, the interposer 130, and the first conductive wire 140 are encapsulated. At least one of the third wiring patterns 132 of the interposer 130 is exposed to the upper portion of the first encapsulant 150 and is electrically connected to the second semiconductor device 200. In this case, a second conductive via 159 may be further formed in the third wiring pattern 132 of the interposer 130 exposed to the upper portion of the first encapsulant 150. The second conductive via 159 is formed inwardly from the upper portion of the first encapsulant 150 to form the third wiring pattern 132 of the interposer 130 and the second semiconductor device 200. Electrically connect between the solder balls 250 to be described.

In addition, the external solder ball 160 is deposited on the second wiring pattern 116 of the first circuit board 110 to pass through the first conductive via 119 and the first wiring pattern 112. It is electrically connected to the semiconductor die 120 or the interposer 130. The external solder ball 160 may be formed of any one selected from tin / lead, lead-free tin, and equivalents thereof, but is not limited thereto.

The second semiconductor device 200 is electrically connected to the first circuit board 110 through the interposer 130 of the first semiconductor device 100. The second semiconductor device 200 may include a second circuit board 210 including a fourth wiring pattern 212 and a fifth wiring pattern 216, and a fourth wiring pattern 212 of the second circuit board 210. A second semiconductor die 220 electrically connected to the second semiconductor die 220, a second conductive wire 230 electrically connecting the second semiconductor die 220 and the second circuit board 210 to each other, and the second semiconductor die 220. The solder ball 250 electrically connected to the second encapsulant 240 encapsulating the second circuit board 210 and the fifth wiring pattern 216 of the second circuit board 210. It includes.

The second circuit board 210 may include a third insulating layer 211, at least one fourth wiring pattern 212 formed in the third insulating layer 211, and a part of the fourth wiring pattern 212. A fourth solder mask 214 exposing a portion thereof, at least one fifth wiring pattern 216 formed on an opposite surface of the third insulating layer 211 on which the fourth wiring pattern 212 is formed, and the fifth A fifth solder mask 218 exposing a portion of the wiring pattern 216 and at least one third conductive via 219 electrically connecting the fourth wiring pattern 212 and the fifth wiring pattern 216. It may include.

The third insulating layer 211 includes a flat first surface 211a and a flat second surface 211b as an opposite surface of the first surface 211a.

The fourth wiring pattern 212 is formed on the first surface 211a of the third insulating layer 211 and is electrically connected to the second semiconductor die 220 through the second conductive wire 230. do. Since the fourth wiring pattern 212 may be made of the same material as the first wiring pattern 112 of the first semiconductor device 100, description of the material is omitted.

The fourth solder mask 214 is formed at a predetermined thickness on the outer circumference of the fourth wiring pattern 212 on the first surface 211a of the third insulating layer 211, so that the fourth wiring pattern 212 is formed. ) From the external environment. Since the fourth solder mask 214 may be made of the same material as the first solder mask 114 of the first semiconductor device 100, a description of the material is omitted.

The fifth wiring pattern 216 is formed on the second surface 211b of the third insulating layer 211, and the interposer 130 of the first semiconductor device 100 is formed through the solder balls 250. Is electrically connected to the Since the fifth wiring pattern 216 may be made of the same material as the first wiring pattern 112 of the first semiconductor device 100, description of the material is omitted.

The fifth solder mask 218 is formed to have a predetermined thickness on the outer circumference of the fifth wiring pattern 216 on the second surface 211b of the third insulating layer 211 to form the fifth wiring pattern 216. ) From the external environment. The fifth solder mask 218 may prevent the position of the solder ball 250 from being changed along the fifth wiring pattern 216 when the solder balls 250 are welded to the fifth wiring pattern 216. Can be. Since the fifth solder mask 218 may be made of the same material as the first solder mask 114 of the first semiconductor device 100, a description of the material is omitted.

The third conductive via 219 penetrates between the first surface 211a and the second surface 211b of the third insulating layer 211 to form the first surface 211a of the third insulating layer 211. The fourth wiring pattern 212 formed in the second wiring layer 211 formed on the second surface 211b of the third insulating layer 211 is electrically connected to each other.

The second semiconductor die 220 has a flat first surface 220a and a flat second surface 220b as an opposite surface of the first surface 220a, and at least one on the first surface 220a. Bond pads 225 are formed. The bond pad 225 of the second semiconductor die 220 is electrically connected to the fourth wiring pattern 212 of the second circuit board 210 through the second conductive wire 230. In FIG. 1, two second semiconductor dies 220 are stacked in a vertical direction. However, at least one second semiconductor die 220 may be arranged in a horizontal direction, and at least one of the second semiconductor dies 220 may be arranged in a horizontal direction. The above may be stacked, and the present invention is not limited to the number and arrangement of the second semiconductor die 220.

The second conductive wire 230 electrically connects the bond pad 225 of the second semiconductor die 220 and the fourth wiring pattern 212 of the second circuit board 210 to each other. The second conductive wire 230 is made of any one of gold (Au), aluminum (Al), and copper (Cu) or an alloy thereof, but is not limited thereto. The second conductive wire 230 is preferably formed of gold (Au), and has higher ductility and electrical conductivity than other metals, so that the second conductive wire 230 may be thinly formed, and even though the second conductive wire 230 is thin It is because conductivity is high and it is easy at the time of wire bonding.

The second encapsulant 240 encapsulates the second circuit board 210, the second semiconductor die 220, and the second conductive wire 230 to protect them from the external environment. )do. That is, the second encapsulant 240 is formed on the first surface 211a of the third insulating layer 211 in the second circuit board 210 and the fourth wiring pattern 212 and the fourth solder mask. 214, the second semiconductor die 220 and the second conductive wire 230 are encapsulated.

The solder ball 250 is deposited on the fifth wiring pattern 216 of the second circuit board 210, and the second semiconductor is formed through the third conductive via 219 and the fourth wiring pattern 212. Is electrically connected to die 220. The solder ball 250 electrically connects the second semiconductor die 220 and the interposer 130 of the second semiconductor device 200 through the second conductive via 159 to form the second semiconductor. The device 200 is electrically connected to the first semiconductor device 100 through the interposer 130. The solder ball 250 may be formed of any one selected from tin / lead, lead-free tin, and equivalents thereof, but is not limited thereto.

As described above, the semiconductor package 10 is electrically connected between the first semiconductor device 100 and the second semiconductor device 200 through the interposer 130 of the first semiconductor device 100. When the semiconductor device 100 and the second semiconductor device 200 are connected without the interposer 130, the wiring pattern, which is an input / output terminal, may be limited to a certain area. That is, the semiconductor package 10 may connect the first semiconductor device 100 and the second semiconductor device 200 through a large area of the interposer 130 formed in the first semiconductor device 100. have.

In addition, since the semiconductor package 10 electrically connects the first semiconductor device 100 and the second semiconductor device 200 through the interposer 130, the first semiconductor device 100 and the second semiconductor device 200. ) When the distance between the wiring pattern and the neighboring wiring pattern becomes narrow when connecting the interconnector 130 without the interposer 130, thereby electrically connecting the wiring patterns of the first semiconductor device 100 and the second semiconductor device 200. It is possible to prevent the solder ball from shorting.

In addition, the semiconductor package 10 may manufacture a semiconductor package having a small size and a high function by stacking the first semiconductor device 100 and the second semiconductor device 200 including a plurality of semiconductor dies.

Referring to FIG. 2, a flowchart illustrating a method of manufacturing the semiconductor package of FIG. 1 is shown.

As shown in FIG. 2, the method of manufacturing a semiconductor package includes a first semiconductor device preparation step S1, a second semiconductor device attach step S2, and a solder ball welding step S3. Here, the first semiconductor device preparation step (S1) is a substrate preparation step (S11), a first semiconductor die attach step (S12), an interposer attach step (S13), a wire bonding step (S14), encapsulation Step S15 and forming a conductive via S16.

3A through 3H, cross-sectional views illustrating a method of manufacturing the semiconductor package illustrated in FIG. 2 are illustrated.

3A to 3F illustrate a substrate preparation step S11, a first semiconductor die attach step S12, an interposer attach step S13, a wire bonding step S14, and a first semiconductor device preparation step S1. Encapsulation step S15 and conductive via forming step S16 are shown.

As shown in FIG. 3A, in the substrate preparing step S11, a first insulating layer 111 having a flat second surface 111b as an opposite surface of the first flat surface 111a and the first surface 111a. Prepare. In addition, at least one first conductive via 119 penetrating between the first surface 111a and the second surface 111b of the first insulating layer 111 is formed. In addition, at least one first wiring pattern 112 is formed on the first surface 111a of the first insulating layer 111, and the first solder mask 114 is formed on the outer circumference of the first wiring pattern 112. To form. In addition, at least one second wiring pattern 116 is formed on the second surface 111b of the first insulating layer 111, and a second solder mask 118 is formed on the outer circumference of the second wiring pattern 116. To form the first circuit board 110. In this case, the first wiring pattern 112 formed on the first surface 111a of the first insulating layer 111 has a second wiring pattern formed on the second surface 111b through the first conductive via 119. Is electrically connected to 116.

As shown in FIG. 3B, in the first semiconductor die attach step S12, the first semiconductor die 120 including the at least one conductive bump 125 may be transferred to the first wiring pattern 112. The first semiconductor die 120 is mounted on the first circuit board 110 so that the conductive bumps 125 and the first wiring patterns 112 are in contact with each other. In this case, the first wiring pattern 112 of the first circuit board 110 is electrically connected to the first semiconductor die 120 through the conductive bumps 125. The first semiconductor die 120 may be absorbed by a transfer member (not shown) and transferred to the first circuit board 110, but the method is not limited thereto.

As shown in FIG. 3C, in the interposer attach step (S13), the interposer 130 including at least one third wiring pattern 132 is transferred and seated on the upper portion of the first semiconductor die 120. . The interposer 130 includes a second insulating layer 131 including a flat first surface 131a and a second surface 131b that is flat to the opposite surface of the first surface 131a, and the second insulating layer. At least one third wiring pattern 132 formed on the first surface 131a of 131 and an outer circumference of the third wiring pattern 132 are exposed to expose a portion of the third wiring pattern 132. The third solder mask 134 is formed. The interposer 130 may be absorbed by a transfer member (not shown) and transferred to the first semiconductor die 120, but the method is not limited thereto.

As shown in FIG. 3D, in the wire bonding step S14, the first circuit board 110 and the interposer 130 are electrically connected to each other using a first conductive wire 140. That is, the first wiring pattern 112 of the first circuit board 110 and the third wiring pattern 132 of the interposer 130 are electrically connected to each other. The first conductive wire 140 is made of any one of gold (Au), aluminum (Al), and copper (Cu) or an alloy thereof, but is not limited thereto.

As shown in FIG. 3E, in the encapsulation step S15, the first circuit board 110, the first semiconductor die 120, the interposer 130, and the first conductive wire 140 are removed. It is encapsulated using the first encapsulant 150. That is, the first encapsulant 150 is formed on the first surface 111a of the first insulating layer 111 on the first circuit board 110 and the first wiring pattern 112 and the first solder mask. 114, the first semiconductor die 120, the interposer 130, and the first conductive wire 140 are encapsulated. In this case, the first encapsulant to expose the third wiring pattern 132 to which the solder ball 250 of the second semiconductor device to be connected is connected to the outside of the third wiring pattern 132 of the interposer 130. Grooves 155 are formed in the 150. The third wiring pattern 132 may be exposed to the outside through the recess 155 to be electrically connected to the solder ball 250.

As shown in FIG. 3F, in the conductive via forming step S16, a second conductive via 159 is formed in the recess 155 formed in the first encapsulant 150 in the encapsulation step S15. Fill. The second conductive via 159 is formed on the third wiring pattern 132 of the interposer 130, and the solder balls 250 of the second semiconductor device 200 to be described below are welded to each other. The poser 130 and the second semiconductor device 200 are electrically connected to each other.

As shown in FIG. 3G, in the second semiconductor device attach step S2, the second semiconductor device 200 including the at least one solder ball 250 may be inserted into the interposer 130 in the first semiconductor device 100. The second semiconductor device 200 may be transferred to the second conductive via 159 electrically connected to the third wiring pattern 132 of FIG. 3 so that the second conductive via 159 and the solder ball 250 are in contact with each other. Is mounted on the first semiconductor device (100). In this case, the second semiconductor device 200 is electrically connected to the third wiring pattern 132 of the interposer 130 through the solder balls 250 and the second conductive vias 159. The second semiconductor device 200 may include a second circuit board 210 including a fourth wiring pattern 212 and a fifth wiring pattern 216, and a fourth wiring pattern 212 of the second circuit board 210. A second semiconductor die 220 electrically connected to the second semiconductor die 220, a conductive wire 230 electrically connecting the second semiconductor die 220 and the second circuit board to each other, the second semiconductor die 220, and the second semiconductor die 220. A second encapsulant 240 encapsulating the two circuit board 210 and a solder ball 250 electrically connected to the fifth wiring pattern 216 of the second circuit board 210. The second semiconductor device may be absorbed by a transfer member (not shown) and transferred to the first semiconductor device 100, but the method is not limited thereto.

As illustrated in FIG. 3H, in the solder ball welding step S3, the external solder ball 140 is welded to the second wiring pattern 116 of the first semiconductor device 100. For example, after applying a volatile flux having a viscosity to the second wiring pattern 116, the external solder ball 140 is temporarily seated thereon. Thereafter, the semiconductor package 10 is put into and taken out of a furnace having a temperature of approximately 100 to 300 ° C., so that the external solder ball 140 is strongly and electrically connected to the second wiring pattern 116. . Of course, all of the flux in the furnace is volatilized and removed. The external solder ball 140 is electrically connected to the first semiconductor die 120 through the first circuit board 110, and connects the first circuit board, the interposer 200, and the second circuit board 210. It is electrically connected to the second semiconductor die 220 through. Thus, the first semiconductor device 100 and the second semiconductor device 200 of the semiconductor package 10 may be mounted on an external device (not shown) through the external solder ball 140 to be electrically connected to the external device. .

What has been described above is only one embodiment for carrying out the semiconductor package according to the present invention, and the present invention is not limited to the above-described embodiment, and the present invention deviates from the gist of the present invention. Without this, anyone skilled in the art to which the present invention pertains will have the technical spirit of the present invention to the extent that various modifications can be made.

1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a method of manufacturing the semiconductor package of FIG. 1.

3A to 3H are cross-sectional views illustrating a method of manufacturing the semiconductor package shown in FIG. 2.

<Description of Symbols for Main Parts of Drawings>

10; Semiconductor package

100; A first semiconductor device 110; First Circuit Board

120; First semiconductor die 130; Interposer

140; A first conductive wire 150; First Capsule

160; Outer solder ball 200; Second semiconductor device

210; Second circuit board 220; Second semiconductor die

230; Second conductive wire 240; Second Encapsulant

250; Solder ball

Claims (16)

A first circuit board, a first semiconductor die formed on the first circuit board, an interposer formed on the first semiconductor die, and at least one first electrically connecting the interposer and the first circuit board. A first semiconductor device having a single conductive wire; And A second semiconductor device formed on top of the first semiconductor device, the second semiconductor device having a second circuit board electrically connected to the interposer and a second semiconductor die formed on top of the second circuit board, The interposer may include a second insulating layer including a first flat surface and a second flat surface opposite to the first surface; and At least one third wiring pattern formed on the first surface of the second insulating layer and electrically connected to the second semiconductor device or the first circuit board, And a third solder mask which exposes a part of the third wiring pattern formed on the first surface of the second insulating layer to be electrically connected to the second semiconductor device or the first circuit board. Semiconductor package. The method of claim 1, The first circuit board of the first semiconductor device A first insulating layer comprising a first flat surface and a second flat surface opposite to the first surface; At least one first wiring pattern formed on a first surface of the first insulating layer and electrically connected to the interposer through the first semiconductor die or the conductive wire; At least one second wiring pattern formed on the second surface of the first insulating layer; and And at least one first conductive via penetrating between the first and second surfaces of the first insulating layer to electrically connect the first wiring pattern and the second wiring pattern. package. The method of claim 2, The first circuit board of the first semiconductor device A first solder mask exposing a portion of the first wiring pattern formed on the first surface of the first insulating layer so as to be electrically connected to the first semiconductor die or the first conductive wire; and And a second solder mask exposing a portion of the second wiring pattern formed on the second surface of the first insulating layer. The method of claim 3, wherein And an external solder ball welded to the second wiring pattern of the first semiconductor device and electrically connected to the first semiconductor device. The method of claim 1, And the first semiconductor device further comprises a first encapsulant encapsulating an upper portion of the first circuit board, the first semiconductor die, the interposer and the first conductive wire. The method of claim 5, The first semiconductor device is formed inwardly from the top of the first encapsulant, further comprising at least one second conductive via electrically connecting between the interposer and the second circuit board of the second semiconductor device. A semiconductor package, characterized in that formed. The method of claim 1, The first semiconductor die of the first semiconductor device has a first flat surface and a flat second surface as an opposite surface of the first surface, on which the interposer is seated. At least one conductive bump is formed, the semiconductor package. delete The method of claim 1, And the first conductive wire is formed between the third wiring pattern of the interposer and the first circuit board to electrically connect the third wiring pattern and the first circuit board. delete The method of claim 1, The second semiconductor die of the second semiconductor device has a flat first surface and a flat second surface as an opposite surface of the first surface, and at least one bond pad is formed on the first surface. . The method of claim 11, The second circuit board of the second semiconductor device A third insulating layer comprising a first flat surface and a second flat surface opposite to the first surface; At least one fourth wiring pattern formed on a first surface of the third insulating layer and electrically connected to the bond pad of the second semiconductor die; At least one fifth wiring pattern formed on a second surface of the third insulating layer and electrically connected to the interposer of the first semiconductor device; And And at least one third conductive via penetrating between the first and second surfaces of the third insulating layer to electrically connect the fourth wiring pattern and the fifth wiring pattern. package. 13. The method of claim 12, The second circuit board of the second semiconductor device A fourth solder mask exposing a portion of the fourth wiring pattern formed on the first surface of the third insulating layer to be electrically connected to the second semiconductor die; and And a fifth solder mask which exposes a portion of the fifth wiring pattern formed on the second surface of the third insulating layer to be electrically connected to the interposer. 13. The method of claim 12, The second semiconductor device And a solder ball formed on the fifth wiring pattern of the second circuit board to electrically connect between the second circuit board and the interposer of the first semiconductor device. 13. The method of claim 12, And the second semiconductor device further comprises a plurality of second conductive wires electrically connecting between the bond pads of the second semiconductor die and the fourth wiring pattern. The method of claim 15, And a second encapsulant for encapsulating the upper portion of the second circuit board, the second semiconductor die, and the second conductive wire.

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