TWI608579B - Semiconductor structure and method of manufacture thereof - Google Patents

Description

Semiconductor structure and its manufacturing method

The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure that avoids delamination of a circuit and a method of fabricating the same.

With the development trend of electronic products, the pursuit of thin and short, and the desire to put more functions, the internal limits of electronic components, and thus the development of different types of semiconductor packages, in order to meet the trend of electronic products.

A conventional semiconductor package is manufactured by first forming a wiring layer on a carrier; then connecting a semiconductor wafer on the wiring layer, and electrically connecting the semiconductor wafer and the wiring layer using a bonding wire; and then performing a packaging process to Coating the circuit layer, the semiconductor wafer and the bonding wire; then removing the carrier, exposing the circuit layer and the lower surface of the encapsulant; and forming an refusal by inkjet on the surface of the circuit layer and the encapsulant Soldering the layer, and patterning the solder resist layer to form an opening of the exposed portion of the circuit layer; finally implanting the ball in the opening.

However, in the above method, the bonding strength between the wiring layer and the solder resist layer is poor, and the problem of delamination is liable to occur, resulting in a decrease in yield.

Therefore, how to overcome various problems of the prior art is an important issue.

In view of the above disadvantages of the prior art, the present invention provides a semiconductor structure comprising: an insulating layer having opposite first and second surfaces and openings extending through the first and second surfaces; And a portion of the circuit layer is exposed on the first surface of the insulating layer; and a metal layer is formed on the second surface of the insulating layer and has at least one recess.

The semiconductor structure further includes: at least one semiconductor wafer disposed and electrically connected to the first circuit layer; and an encapsulant formed on the first surface of the insulating layer and covering the semiconductor wafer and the circuit Floor.

The invention provides a method for fabricating a semiconductor structure, comprising: providing a substrate having an insulating layer opposite to the first surface and the second surface, and forming a first metal layer on the first surface and the second surface, respectively And a second metal layer; patterning the first metal layer to form a first wiring layer; removing the second metal layer to expose a second surface of the insulating layer; and forming a first surface through the insulating layer And opening the second surface to expose a portion of the first circuit layer.

The method for fabricating the semiconductor structure further comprises: attaching at least one semiconductor wafer to the first circuit layer, and electrically connecting the first circuit layer; performing a package molding process to form a cladding on the first surface of the insulating layer The semiconductor wafer and the encapsulant of the first circuit layer; and a solder ball electrically connected to the first circuit layer is formed in the opening.

The present invention further provides another embodiment of a method for fabricating a semiconductor structure, comprising: providing a substrate having an insulating layer opposite to the first surface and the second surface, and forming the first surface and the second surface respectively a first metal layer and a second metal layer; the first metal layer and the second metal layer are patterned to form a first circuit layer and a second circuit layer, respectively; and the first surface is formed in the insulating layer The opening of the second surface exposes a portion of the first circuit layer.

The method of fabricating the semiconductor structure further comprises: attaching at least one semiconductor wafer to the first circuit layer, and electrically connecting the semiconductor wafer to the first circuit layer; forming a cladding on the first surface of the insulating layer The semiconductor wafer and the encapsulant of the first circuit layer; and a solder ball electrically connected to the first circuit layer is formed in the opening.

In the above semiconductor structure and method, the semiconductor wafer is electrically connected to the first wiring layer by flip chip or wire bonding.

In the foregoing semiconductor structure and method, an insulating protective layer is formed on the first circuit layer, and the insulating protective layer has an opening, and the first circuit layer is exposed outside, and the semiconductor chip is correspondingly disposed on The insulating protective layer is on.

In the foregoing semiconductor structure and method, a metal protective layer is formed on a portion of the first wiring layer for electrically connecting the semiconductor wafer to the metal protective layer. The material of the metal protective layer is, for example, nickel/gold.

In the semiconductor structure and the manufacturing method described above, a method of forming an opening in the insulating layer is a laser drilling.

In the foregoing semiconductor structure and method, the first and second metal layers are The quality is copper.

In the semiconductor structure and the manufacturing method described above, the material of the insulating layer is, for example, an insulating material such as a resin, an epoxy resin, a polyimide or an ABF (Ajinomoto Build-up Film) dielectric material.

In the foregoing semiconductor structure and method, the second metal layer is formed with at least one recess, and the recess is formed by, for example, a half etching process. In the semiconductor structure and the manufacturing method described above, an electrode pad is repeatedly formed on the first wiring layer on which the opening is exposed.

As can be seen from the above, the present invention provides a stable combination of an insulating layer and a metal layer for patterning and subsequent crystallization, package molding, and drilling of the insulating layer for implanting solder balls on the exposed portion of the wiring layer. To avoid the problem of delamination between the conventional circuit layer and the solder resist layer due to poor bonding force, thereby improving the product yield, and achieving the effect of reducing the height of the semiconductor structure and reducing the manufacturing cost.

Furthermore, the present invention can form an insulating protective layer on a portion of the first wiring layer, which can increase the strength and symmetry of the semiconductor structure, and can reduce the occurrence of warpage during the packaging process, and, due to the encapsulation colloid and the The bonding force between the insulating protective layers is better than the bonding strength between the encapsulating colloid and the first wiring layer, and the problem of delamination is avoided.

In addition, the present invention utilizes a half etching process to remove a portion of the second metal layer to form at least one recess, so that the stresses received on the upper and lower sides of the substrate are symmetric during subsequent packaging processes to avoid warpage problems.

1,2,3,4,5‧‧‧Semiconductor structure

10,20,30,40,50‧‧‧insulation

10', 40'‧‧‧ substrate

10a, 30a, 40a, 50a‧‧‧ first surface

10b, 30b, 40b, 50b‧‧‧ second surface

100,400,500‧‧‧ openings

11, 41‧‧‧ first metal layer

110, 210, 310, 410, 510‧‧‧ first line layer

12,22,32,42‧‧‧second metal layer

14,24,34,44,54‧‧‧metal protective layer

15,25,35,45‧‧‧ semiconductor wafer

16,36,46‧‧‧welding line

17,27,37,47‧‧‧Package colloid

19,49‧‧‧ solder balls

28,38‧‧‧Insulating protective layer

28a, 38a, 481a, 581a‧‧ hole

32a‧‧‧ Groove

411,511‧‧‧electrode pads

420, 520‧‧‧ second circuit layer

43,53‧‧‧resist

43a, 53a‧‧‧ openings

481,581‧‧‧First insulation protection layer

482,582‧‧‧Second insulation protection layer

540‧‧‧ Conductive layer

Figures 1A to 1H are the first method of the semiconductor structure of the present invention. 2A and 2B are cross-sectional views showing a second embodiment of the method for fabricating a semiconductor structure of the present invention; and FIGS. 3A to 3D are third embodiment of the method for fabricating the semiconductor structure of the present invention; FIG. 4A to FIG. 4H are schematic cross-sectional views showing a fourth embodiment of the method for fabricating a semiconductor structure of the present invention; and FIGS. 5A to 5C are diagrams showing a fifth embodiment of the method for fabricating the semiconductor structure of the present invention. A schematic cross-sectional view.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "first", "second" and "one" are used in the description for convenience of description, and are not intended to limit the scope of the invention. Changes or adjustments are considered to be within the scope of the invention, without departing from the scope of the invention.

1A to 1H are cross-sectional views showing a semiconductor structure of the present invention and a method of fabricating the same.

As shown in FIG. 1A, a substrate 10' is provided. The substrate 10' includes an insulating layer 10 having a first surface 10a and a second surface 10b opposite thereto, and is disposed on the first surface 10a and the second surface 10b. The first metal layer 11 and the second metal layer 12.

The material of the first metal layer 11 and the second metal layer 12 is, for example, copper, and the material of the insulating layer 10 is, for example, a dielectric material of a resin, an epoxy resin, a polyimide or an ABF (Ajinomoto Build-up Film). Insulation material.

As shown in FIG. 1B, the first metal layer 11 is patterned by, for example, etching or the like to form the first wiring layer 110.

As shown in FIG. 1C, a metal protective layer 14 such as nickel/gold is formed on a portion of the first wiring layer 110, and the first wiring layer 110 covered with the metal protective layer 14 is used as a follow-up semiconductor. A pad that is electrically connected to the wafer.

As shown in FIG. 1D, at least one semiconductor wafer 15 is connected to the first circuit layer 110, and the semiconductor wafer 15 and the metal protection layer 14 formed on the first circuit layer 110 are electrically connected by the bonding wires 16. . The semiconductor wafer 15 may be flip chip mounted in addition to the first wiring layer 110 by wire bonding, but is not limited thereto.

As shown in FIG. 1E, a package molding process is performed to form an encapsulant 17 covering the semiconductor wafer 15, the bonding wire 16 and the first wiring layer 110 on the first surface 10a of the insulating layer 10.

Etching the second metal layer 12 to expose as shown in FIG. 1F The second surface 10b of the insulating layer 10.

As shown in FIG. 1G, an opening 100 penetrating the first surface 10a and the second surface 10b is formed in the insulating layer 10, and a portion of the first wiring layer 110 is exposed outside, wherein a portion of the opening 100 is exposed. A circuit layer 110 is a ball pad; the opening 100 is formed by laser drilling, but is not limited thereto.

As shown in FIG. 1H, solder balls 19 electrically connected to the first wiring layer 110 are formed in the opening 100 to fabricate the semiconductor structure 1 of the present invention.

2A and 2B are schematic cross-sectional views showing a second embodiment of the method for fabricating a semiconductor structure according to the present invention. This embodiment is substantially the same as the method of the first embodiment described above, except that the embodiment is in the first embodiment. Between the steps 1B to 1C, the steps as in Figure 2A are added.

As shown in FIG. 2A, a first wiring layer 210 is formed on the first surface of the insulating layer 20, and a second metal layer 22 is disposed on the second surface of the insulating layer 20.

An insulating protective layer 28 is further formed on the first circuit layer 210, and the insulating protective layer 28 is provided with an opening 28a, the exposed portion of the first circuit layer 210 is exposed, and then the portion of the insulating protective layer 28 is exposed. A metal protective layer 24 is formed on a wiring layer 210. The insulating protective layer 28 is, for example, a solder mask formed by screen printing, thereby increasing the structural strength and forming a vertically symmetrical structure, thereby reducing the problem of warpage occurring at the time of package molding.

As shown in FIG. 2B, the subsequent process steps are the same as in the first embodiment, followed by crystallization, wire bonding, package molding, and ball implantation processes for the insulation. A semiconductor wafer 25 is attached to the protective layer 28, and an encapsulant 27 covering the semiconductor wafer 25 and the first wiring layer 210 is formed on the first surface of the insulating layer 20. Finally, the semiconductor structure 2 covered with the insulating protective layer 28 is formed on the circuit layer as shown in FIG. 2B, wherein the bonding force between the encapsulant 27 and the insulating protective layer 28 is higher than that of the encapsulant 27 and the first wiring layer 210. The bonding force is better, so the problem of line delamination can be further avoided.

3A to 3D are schematic cross-sectional views showing a third embodiment of the method for fabricating a semiconductor structure of the present invention. This embodiment is substantially the same as the method of the first embodiment described above. First, as shown in FIG. 3A,

A first wiring layer 310 is formed on the first surface 30a of the insulating layer 30, and a second metal layer 32 is disposed on the second surface 30b of the insulating layer 30, and a portion of the second metal layer 32 is removed by half etching. A plurality of grooves 32a are formed.

As shown in FIG. 3B, an insulating protective layer 38 is formed on the first wiring layer 310, and the insulating protective layer 38 has an opening 38a, and the first wiring layer 310 is exposed outside, and then the insulating protective layer is exposed. A metal protective layer 34 is formed on the portion of the first circuit layer 310.

As shown in FIG. 3C, at least one semiconductor wafer 35 is attached to the insulating protective layer 38, and the semiconductor wafer 35 and the metal protective layer 34 formed on the first wiring layer 310 are electrically connected by a bonding wire 36. Then, through the package molding operation, an encapsulant 37 covering the semiconductor wafer 35, the bonding wires 36 and the first wiring layer 310 is formed, wherein the package is molded by partially etching the second metal layer 32 to form the recess 32a. During operation, the stress on the upper and lower sides of the insulation layer is symmetrical to avoid warpage.

As shown in FIG. 3D, the remaining second metal layer 32 is removed by etching, and the insulating layer 30 is exposed. Laser drilling and ball placement operations can then be performed to produce the semiconductor structure 3.

4A to 4H are cross-sectional views showing a fourth embodiment of the method for fabricating a semiconductor structure of the present invention.

As shown in FIG. 4A, a substrate 40' is provided. The substrate 40' includes an insulating layer 40 having a first surface 40a and a second surface 40b opposite thereto, and is disposed on the first surface 40a and the second surface 40b. The first metal layer 41 and the second metal layer 42.

The material of the first metal layer 41 and the second metal layer 42 is, for example, copper, and the material of the insulating layer 40 is, for example, a dielectric material of a resin, an epoxy resin, a polyimide or an ABF (Ajinomoto Build-up Film). Insulation material.

As shown in FIG. 4B, the first metal layer 41 is patterned by, for example, etching to form a first wiring layer 410, and the second metal layer 42 is patterned to form a second wiring layer 420.

As shown in FIG. 4C, a first insulating protective layer 481 and a second insulating protective layer 482 are formed on the first wiring layer 410 and the second wiring layer 420, wherein the first insulating protective layer 481 is provided with an opening. The hole 481a exposes a portion of the first wiring layer 410. The first insulating protective layer 481 and the second insulating protective layer 482 are, for example, solder masks formed by screen printing, thereby increasing the structural strength and forming a symmetrical structure, thereby reducing the occurrence of warpage during package molding. .

As shown in FIG. 4D, openings 400 are formed through the first surface 40a and the second surface 40b of the insulating layer 40 and the second insulating protective layer 482 to A portion of the first circuit layer 410 is exposed, wherein the portion of the first circuit layer 410 is a ball pad; the opening 400 is formed by laser drilling, but is not limited thereto.

As shown in FIG. 4E, a resist layer 43 is formed on the first insulating protective layer 481 and the second insulating protective layer 482, and the resist layer 43 corresponds to the opening of the first insulating protective layer 481. The hole 481a is formed with an opening 43a, and the first wiring layer 410 is exposed outside, and the first wiring layer 410 not covered with the first insulating protective layer 481 and the resist layer 43 is formed, for example, of nickel/gold. The metal protection layer 44, wherein the first circuit layer 410 covered with the metal protection layer 44 serves as a pad for subsequent electrical connection with the semiconductor wafer.

As shown in FIG. 4F, the resist layer 43 is removed, and an electrode pad 411 is formed on the first wiring layer 410 in which the opening 400 is exposed. The electrode pad 411 is, for example, an electrical connection pad formed by a surface treatment method of Organic Solderability Preservatives (OSP) to protect the first wiring layer 410 and facilitate welding processing for subsequent ball placement operations.

As shown in FIG. 4G, at least one semiconductor wafer 45 is attached to the first insulating protective layer 481, and the semiconductor wafer 45 and the metal protective layer 44 on the first wiring layer 410 are electrically connected by a bonding wire 46. And performing a package molding process to form the metal protective layer 44, the semiconductor wafer 45, the bonding wire 46, the first insulating protective layer 481 and the first wiring layer 410 on the first surface 40a of the insulating layer 40. The encapsulant 47; wherein, since the bonding force between the encapsulant 47 and the first insulating protective layer 481 (resist soldering layer) is better than the bonding strength between the encapsulant 47 and the first wiring layer 410, it can be further improved. Steps to avoid line delamination problems. In addition, the semiconductor wafer 45 may be a flip chip method, except for being electrically connected to the first circuit layer 410 by wire bonding, but is not limited thereto.

As shown in FIG. 4H, a solder ball 49 electrically connected to the electrode pad 411 is formed in the opening 400 to fabricate the semiconductor structure 4 of the present invention.

5A to 5C are schematic cross-sectional views showing a fifth embodiment of the method for fabricating a semiconductor structure of the present invention. This embodiment is substantially the same as the method of the fourth embodiment described above, and the main difference is that the present embodiment utilizes an electroless plating process. (Non Plating Line, NPL) forms a metal protective layer such as nickel/gold on the first wiring layer without the need to lay out electroplated wires, thereby reducing the influence of the plating of the electroplated wires.

First, as shown in FIG. 5A, after the fourth DD of the fourth embodiment, a first wiring layer 510 and a second wiring layer 520 are formed on the first surface 50a and the second surface 50b of the insulating layer 50. And covering the first circuit layer 510 and the second circuit layer 520 with a first insulating protective layer 581 and a second insulating protective layer 582, wherein the first insulating protective layer 581 is formed with an exposed portion of the first wiring layer 510 The opening 581a is further formed with an opening 500 penetrating the insulating layer 50 and the second insulating protective layer 582.

Then, on the first insulating protective layer 581, the opening 581a, and the first wiring layer 510 exposing the opening 581a, the conductive layer 540 is formed by sputtering or the like, for example, the conductive layer 540 The material is copper, but not limited to this.

Then forming a resist layer 53 on the conductive layer 540 and the second insulating protective layer 582, wherein the resist layer 53 corresponds to not covering the first insulating layer A portion of the first layer 510 of the protective layer 581 is formed with an opening 53a, and a portion of the conductive layer 540 is exposed, and a metal protective layer 54 such as nickel/gold is formed on the exposed conductive layer 540.

As shown in FIG. 5B, the resist layer 53 is removed first, and then the conductive layer 540 is removed by an ablation process, and then the surface of the first wiring layer 510 in the opening 500 is exposed. The processing method forms the electrode pad 511 to protect the first circuit layer 510 and facilitate the soldering process of the subsequent ball placement operation.

The subsequent process steps are the same as in the fourth embodiment, followed by crystallization, wire bonding, package molding, and ball implantation processes, and finally the semiconductor structure 5 as shown in FIG. 5C is obtained.

Referring to FIG. 1H, the present invention further provides a semiconductor structure comprising: an insulating layer 10 having opposite first and second surfaces 10a, 10b, and having an insulating layer 10 extending through the first surface 10a and the first surface The opening 100 of the two surfaces 10b; and the first circuit layer 110 are disposed on the first surface 10a of the insulating layer 10, and a portion of the first circuit layer 110 is exposed to the opening 100. In addition, the semiconductor structure includes: at least one semiconductor wafer 15 is disposed on the first circuit layer 110; the bonding wire 16 is electrically connected to the semiconductor wafer 15 and the first circuit layer 110; and the encapsulant 17 is Formed on the first surface 10a of the insulating layer 10, and covering the semiconductor wafer 15, the bonding wire 16 and the first wiring layer 110; and the solder ball 19 is disposed in the opening 100, and is electrically connected to The first circuit layer 110.

Referring to FIG. 2B, the semiconductor structure 2 of the present invention further includes an insulating protective layer 28 formed on the first wiring layer 210.

Referring to FIG. 4H, the semiconductor structure 4 of the present invention further includes a second wiring layer 420 formed on the second surface 40b of the insulating layer 40. In addition, the semiconductor structure 4 further includes a metal protective layer 44 formed on a portion of the first wiring layer 410.

In summary, the present invention provides a stable combination of insulating layers and metal layers for patterning and subsequent crystallization, package molding, drilling of the insulating layer for implantation on exposed portions of the wiring layer. The ball avoids the problem of delamination between the conventional circuit layer and the solder resist layer due to poor bonding force, thereby improving the yield of the product, and achieving the effect of reducing the height of the semiconductor structure and reducing the manufacturing cost.

Furthermore, the present invention can form an insulating protective layer on a portion of the first wiring layer, which can increase the strength and symmetry of the semiconductor structural package, and can reduce the problem of warpage during the packaging process, and, due to the encapsulation colloid The bonding force with the insulating protective layer is better than the bonding force between the encapsulating colloid and the first wiring layer, and the problem of delamination is avoided.

In addition, the present invention utilizes a half etching process to remove a portion of the second metal layer to form at least one recess, so that the stresses received on the upper and lower sides of the substrate are symmetric during subsequent packaging processes to avoid warpage problems. Further, the present invention also utilizes a Non Plating Line (NPL) process to reduce the effects of plating of the electroplated wires.

The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, those who have this expertise in the technical field are All equivalent modifications or variations that are made without departing from the spirit and scope of the inventions disclosed herein are still covered by the appended claims.

1‧‧‧Semiconductor structure

10‧‧‧Insulation

10a‧‧‧ first surface

10b‧‧‧second surface

100‧‧‧ openings

110‧‧‧First circuit layer

14‧‧‧Metal protective layer

15‧‧‧Semiconductor wafer

16‧‧‧welding line

17‧‧‧Package colloid

19‧‧‧ solder balls

Claims (24)

A semiconductor structure comprising: an insulating layer having opposite first and second surfaces and openings extending through the first and second surfaces; a first circuit layer formed on the first surface of the insulating layer, And a portion of the first circuit layer is exposed on the opening; a second circuit layer is formed on the second surface of the insulating layer; and an insulating protective layer is formed on the first circuit layer and the second circuit layer. The insulating protective layer on the first circuit layer has an opening, and the first circuit layer is exposed outside, and the insulating protective layer on the second circuit layer has an opening, and the opening of the insulating layer is exposed; And an electrode pad formed on the first circuit layer exposed to the opening. The semiconductor structure of claim 1, further comprising a conductive layer formed on the first circuit layer exposing the opening of the insulating protective layer. The semiconductor structure of claim 1, further comprising a metal protective layer formed on the first circuit layer exposing the opening of the insulating protective layer. The semiconductor structure of claim 1, comprising at least one semiconductor wafer disposed on the insulating protective layer and electrically connected to the first wiring layer. The semiconductor structure as described in claim 4, including A colloid is formed on the first surface of the insulating layer to encapsulate the semiconductor wafer. The semiconductor structure according to claim 1, wherein the insulating layer is made of a dielectric material of a resin, an epoxy resin, a polyimide or an ABF (Ajinomoto Build-up Film). A method of fabricating a semiconductor structure, comprising: providing a substrate having an insulating layer opposite to the first surface and the second surface, and forming a first metal layer and a second metal on the first surface and the second surface, respectively a layer; patterning the first metal layer to form a first wiring layer; removing the second metal layer to expose a second surface of the insulating layer; and forming a first surface and the second through the insulating layer The opening of the surface exposes a portion of the first circuit layer. The method of fabricating the semiconductor structure of claim 7, further comprising: attaching at least one semiconductor wafer to the first circuit layer, and electrically connecting the semiconductor wafer to the first circuit layer. The method for fabricating a semiconductor structure according to claim 8 is further characterized in that the first surface of the insulating layer is formed on the first surface of the insulating layer to form an encapsulant covering the semiconductor wafer and the first wiring layer. The method for manufacturing a semiconductor structure according to claim 7, further comprising forming a solder ball on a portion of the first circuit layer on which the opening is exposed, and electrically connecting the solder ball to a portion of the opening. A line layer. The method for fabricating a semiconductor structure according to claim 7 is characterized in that the insulating layer is formed on the first circuit layer. The method for fabricating a semiconductor structure according to claim 7, further comprising forming a metal protective layer on a portion of the first wiring layer. The method of fabricating the semiconductor structure of claim 7, further comprising forming at least one recess in the second metal layer. The method of fabricating a semiconductor structure according to claim 7, wherein the material of the insulating layer is a dielectric material of a resin, an epoxy resin, a polyimide or an ABF (Ajinomoto Build-up Film). A method of fabricating a semiconductor structure, comprising: providing a substrate having an insulating layer opposite to the first surface and the second surface, and forming a first metal layer and a second metal on the first surface and the second surface, respectively Forming the first metal layer and the second metal layer to form a first circuit layer and a second circuit layer, respectively; and forming an opening through the first surface and the second surface in the insulating layer Part of the first circuit layer. The method for fabricating a semiconductor structure according to claim 15 further comprising forming a solder ball on a portion of the first circuit layer on which the opening is exposed, and electrically connecting the solder ball to a portion of the opening. A line layer. The method of fabricating a semiconductor structure according to claim 15 further comprising: attaching at least one semiconductor wafer to the first circuit layer, and electrically connecting the semiconductor wafer to the first circuit layer. The method of fabricating a semiconductor structure according to claim 17, further comprising forming a package colloid covering the semiconductor wafer and the first wiring layer on the first surface of the insulating layer. The method for fabricating a semiconductor structure according to claim 15 further comprises forming an insulating protective layer on the first circuit layer and the second circuit layer. The method for fabricating a semiconductor structure according to claim 15 further comprising forming a metal protective layer on a portion of the first wiring layer. The method of fabricating a semiconductor structure according to claim 15 further comprising forming an electrode pad on the first circuit layer on which the opening is exposed. The method of fabricating a semiconductor structure according to claim 15 , wherein after forming the first and second circuit layers, the method further comprises: forming a first on the first circuit layer and the second circuit layer respectively An insulating protective layer and a second insulating protective layer, wherein the first insulating protective layer has an opening, the portion of the first circuit layer is exposed; the first surface and the second surface penetrating the insulating layer and the second insulating protective layer are formed Opening a portion of the first circuit layer; forming a resist layer on the first insulating protective layer and the second insulating protective layer; wherein the resist layer corresponds to the opening of the first insulating protective layer The hole is formed with an opening, the portion of the first circuit layer is exposed; the metal protection layer is formed on the first circuit layer not covered with the first insulation protection layer and the resist layer; and the resist layer is removed. The method for fabricating a semiconductor structure as described in claim 22, Before forming the resist layer, forming a conductive layer on the first insulating protective layer and the opening of the first insulating protective layer, and then forming the resist layer, wherein the resist layer corresponds to the first layer The opening of the insulating protective layer is formed with an opening, and a portion of the conductive layer is exposed, and the metal protective layer is formed on the exposed conductive layer, and then the resist layer and the conductive layer covered thereby are removed. The method for fabricating a semiconductor structure according to claim 15, wherein the material of the insulating layer is a dielectric material of a resin, an epoxy resin, a polyimide or an ABF (Ajinomoto Build-up Film).