JP3949077B2 - Semiconductor device, substrate, semiconductor device manufacturing method, and semiconductor device mounting method - Google Patents

Semiconductor device, substrate, semiconductor device manufacturing method, and semiconductor device mounting method Download PDF

Info

Publication number
JP3949077B2
JP3949077B2 JP2003112052A JP2003112052A JP3949077B2 JP 3949077 B2 JP3949077 B2 JP 3949077B2 JP 2003112052 A JP2003112052 A JP 2003112052A JP 2003112052 A JP2003112052 A JP 2003112052A JP 3949077 B2 JP3949077 B2 JP 3949077B2
Authority
JP
Japan
Prior art keywords
substrate
wiring
terminal
semiconductor device
terminal group
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2003112052A
Other languages
Japanese (ja)
Other versions
JP2004319792A (en
Inventor
俊也 石尾
宏之 中西
隆正 田中
勝信 森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP2003112052A priority Critical patent/JP3949077B2/en
Publication of JP2004319792A publication Critical patent/JP2004319792A/en
Application granted granted Critical
Publication of JP3949077B2 publication Critical patent/JP3949077B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、外部と接続する為の実装用電極を形成した実装面を有するエリアアレイ型の半導体装置、この半導体装置を実装した基板、この半導体装置の製造方法、及びこの半導体装置の実装方法に関するものである。
【０００２】
【従来の技術】
近年、電子機器の小型化にともなって、半導体装置等の電子部品の小型化及び高密度実装に適応する為、外部接続端子がパッケージ本体に形成されたエリアアレイ型の半導体装置の生産が、増加の一途をたどっている。この種の半導体装置の例として、特許文献１に開示されている図１１に示すような構造がある。これは、ウエハ単位でパッケージングを行うタイプのエリアアレイ半導体装置である。これの特徴は、パッケージング後の半導体装置のサイズが、半導体チップと全く同じサイズとなっていることである。
【０００３】
この半導体装置は、表面側に、素子（図示せず）と電極パッド２と２層の絶縁層３，４とを形成した半導体チップ１に、２次配線１１を更に形成し、これらを絶縁層２１が覆っている。但し、素子と電極パッド２を電気的に接続する配線を１次配線（図示せず）とし、電極パッド２と外部とを接続する配線を２次配線とする。
絶縁層２１は、２次配線１１上に外部接続端子接合部（電極）１２となる領域が露出されており、バンプ３１が形成されている。この種の半導体装置は、本体の実装面にバンプ状の外部接続端子が設けられており、ＢＧＡ（Ball Grid Array）とも呼ばれている。
【０００４】
【特許文献１】
特開平８−３３０３１３号公報
【０００５】
【発明が解決しようとする課題】
上述した従来の半導体装置では、半導体装置と実装基板との線膨張係数の違いにより、半導体装置を実装基板に実装した後、ＩＣチップの発熱及び使用環境下での温度変化により、外部接続端子であるバンプに熱応力が発生し、バンプ接合部での接合不良が発生しやすいという問題がある。
【０００６】
これは、ＳＯＰ（Small Outline Package）、ＴＳＯＰ（Thin Small Outline Package）、ＱＦＰ(Quad Flat Package)等の、図１２に示すように、外部接続端子であるアウターリード３３がパッケージ７１側面から突き出て、実装基板８１上の配線９１に接続されたガルウイング構造を有する半導体装置では、アウターリード３３が弾性変形しやすい為、熱応力を分散させることが出来るのに対し、従来のＢＧＡタイプの半導体装置では、バンプの弾性変形が比較的小さく、接合部に応力集中が発生する為である。
【０００７】
また、半導体装置が、強い電磁波を発生する半導体チップ、又は電磁波の影響で誤動作しやすい半導体チップを搭載する場合には、半導体装置を覆うようなシールドキャップを設ける必要がある。この場合、半導体装置のサイズごとにシールドキャップを準備する必要があり、半導体装置の製造工程又は実装基板への実装工程が複雑になるという問題がある。
特に、外部接続端子から発生する電磁波による装置外部の半導体チップへの影響、及び外部から素子面に進入する電磁波による装置内部の半導体チップへの影響が大きい為、これらの部位をシールドすることは必須となる。
【０００８】
本発明は、上述したような事情に鑑みてなされたものであり、基板等への実装後の接合強度を向上させることが出来ると共に、基板等への実装後は、半導体装置から外部への電磁波放射と、外部からの電磁波の影響と、外部からの光の影響とを防止することが出来る半導体装置を提供することを目的とする。
また、本発明は、配線形状の電極と、配線形状の電極以外の電極との上に、同時的にしかも簡便にバンプ形成することが出来る半導体装置の製造方法を提供することを目的とする。
【０００９】
【課題を解決するための手段】
本発明に係る半導体装置は、実装面にペリフェラル配置に形成された端子群と、前記実装面の表層側に設けられ、前記端子群の各端子に開口部を有する第１絶縁層とを有する半導体チップを備える半導体装置において、前記端子群の内側の領域の前記第１絶縁層の表層側に設けられ、前記端子群の何れかの端子と接続された１又は複数の電極と、前記端子群の外側の領域の前記第１絶縁層の表層側にパターニングにより形成された１又は複数の配線形状の電極と、前記内側の領域に設けられた電極と前記外側の領域に形成された電極とに開口部を有し、前記第１絶縁層の表層側に設けられた第２絶縁層とを備えることを特徴とする。
本発明に係る半導体装置は、前記端子群の内側の領域の前記第１絶縁層の表層側に設けられ、前記端子群の内の信号端子に電気的に接続された電極を更に備え、前記配線形状の電極は、パターニングにより形成された配線により、前記端子群の内のグランド端子と電気的に接続されていることを特徴とする。
【００１０】
本発明に係る半導体装置は、実装面にペリフェラル配置に形成され、信号端子及びグランド端子を含む端子群と、前記実装面の表層側に設けられ、前記端子群の各端子に開口部を有する第１絶縁層とを有する半導体チップを備える半導体装置において、前記端子群の内側の領域の前記第１絶縁層の表層側に設けられ、前記信号端子に配線で接続された電極と、前記第１絶縁層の表層側に設けられた第２絶縁層と、前記端子群に重なるように、前記第２絶縁層の表層側にパターニングにより形成された１又は複数の配線形状の電極とを備え、該配線形状の電極及び前記配線の間に前記第２絶縁層が介在し、該第２絶縁層は、前記端子群の内の前記信号端子及び前記配線を覆うと共に、該信号端子に配線で接続された前記電極に開口部を有し、前記グランド端子を前記配線形状の電極と電気的に接続する為に選択的に設けられた開口部を有していることを特徴とする。
本発明に係る半導体装置は、前記信号端子と配線で接続された電極、及び前記配線形状の電極には、ハンダによるバンプが設けられていることを特徴とする。
【００１１】
本発明に係る半導体装置は、一方の面にペリフェラル配置に形成された端子群を有する半導体チップと、該半導体チップを搭載する半導体チップ搭載面、及び該半導体チップ搭載面の裏側の基板実装面を有するパッケージ基板とを備える半導体装置において、前記半導体チップ搭載面に露出してペリフェラル配置に形成され、前記半導体チップの端子群とそれぞれ電気的に接続された基板端子群と、該基板端子群の内側の領域に設けられ、該基板端子群の何れかの基板端子と基板配線で接続され、前記基板実装面に露出した基板電極と、前記基板端子群の外側の領域の前記基板実装面にパターニングにより形成された１又は複数の配線形状の基板電極とを備えることを特徴とする。
本発明に係る半導体装置は、前記基板端子群の内側の領域に設けられ、前記半導体チップの端子群の内の信号端子に電気的に接続され、前記基板実装面に露出した基板電極を更に備え、前記配線形状の基板電極は、前記端子群の内のグランド端子に電気的に接続された基板端子に、パターニングにより形成された配線により接続されていることを特徴とする。
【００１２】
本発明に係る半導体装置は、一方の面にペリフェラル配置に形成され、信号端子及びグランド端子を含む端子群を有する半導体チップと、該半導体チップを搭載する半導体チップ搭載面、及び該半導体チップ搭載面の裏側の基板実装面を有するパッケージ基板とを備える半導体装置において、前記半導体チップ搭載面に露出してペリフェラル配置に形成され、前記半導体チップの端子群にそれぞれ電気的に接続された基板端子群と、該基板端子群の内側の領域に設けられ、前記信号端子に電気的に接続された基板端子に基板配線で接続され、前記基板実装面に露出した基板電極と、前記パッケージ基板の基板絶縁層を介在させて前記基板端子群に重なるように、前記基板実装面にパターニングにより形成された１又は複数の配線形状の基板電極とを備え、該配線形状の基板電極及び前記基板配線の間に前記基板絶縁層が介在し、該基板絶縁層は、前記基板端子に基板配線で接続された前記基板電極に開口部を有し、前記グランド端子に電気的に接続された基板端子を、前記配線形状の基板電極と電気的に接続する為に選択的に設けられた開口部を有していることを特徴とする。
【００１３】
本発明に係る半導体装置は、前記信号端子に電気的に接続された基板電極、及び前記配線形状の基板電極は、ハンダによるバンプが設けられていることを特徴とする。
本発明に係る基板は、本発明に係る半導体装置がハンダにより実装されていることを特徴とする。
【００１４】
本発明に係る半導体装置の製造方法は、実装面にペリフェラル配置に形成された端子群と、前記実装面の表層側に設けられ、前記端子群の各端子に開口部を有する第１絶縁層とを有する半導体チップを備える半導体装置の製造方法において、前記端子群の内側の領域の前記第１絶縁層の表層側に、前記端子群の何れかの端子と接続された１又は複数の電極と、前記端子群の外側の領域の前記第１絶縁層の表層側に、１又は複数の配線形状の電極とを、一括してパターニングにより形成する工程と、前記内側の領域に設けられた電極と前記外側の領域に形成された電極とに開口部を有する第２絶縁層を、前記第１絶縁層の表層側に形成する工程とを含むことを特徴とする。
本発明に係る半導体装置の製造方法は、前記パターニングにより形成する工程では、前記端子群の内側の領域の前記第１絶縁層の表層側に、前記端子群の内の信号端子に電気的に接続された電極を形成し、前記配線形状の電極を、前記端子群の内のグランド端子と電気的に接続することを特徴とする。
【００１５】
本発明に係る半導体装置の製造方法は、実装面にペリフェラル配置に形成され、信号端子及びグランド端子を含む端子群と、前記実装面の表層側に設けられ、前記端子群の各端子に開口部を有する第１絶縁層とを有する半導体チップを備える半導体装置の製造方法において、前記端子群の内側の領域の前記第１絶縁層の表層側に、前記信号端子に接続された配線及び電極を形成する工程と、前記第１絶縁層の表層側に、前記信号端子及び前記配線を覆うと共に、該信号端子に配線で接続された前記電極に開口部を有し、前記グランド端子に選択的に設けられた開口部を有する第２絶縁層を形成する工程と、該第２絶縁層の表層側に、前記端子群に重なるように、１又は複数の配線形状の電極をパターニングにより形成する工程とを含むことを特徴とする。
【００１６】
本発明に係る半導体装置の製造方法は、前記信号端子と配線で接続された電極、及び前記配線形状の電極には、一括してハンダによるバンプを設けることを特徴とする。
本発明に係る半導体装置の実装方法は、本発明に係る半導体装置の製造方法により製造された半導体装置の電極と配線形状の電極とをハンダにより基板に実装することを特徴とする。
本発明に係る半導体装置の実装方法は、複数の配線形状の電極を形成した場合は、該複数の配線形状の電極の間からアンダーフィル材を注入することを特徴とする。
【００１７】
本発明に係る半導体装置の製造方法は、一方の面にペリフェラル配置に形成された端子群を有する半導体チップと、該半導体チップを搭載する半導体チップ搭載面、及び該半導体チップ搭載面の裏側の基板実装面を有するパッケージ基板とを備える半導体装置の製造方法において、前記半導体チップ搭載面に露出してペリフェラル配置された基板端子群と、該基板端子群の内側の領域に設けられ、該基板端子群の何れかの基板端子と基板配線で接続され、前記基板実装面に露出した基板電極とを形成し、前記基板端子群の外側の領域の前記基板実装面に１又は複数の配線形状の基板電極をパターニングにより形成する工程と、該工程により形成された前記パッケージ基板への前記半導体チップの搭載と、該半導体チップの端子群及び前記基板端子群それぞれの電気的接続とを行う工程とを含むことを特徴とする。
【００１８】
本発明に係る半導体装置の製造方法は、前記パッケージ基板を形成する工程は、前記基板端子群の内側の領域に、前記基板実装面に露出した基板電極を形成し、前記配線形状の基板電極と前記基板端子の１又は複数とを接続する配線を、パターニングにより形成し、前記パッケージ基板に前記半導体チップを搭載する工程は、前記基板電極を該半導体チップの端子群の内の信号端子に電気的に接続し、前記配線形状の基板電極に接続された前記基板端子を、前記端子群の内のグランド端子に電気的に接続することを特徴とする。
【００１９】
本発明に係る半導体装置の製造方法は、一方の面にペリフェラル配置に形成され、信号端子及びグランド端子を含む端子群を有する半導体チップと、該半導体チップを搭載する半導体チップ搭載面、及び該半導体チップ搭載面の裏側の基板実装面を有するパッケージ基板とを備える半導体装置の製造方法において、前記半導体チップ搭載面に露出してペリフェラル配置された基板端子群と、該基板端子群の内側の領域に設けられ、該基板端子群の基板端子に基板配線で接続され、前記基板実装面に露出した基板電極とを形成し、前記パッケージ基板の基板絶縁層の所定の複数位置に各開口部を形成し、前記基板絶縁層を介在させて前記基板端子群に重なるように、前記基板実装面に１又は複数の配線形状の基板電極をパターニングにより形成する工程と、該工程により形成された前記パッケージ基板への前記半導体チップの搭載と、該半導体チップの端子群及び前記基板端子群それぞれの電気的接続と、前記グランド端子に電気的に接続された基板端子の、前記開口部を通じての選択的な前記配線形状の基板電極への電気的接続とを行う工程とを含むことを特徴とする。
【００２０】
本発明に係る半導体装置の製造方法は、前記基板実装面に露出した基板電極、及び前記配線形状の基板電極は、一括してハンダによるバンプを設けることを特徴とする。
本発明に係る半導体装置の実装方法は、本発明に係る半導体装置の製造方法により製造された半導体装置の基板電極と配線形状の基板電極とをハンダにより基板に実装することを特徴とする。
本発明に係る半導体装置の実装方法は、複数の配線形状の基板電極を形成した場合は、該複数の配線形状の基板電極の間からアンダーフィル材を注入することを特徴とする。
【００２１】
【発明の実施の形態】
以下に、本発明を、その実施の形態を示す図面を参照しながら説明する。
実施の形態１．
図１は、本発明に係るエリアアレイ型の半導体装置の実施の形態１の構成を示す平面図及び断面図であり、図１（ａ）は、この半導体装置の実装面側から見た平面図であり、図１（ｂ）は、図１（ａ）のＡ−Ａ′における断面図である。この半導体装置は、半導体チップ１の表面に素子（図示せず）と電極パッド２（２ａ，２ｂも含む）及び２層の絶縁層３，４とが形成されている。
【００２２】
絶縁層３は、シリコン酸化物等の無機絶縁層で形成され、絶縁層３の表層側に設けられた絶縁層４は、ポリイミド系の有機絶縁層で形成されている。絶縁層３のみでも絶縁性は保たれるが、ここでは、１次配線と２次配線との間に発生するクロストーク等を抑制する為に絶縁層４を更に形成している。また、絶縁層３は有機性のものでも良く、あらゆる組合せが考えられ、３層以上形成することも可能である。
絶縁層３，４には、電極パッド２の領域を露出するように開口部が設けられている。
【００２３】
絶縁層４の表面には、絶縁層４の開口部から露出した電極パッド２と電気的に接続された２次配線１１が形成されており、絶縁層４及び２次配線１１を更に絶縁層２１が覆っている。絶縁層２１には、２次配線１１の所望の領域１２，１４に対向して、開口部２２，２３がそれぞれ形成されている。
領域１２は、外部と電気的に接続可能な電極であり、領域１４は、実装面の外縁部に沿って延設された配線形状の電極であり、外部と電気的に接続可能である。２次配線１１，１２(電極１２),１４(配線形状の電極１４)は同一平面上に形成されている。
【００２４】
電極パッド２の内、電極パッド２ａ，２ｂはグランド端子（固定電位を与えられた端子）であり、配線形状の電極１４と電気的に接続されている。本実施の形態１では，電極１２ａにもグランド端子２ａが電気的に接続しているが、実装面の面積が小さい場合等、場合によってはグランド端子と電気的に接続する電極１２を設けないことも可能である。
また、グランド端子が１つしか存在しない場合は、２次配線１１によって、複数個ある配線形状の電極の個数分、枝分かれさせて電気的に接続すれば良い。
【００２５】
また、本実施の形態１では、配線形状の電極１４とグランド端子とを電気的に接続しているが、接続しない場合でも、配線形状の電極が存在するだけで、実装後の接合強度を向上させることが可能であり、半導体チップ１から外部への電磁波放射と、外部からの電磁波の影響と、外部からの光の影響とをそれぞれ防止する効果がある。但し、電磁波のシールド効果は、グランド端子と電気的に接続した場合の方が遥かに向上する。
また、本実施の形態１では、配線形状の電極１４を２分割しているが、この場合でも、実装後の接合強度を向上させることが可能であり、半導体チップ１から外部への電磁波放射と、外部からの電磁波の影響と、外部からの光の影響とをそれぞれ防止する効果がある。
【００２６】
図８は、この半導体装置の実装状態の一例を示す説明図である。尚、図８及び後述する図６，７における実装基板８１とは、半導体装置が実装される面のことであり、プリント基板、半導体チップ、半導体装置等、あらゆるものを実装対象物に当てはめることが出来る。
図８に示すこの半導体装置の実装状態では、電極１２,１４と実装基板８１上のランド９１，９２（配線）とを、外部接続端子３１,３２がそれぞれ接続している。
【００２７】
図６は、図８に示す半導体装置の実装状態を得る方法の例を示す説明図である。
この方法では、外部接続端子３１,３２となる材料を、予め実装基板８１のランド９１，９２に形成しておく。この例では、外部接続端子３１,３２となるペースト状のハンダを印刷法により所望の領域に印刷し、実装基板８１と半導体装置との位置合わせを行い、リフロー炉等で熱処理を行って接続する。
【００２８】
図２は、図１に示す半導体装置の電極１２及び配線形状の電極１４にバンプを形成した場合の構成例を示す平面図及び断面図であり、図２（ａ）は、この半導体装置の実装面側から見た平面図であり、図２（ｂ）は、図２（ａ）のＢ−Ｂ′における断面図である。
この半導体装置では、ハンダからなるバンプ３１，３２が、電極１２,１４に予め形成されている。尚、バンプ材料としては、特に限定する必要はないが、この例ではハンダを用いている。
【００２９】
図７は、図２に示す半導体装置の実装基板への実装状態を得る方法の例を示す説明図である。
上述した図６に示す方法では、実装基板８１上にハンダを印刷したが、図７に示す例では、半導体装置にハンダからなるバンプ３１，３２が予め形成されている。その為、実装基板８１にはフラックスのみ又は少量のハンダを供給するだけでも、接続が可能である。予め半導体装置にバンプ３１，３２を形成しておくと、基板実装時に半導体装置の高さ、傾き等を調整する必要がない為、半導体装置を実装基板に容易に実装することが出来る。
【００３０】
本実施の形態１では、配線形状の電極１４を一例として２つに分割しているが、この形状には以下の利点がある。即ち、配線形状の電極と接続したバンプ間には隙間が存在する為、実装後、この隙間からアンダーフィル材等の液状樹脂を注入することが可能である。従って、注入された液状樹脂の硬化処理を行えば、更に実装の接合強度を向上させることが出来る。
【００３１】
また、ハンダペースト等、粒子を含む材料を実装基板（半導体装置等も含む）上に印刷する場合、メッシュスクリーンよりもメタルマスクの方が、印刷材料が通過し易い為、印刷し易い。ところが、配線形状の電極１４が分割されていない場合、マスクの作製は非常に困難であるが、分割している為、容易にマスクを製作することが出来る。
【００３２】
図９は、図１及び図２に示す半導体装置の製造工程の一例を示す説明図である。生産性を考慮すると、図１に示す半導体装置の場合は、工程（ａ）から工程（ｃ）迄をウエハ単位で製造し、工程（ｃ）以降に個片化すると良い。図２に示す半導体装置の場合は、工程（ａ）から工程（ｅ）迄をウエハ単位で製造し、工程（ｃ）以降に個片化すると良い。尚。図９では、半導体ウエハの全体図は省略し、１つの半導体チップについて図示している。
以下に、各工程（ａ）〜（ｅ）について説明する。
工程（ａ）では、半導体チップ１には、素子（図示せず）と電極パッド２と絶縁層３，４とが形成されており、電極パッド２の領域に絶縁層３，４の開口部が形成されている。
【００３３】
工程（ｂ）では、半導体チップ１上に２次配線１１，１２，１４を形成するが、この２次配線のパターンニング方法には、リフトオフ、電解メッキ、無電解メッキ、エッチング、印刷及びこれらを組み合わせた方法等、あらゆる方法が考えられ、更に配線材料としても様々なものが考えられる。
ここでは、電解メッキによりＡｕ／Ｎｉ／Ｃｕを形成している。電極パッド２がＡｌを主成分とする場合には、Ｔｉ，Ｔｉ−Ｗ，Ｃｒ等のバリア層（図示せず）を必要とする。ここでは、Ｔｉ−Ｗの薄膜を形成し、更にＣｕメッキを密着、形成させる為のＣｕ薄膜（図示せず）を、スパッタリングにより半導体チップ１の全面に形成する。
【００３４】
次に、感光性レジストを塗布、乾燥させた後、フォトリソグラフィによりパターニングし、２次配線１１，１２，１４が所望のパターンとなるように、Ｃｕ，Ｎｉ，Ａｕの順に形成する。
メッキ終了後、レジストを剥離液で除去し、２次配線１１，１２，１４の配線パターンをマスクとして、配線パターン以外の領域に形成したＣｕ，Ｔｉ−Ｗのスパッタリング形成膜をエッチング液により除去する。
【００３５】
工程（ｃ）では、絶縁層２１を形成するが、ここでも材料として種々の材料が考えられる。本実施の形態１では、感光性ポリイミドを用いる。
先ず、この材料のワニス状態のものを塗布、乾燥する。次に、フォトリソグラフィによりパターニングし、２次配線１１，１２，１４上の電極１２の領域と配線形状の電極１４の領域に開口部２２，２３を設け、熱処理により硬化させる。図１に示す半導体装置の場合は、絶縁層２１の形成後、ダイシング等によって個片化され、完成となる。個片化を行い易くする為、絶縁膜３，４，２１については、予めダイシング領域に開口部を設けておくと良い。
【００３６】
図２に示す半導体装置の場合は、その製造方法の一例としては以下のようになる。この場合、生産性を考えると、工程（ｃ）の後、個片化を行わずに、工程（ｄ）以降を行う。バンプ３１，３２についても種々の材料、形成方法が考えられるが、ここでは，電極１２と配線形状の電極１４とを同時に、しかも簡便に形成することが可能な印刷方法を用いている。即ち、工程（ｄ）において、ペースト状のハンダを電極１２及び配線形状の電極１４上にメタルマスクを用いて印刷した後、工程（ｅ）において、リフロー炉等を用いて熱処理を行うことにより、バンプを形成する。次いで、個片化すると図２に示す半導体装置が完成する。
【００３７】
実施の形態２．
図３は、本発明に係るエリアアレイ型の半導体装置の実施の形態２の構成を示す平面図及び断面図であり、図３（ａ）は、この半導体装置の実装面側から見た平面図であり、図３（ｂ）は、図３（ａ）のＣ−Ｃ′における断面図である。ここでは、実施の形態１の半導体装置と異なる構成についてのみ説明する。
上述した実施形態１では、実装面の外縁部に沿って延設された配線形状の電極１４には、半導体チップ上の電極パッドから配線を引き回していたが、本実施の形態２では、配線形状の電極１４を、電極パッド２上に設ける為、半導体装置の実装面が小さな場合に有効である。
【００３８】
本実施の形態２では、半導体装置の実装面において、半導体チップ１のグランド端子２ａと電気的に接続された２次配線１３ａ上には，絶縁層２１の開口部２３を設け、この開口部２３を横切るように、配線形状の電極１４を形成している。
一方、グランド端子以外の電極パッド２(又はグランド端子以外の電極パッド２と接続された２次配線１３)と配線形状の電極１４との間には、絶縁層２１が存在する為(図３（ｂ）に描かれた右側の電極パッド２付近を参照)、電気的にショートすることはない。その他の構成については、実施の形態１の半導体装置の構成と略同様であるので、説明を省略する。
【００３９】
図１０は、図３に示す半導体装置の製造工程の一例を示す説明図である。実施の形態１の場合と同様に、生産性を考慮すると、バンプ迄形成しない場合は、工程（ａ）から工程（ｄ）迄をウエハ単位で製造し、その後個片化すると良い。図３に示す半導体装置のようにバンプを形成する場合は、工程（ａ）から工程（ｆ）迄をウエハ単位で製造し、工程（ｆ）の後に個片化すると良い。尚、図１０では、半導体ウエハ全体図は省略し、1つの半導体チップについて図示している。
以下に、各工程（ａ）〜（ｆ）について説明する。
工程（ａ）では、半導体チップ１には、素子（図示せず）と電極パッド２と絶縁層３，４とが形成されており、電極パッド２の領域に絶縁層３，４の開口部を形成している。
【００４０】
工程（ｂ）では、半導体チップ１上の２次配線１１，１２，１３の形成は、実施の形態１で説明したように、種々の方法が考えられるが、ここでも電解メッキにより形成した。但し、ここでは、２次配線１１，１２，１３の材料はＣｕのみとする。
電極パッド２がＡｌを主成分とする場合には、Ｔｉ，Ｔｉ−Ｗ，Ｃｒ等のバリア層（図示せず）を必要とする。ここでも、実施の形態１と同様に、Ｔｉ−Ｗの薄膜を形成し、更にＣｕメッキを密着、形成させる為のＣｕ薄膜（図示せず）を、スパッタリングにより半導体チップ１の全面に形成する。
【００４１】
次に、感光性レジストを塗布、乾燥させた後、フォトリソグラフィにより２次配線１１，１２，１３が所望のパターンとなるように形成し、パターンの開口部に電解メッキによりＣｕ配線を形成する。
メッキ終了後、レジストを剥離液で除去し、２次配線１１，１２，１３の配線パターンをマスクとして、配線パターン以外の領域に形成したＣｕ，Ｔｉ−Ｗのスパッタリング形成膜をエッチング液で除去する。
【００４２】
工程（ｃ）では、感光性ポリイミドを用い、フォトリソグラフィによりパターニングする。絶縁層２１の材料として、種々の材料が考えられるが、ここでも実施の形態１と同様に、感光性ポリイミドを用いる。
但し、２次配線１１，１２，１３上の領域１２と、後の工程で配線形状の電極１４が形成される２次配線上の領域１３ａ，１３ｂ（図３（ａ）参照）とに開口部２２と開口部２３とを設ける。
ここで、領域１３ａ，１３ｂに開口部２３を設けたことにより、グランド端子２ａ，２ｂ（図３（ａ）参照）に電気的に接続された２次配線の領域１３ａ，１３ｂと配線形状の電極１４とを電気的に接続することが出来る。絶縁層２１は、開口部２２，２３の形成後、熱処理により硬化される。
【００４３】
本実施の形態２においては、更に配線形状の電極１４を設ける必要がある。ここでも種々の方法から、電解メッキ法を用いる。
工程（ｄ）では、この為、Ｃｕ薄膜をスパッタリングで形成する。また、必要に応じて、下地の絶縁層２１等との密着性が良好な金属薄膜をＣｕの下層にスパッタリング等で形成しても良い。
次に，感光性レジストの塗布及び乾燥を行い、フォトリソグラフィによりパターニングを行い、配線形状の電極１４を形成する領域と、領域１２の開口部とを設ける。配線形状の電極１４と、領域１２に形成する電極１５との構成をＡｕ／Ｎｉ／Ｃｕとする場合は、ここで、Ｃｕ，Ｎｉ，Ａｕの順に電解メッキにより形成する。
【００４４】
感光性レジストの開口部は、配線形状の電極１４の形成領域のみに形成しても良いが、この場合、配線形状の電極１４に、この段階ではＣｕのみを形成し、感光性レジスト及びＣｕメッキパターン以外の不要部分に形成されたＣｕ薄膜の除去を行った後に、更に無電解メッキ等でＡｕ／Ｎｉ薄膜を配線形状の電極１４と電極１５とに形成することになる。
外部接続端子３１，３２をハンダとした場合、ハンダの主成分であるＳｎがＣｕ中に拡散しやすい為、Ｃｕのみの電極ではＣｕ膜の厚さを数十μm以上に形成する必要がある。その為、バリア層となるＮｉを形成し、Ｎｉの酸化防止及びハンダの濡れ性向上の為に、Ａｕを形成する必要がある。
【００４５】
このように、無電解メッキ等で更にＡｕ／Ｎｉを形成する工程では、非常に複雑になることから、感光性レジストの開口を電極１２の領域にも行い、配線形状の電極１４の形成と同時にＡｕ／Ｎｉ／Ｃｕを形成すると良い。Ａｕ／Ｎｉ／Ｃｕメッキの形成後、剥離液によりレジストの除去を行い、領域１２及び配線形状の電極１４の形成領域に形成したＡｕ／Ｎｉ／Ｃｕメッキ層をマスクとして、その他の領域のスパッタリング形成膜について、エッチングを行う。
【００４６】
上述した図１に示す半導体装置の場合と同様に、電極１５及び配線形状の電極１４にバンプを形成しない場合は、工程（ｄ）の後に、半導体ウエハを個片化し、半導体装置を得る。バンプを形成する場合は、ここで個片化を行わずに、工程（ｅ）以降を行うと生産性が良い。
バンプの種類及びその形成方法としては種々考えられるが、工程（ｅ）では、、ハンダペーストを印刷法により電極１５上と、配線形状の電極１４上とにおいて同時に印刷し、工程（ｆ）では、リフロー炉等を用いて、加熱することによりバンプを形成する。その後、個片化することにより図３に示す半導体装置が完成する。
【００４７】
実施の形態３．
図４は、本発明に係るエリアアレイ型の半導体装置の実施の形態３の構成を示す平面図及び断面図であり、図４（ａ）は、この半導体装置の実装面側から見た平面図であり、図４（ｂ）は、図４（ａ）のＤ−Ｄ′における断面図である。ここでは、実施の形態１，２の半導体装置と異なる構成についてのみ説明する。
上述した実施の形態１，２は、半導体チップ１上に２次配線を形成した半導体装置であるが、本実施の形態３は、配線形成を行ったパッケージ基板４１を用いた半導体装置である。
【００４８】
パッケージ基板４１には、ガラス繊維にエポキシ樹脂を含有させたもの、ポリイミド系材料、セラミック材料等があり、配線は単層または複数層に形成されたものがある。パッケージ基板４１への半導体チップ1の搭載方法は、フェイスアップ方式（半導体チップ１の裏面側をパッケージ基板４１に接合。図４に相当）、及びフェイスダウン方式（半導体チップ１の素子面側をパッケージ基板４１に接合）がある。
【００４９】
フェイスアップ方式では、通常、金属細線（ボンディングワイヤ）６１で半導体チップ1の電極パッド２とパッケージ基板４１の配線５１，５２，５３とを電気的に接続する。
フェイスダウン方式では、バンプ、異方性導電膜等を用いて、半導体チップ１の電極パッド２とパッケージ基板４１の配線５１，５２，５３とを電気的に接続する。
【００５０】
本実施の形態３では，一例として、フェイスアップ方式を図示している（図４）。即ち、パッケージ基板４１に半導体チップ１の裏面側をダイアタッチ材料（図示せず）で接着し、金属細線（ボンディングワイヤ）６１でパッケージ基板４１のパッド５２と電極パッド２とを電気的に接続する。パッド５２は、配線５１により所望の電極５３と電気的な導通が確保されている。半導体チップ1のグランド端子から金属細線６１で電気的に接続されたパッド５２ａ，５２ｂは、その裏面の絶縁層４２に開口部４５が設けられており、この開口部４５を横切るように形成された配線形状の電極５４に、電気的に接続されている。パッド５２ａは、更に配線５１を介して電極５３ａにも接続されている。配線形状の電極５４は、実装面の外縁部に沿って延設されている。
【００５１】
また、グランド端子以外の電極パッド２と電気的に接続されたパッド５２については、配線形状の電極５４との間に絶縁層４２が介在し、絶縁されている。このような配線形状の電極５４の配置は、半導体装置の実装面が小さな場合に有効である。
本実施の形態３の半導体装置では、樹脂７１はトランスファモールドと呼ばれる方法で成型するが、液状樹脂を滴下するなどの方法もある。これは、半導体チップ１を外部からの物理的、化学的なダメージから保護する目的で形成しているので、樹脂以外にも金属、ガラス、セラミックス等で保護しても良い。
【００５２】
実施の形態４．
図５は、本発明に係るエリアアレイ型の半導体装置の実施の形態４の構成を示す平面図及び断面図であり、図５（ａ）は、この半導体装置の実装面側から見た平面図であり、図５（ｂ）は、図５（ａ）のＥ−Ｅ′における断面図である。ここでは、実施の形態１〜３の半導体装置と異なる構成についてのみ説明する。
上述した実施の形態１，２は、半導体チップ１上に２次配線を形成した半導体装置であり、電極パッド２を特にペリフェラルに（外縁部に）配置した場合に有効である。また、ペリフェラルタイプでなくても、既存の半導体チップ１を用いる場合には、２次配線を用いて自由に電極等を配置できるので有効である。
【００５３】
実施の形態４の半導体装置は、電極パッド２が半導体チップ１の中央部に配置されており、２次配線を用いて、電極等の再配置を行う必要がない場合の例である。半導体チップ１の実装面は絶縁層５で覆われており、絶縁層５には、電極パッド２及び配線形状の電極２′を露出するように、それぞれ開口部６及び開口部７が設けられている。
【００５４】
本実施の形態４のように、電極パッド２が、実装面全体ではなく、一部分に密集して存在する場合においても、実装面の外縁部に沿って延設された配線形状の電極２′の存在により、バンプを形成し基板実装を行う際に、バランスを崩して半導体装置が傾いてしまう等の不具合を防ぐことが出来る。
このように、半導体チップ１を新規に設計する場合は、配線形状の電極２′を設けることが出来るが、既存の場合、配線形状の電極２′を、実施の形態１，２のように、メッキ等で形成することも可能である。そのとき、２次配線によりグランド端子との接続を行っておくと、電磁波のシールド効果が更に向上する。
【００５５】
尚、実施の形態１〜４において説明してきた内容は、エリアアレイ型の半導体装置の中でも面実装タイプのものであるが、その他の例として、パッケージ底面にピン状の外部端子をグリッド状に垂直に立てて配置したピングリッドアレイ型の場合も考えられる。この場合は、基板実装後の接合強度を向上させるというよりも、むしろ電磁波をシールドする効果が重要である。このように、本発明の構成は、種々のエリアアレイ型の半導体装置に適用することが可能である。
【００５６】
【発明の効果】
本発明に係る半導体装置によれば、基板等への実装後の接合強度を向上させることが出来ると共に、基板等への実装後は、半導体装置から外部への電磁波放射と、外部からの電磁波の影響と、外部からの光の影響とを防止することが出来る半導体装置を実現することが出来る。また、電極が、実装面全体ではなく、一部分に密集して存在する場合においても、バランスを崩して半導体装置が傾いてしまう等の不具合を防ぐことが出来る。
【００５７】
また、本発明に係る半導体装置によれば、基板等への実装後の接合強度を向上させることが出来ると共に、基板等への実装後は、半導体装置から外部への電磁波放射と、外部からの電磁波の影響と、外部からの光の影響とを防止することが出来る半導体装置を実現することが出来る。また、アンダーフィル材等の絶縁材料を注入することができる為、基板等への実装後の接合強度を更に向上させることが出来る。また、バンプ形成時において印刷方式を用いる場合は、印刷マスクの開口領域によってマスキング領域を完全に囲い込むパターンとはならないので容易に作製出来る。
【００５８】
また、本発明に係る半導体装置によれば、基板等への実装後の接合強度を向上させることが出来ると共に、基板等への実装後は、半導体装置から外部への電磁波放射と、外部からの電磁波の影響とをより確実に防止することが出来る半導体装置を実現することが出来る。
【００５９】
また、本発明に係る半導体装置によれば、基板等への実装後の接合強度を向上させることが出来ると共に、基板等への実装後は、半導体装置から外部への電磁波放射と、外部からの電磁波の影響と、外部からの光の影響とを防止することが出来る半導体装置を実現することが出来る。また、半導体装置の実装面が小さな場合においても配線形状の電極を設けることができる。
【００６０】
また、本発明に係る半導体装置によれば、基板等への実装後の接合強度を向上させることが出来ると共に、基板等への実装後は、半導体装置から外部への電磁波放射と、外部からの電磁波の影響と、外部からの光の影響とを防止することが出来る半導体装置を実現することが出来る。また、実装の容易性を高めることが出来る。
【００６１】
また、本発明に係る半導体装置の製造方法によれば、配線形状の電極と、配線形状の電極以外の電極との上に、同時にしかも簡便にバンプ形成することが出来る半導体装置の製造方法を実現することが出来る。
【図面の簡単な説明】
【図１】本発明に係るエリアアレイ型の半導体装置の実施の形態の構成を示す平面図及び断面図である。
【図２】図１に示す半導体装置の電極及び配線形状の電極にバンプを形成した場合の構成例を示す平面図及び断面図である。
【図３】本発明に係るエリアアレイ型の半導体装置の実施の形態の構成を示す平面図及び断面図である。
【図４】本発明に係るエリアアレイ型の半導体装置の実施の形態の構成を示す平面図及び断面図である。
【図５】本発明に係るエリアアレイ型の半導体装置の実施の形態の構成を示す平面図及び断面図である。
【図６】図８に示す半導体装置の実装状態を得る方法の例を示す説明図である。
【図７】図２に示す半導体装置の実装基板への実装状態を得る方法の例を示す説明図である。
【図８】本発明に係る半導体装置の実装状態の一例を示す説明図である。
【図９】図１及び図２に示す半導体装置の製造工程の一例を示す説明図である。
【図１０】図３に示す半導体装置の製造工程の一例を示す説明図である。
【図１１】従来の半導体装置の模式的な構造例を示す断面図である。
【図１２】ガルウイング構造を有する半導体装置の模式的な構造例を示す断面図である。
【符号の説明】
１ 半導体チップ
２ 電極パッド(電極)
２′ 電極パッド(配線形状の電極)
２ａ，２ｂ 電極パッド（電極、グランド端子（固定電位を与えられた端子））
３，４，５，２１，４２，４３ 絶縁層
６，７，２２，２３，４４，４５ 開口部
１１，１３，１３ａ，１３ｂ ２次配線
１２，１２ａ ２次配線(電極)
１４，５４ 配線形状の電極
３１，３２ バンプ
４１，８１ 実装基板
５１ 配線
５２ 配線(パッド)
５３ 配線(電極)
６１ 金属細線（ボンディングワイヤ）
９１，９２ 配線(ランド)[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to an area array type semiconductor device having a mounting surface on which mounting electrodes for connection to the outside are formed,The substrate on which this semiconductor device is mounted,Manufacturing method of semiconductor deviceAnd mounting method of this semiconductor deviceIt is about.
[0002]
[Prior art]
In recent years, with the downsizing of electronic equipment, the production of area array type semiconductor devices in which external connection terminals are formed on the package body has been increased to accommodate the downsizing and high-density mounting of electronic components such as semiconductor devices. I'm following a course. As an example of this type of semiconductor device, there is a structure as shown in FIG. This is an area array semiconductor device of the type that performs packaging in wafer units. The feature of this is that the size of the semiconductor device after packaging is exactly the same size as the semiconductor chip.
[0003]
In this semiconductor device, a secondary wiring 11 is further formed on a semiconductor chip 1 in which an element (not shown), an electrode pad 2, and two insulating layers 3 and 4 are formed on the surface side, and these are formed as insulating layers. 21 covers. However, a wiring that electrically connects the element and the electrode pad 2 is a primary wiring (not shown), and a wiring that connects the electrode pad 2 and the outside is a secondary wiring.
In the insulating layer 21, a region that becomes the external connection terminal joint (electrode) 12 is exposed on the secondary wiring 11, and a bump 31 is formed. This type of semiconductor device has bump-shaped external connection terminals on the mounting surface of the main body, and is also called a BGA (Ball Grid Array).
[0004]
[Patent Document 1]
JP-A-8-330313
[0005]
[Problems to be solved by the invention]
In the above-described conventional semiconductor device, due to the difference in coefficient of linear expansion between the semiconductor device and the mounting substrate, after the semiconductor device is mounted on the mounting substrate, the external connection terminals are connected by the heat generation of the IC chip and the temperature change in the usage environment. There is a problem that thermal stress is generated in a certain bump, and bonding failure is likely to occur at the bump bonding portion.
[0006]
This is because, as shown in FIG. 12, the outer lead 33 as an external connection terminal protrudes from the side surface of the package 71, such as SOP (Small Outline Package), TSOP (Thin Small Outline Package), QFP (Quad Flat Package), etc. In a semiconductor device having a gull wing structure connected to the wiring 91 on the mounting substrate 81, the outer leads 33 are easily elastically deformed, so that thermal stress can be dispersed. On the other hand, in a conventional BGA type semiconductor device, This is because the elastic deformation of the bump is relatively small and stress concentration occurs in the joint.
[0007]
In addition, when a semiconductor chip that generates a strong electromagnetic wave or a semiconductor chip that easily malfunctions due to the influence of the electromagnetic wave is mounted on the semiconductor device, it is necessary to provide a shield cap that covers the semiconductor device. In this case, it is necessary to prepare a shield cap for each size of the semiconductor device, and there is a problem that the manufacturing process of the semiconductor device or the mounting process on the mounting substrate becomes complicated.
In particular, it is indispensable to shield these parts because the electromagnetic wave generated from the external connection terminal has a great influence on the semiconductor chip outside the device and the electromagnetic wave entering the element surface from the outside has a great influence on the semiconductor chip inside the device. It becomes.
[0008]
The present invention has been made in view of the circumstances as described above, and can improve the bonding strength after mounting on a substrate and the like, and after mounting on the substrate and the like, electromagnetic waves from the semiconductor device to the outside can be obtained. It is an object of the present invention to provide a semiconductor device capable of preventing radiation, the influence of external electromagnetic waves, and the influence of external light.
It is another object of the present invention to provide a method for manufacturing a semiconductor device, in which bumps can be simultaneously and simply formed on a wiring-shaped electrode and an electrode other than the wiring-shaped electrode.
[0009]
[Means for Solving the Problems]
  A semiconductor device according to the present invention includes:A semiconductor chip having a terminal group formed in a peripheral arrangement on the mounting surface and a first insulating layer provided on the surface layer side of the mounting surface and having an opening in each terminal of the terminal group.In semiconductor devices,One or a plurality of electrodes provided on the surface layer side of the first insulating layer in a region inside the terminal group and connected to any terminal of the terminal group; and the first region in a region outside the terminal group One or a plurality of wiring-shaped electrodes formed by patterning on the surface layer side of the insulating layer, an electrode provided in the inner region, and an electrode formed in the outer region have openings. A second insulating layer provided on the surface layer side of the one insulating layerIt is characterized by that.
  The semiconductor device according to the present invention further includes an electrode provided on a surface layer side of the first insulating layer in an inner region of the terminal group, and electrically connected to a signal terminal in the terminal group. The electrode having a shape is electrically connected to a ground terminal in the terminal group by a wiring formed by patterning..
[0010]
  A semiconductor device according to the present invention is formed in a peripheral arrangement on a mounting surface, includes a terminal group including a signal terminal and a ground terminal, and is provided on a surface layer side of the mounting surface, and has an opening in each terminal of the terminal group. In a semiconductor device including a semiconductor chip having one insulating layer, an electrode provided on a surface layer side of the first insulating layer in a region inside the terminal group and connected to the signal terminal by a wiring; and the first insulating layer A second insulating layer provided on a surface layer side of the layer, and one or a plurality of wiring-shaped electrodes formed by patterning on the surface layer side of the second insulating layer so as to overlap the terminal group. The second insulating layer is interposed between the electrode having the shape and the wiring, and the second insulating layer covers the signal terminal and the wiring in the terminal group and is connected to the signal terminal by the wiring. The electrode has an opening, and the front Characterized in that it has an opening selectively provided to connect the ground terminal to the electrodes electrically in the wiring shape.
  The semiconductor device according to the present invention is characterized in that bumps made of solder are provided on the electrodes connected to the signal terminals by wiring and the wiring-shaped electrodes..
[0011]
  A semiconductor device according to the present invention includes:A semiconductor device comprising a semiconductor chip having a terminal group formed in a peripheral arrangement on one surface, a semiconductor chip mounting surface for mounting the semiconductor chip, and a package substrate having a substrate mounting surface on the back side of the semiconductor chip mounting surface A substrate terminal group that is exposed to the semiconductor chip mounting surface and formed in a peripheral arrangement, and is electrically connected to each of the terminal groups of the semiconductor chip, and is provided in an inner region of the substrate terminal group. A substrate electrode connected to any substrate terminal of the terminal group by a substrate wiring and exposed to the substrate mounting surface, and one or a plurality of wirings formed by patterning on the substrate mounting surface in a region outside the substrate terminal group A substrate electrode having a shapeIt is characterized by that.
  The semiconductor device according to the present invention further includes a substrate electrode provided in an inner region of the substrate terminal group, electrically connected to a signal terminal in the terminal group of the semiconductor chip, and exposed to the substrate mounting surface. The wiring-shaped substrate electrode is connected to a substrate terminal electrically connected to a ground terminal in the terminal group by a wiring formed by patterning..
[0012]
  A semiconductor device according to the present invention has a peripheral arrangement on one surface, a semiconductor chip having a terminal group including a signal terminal and a ground terminal, a semiconductor chip mounting surface on which the semiconductor chip is mounted, and the semiconductor chip mounting surface In a semiconductor device comprising a package substrate having a substrate mounting surface on the back side, a substrate terminal group exposed to the semiconductor chip mounting surface and formed in a peripheral arrangement and electrically connected to the terminal group of the semiconductor chip, and A substrate electrode provided in an inner region of the substrate terminal group, electrically connected to the signal terminal, connected to the substrate terminal by substrate wiring, and exposed on the substrate mounting surface; and a substrate insulating layer of the package substrate One or a plurality of wiring-shaped substrate electrodes formed by patterning on the substrate mounting surface so as to overlap the substrate terminal group with a gap interposed therebetween. The substrate insulating layer is interposed between the wiring-shaped substrate electrode and the substrate wiring, and the substrate insulating layer has an opening in the substrate electrode connected to the substrate terminal by the substrate wiring The substrate terminal electrically connected to the ground terminal has an opening selectively provided for electrically connecting to the wiring-shaped substrate electrode.
[0013]
  The semiconductor device according to the present invention is characterized in that the substrate electrode electrically connected to the signal terminal and the wiring-shaped substrate electrode are provided with bumps made of solder.
  According to the present inventionThe substrate is a semiconductor device according to the present invention.By solderRealIt is equipped with.
[0014]
  A method of manufacturing a semiconductor device according to the present invention includes a terminal group formed in a peripheral arrangement on a mounting surface, a first insulating layer provided on the surface layer side of the mounting surface, and having an opening at each terminal of the terminal group. In a method of manufacturing a semiconductor device including a semiconductor chip having: one or a plurality of electrodes connected to any terminal of the terminal group on the surface layer side of the first insulating layer in a region inside the terminal group; Forming one or a plurality of wiring-shaped electrodes collectively on the surface layer side of the first insulating layer in the outer region of the terminal group by patterning; the electrodes provided in the inner region; and Forming a second insulating layer having an opening in an electrode formed in an outer region on the surface layer side of the first insulating layer.
  In the method of manufacturing a semiconductor device according to the present invention, in the step of forming by patterning, the signal terminal in the terminal group is electrically connected to the surface layer side of the first insulating layer in the region inside the terminal group. The wiring electrode is electrically connected to the ground terminal in the terminal group.
[0015]
  A manufacturing method of a semiconductor device according to the present invention is formed in a peripheral arrangement on a mounting surface, includes a terminal group including a signal terminal and a ground terminal, and is provided on a surface layer side of the mounting surface, and an opening is formed in each terminal of the terminal group. In a method of manufacturing a semiconductor device including a semiconductor chip having a first insulating layer having a wiring, electrodes and wires connected to the signal terminals are formed on a surface layer side of the first insulating layer in a region inside the terminal group. And the step of covering the signal terminal and the wiring on the surface layer side of the first insulating layer, and having an opening in the electrode connected to the signal terminal by the wiring, and selectively providing the ground terminal Forming a second insulating layer having the formed opening, and forming one or a plurality of wiring-shaped electrodes by patterning on the surface layer side of the second insulating layer so as to overlap the terminal group. To include And butterflies.
[0016]
  The method for manufacturing a semiconductor device according to the present invention is characterized in that bumps made of solder are collectively provided on the electrodes connected to the signal terminals by wiring and the wiring-shaped electrodes.
  The semiconductor device according to the present inventionImplementationThe method isA semiconductor device manufactured by the method of manufacturing a semiconductor device according to the present inventionElectrode and wiring-shaped electrodeBy solderIt is mounted on a substrate.
  The semiconductor device according to the present inventionImplementationThe method is characterized in that, when a plurality of wiring-shaped electrodes are formed, an underfill material is injected from between the plurality of wiring-shaped electrodes.
[0017]
  A method of manufacturing a semiconductor device according to the present invention includes a semiconductor chip having a terminal group formed in a peripheral arrangement on one surface, a semiconductor chip mounting surface on which the semiconductor chip is mounted, and a substrate on the back side of the semiconductor chip mounting surface. In a manufacturing method of a semiconductor device comprising a package substrate having a mounting surface, a substrate terminal group exposed on the semiconductor chip mounting surface and arranged peripherally, and provided in a region inside the substrate terminal group, the substrate terminal group A substrate electrode connected to the substrate terminal by a substrate wiring and exposed to the substrate mounting surface, and one or a plurality of wiring-shaped substrate electrodes on the substrate mounting surface in a region outside the substrate terminal group Forming by patterning, mounting of the semiconductor chip on the package substrate formed by the process, terminal group of the semiconductor chip and the substrate Characterized in that it comprises a step of performing Kogun and respective electrical connections.
[0018]
  In the method of manufacturing a semiconductor device according to the present invention, in the step of forming the package substrate, a substrate electrode exposed on the substrate mounting surface is formed in a region inside the substrate terminal group, and the wiring-shaped substrate electrode and The step of forming a wiring for connecting one or more of the substrate terminals by patterning and mounting the semiconductor chip on the package substrate includes electrically connecting the substrate electrode to a signal terminal in a terminal group of the semiconductor chip. The board terminal connected to the wiring-shaped board electrode is electrically connected to a ground terminal in the terminal group.
[0019]
  A method of manufacturing a semiconductor device according to the present invention includes a semiconductor chip formed in a peripheral arrangement on one surface and having a terminal group including a signal terminal and a ground terminal, a semiconductor chip mounting surface on which the semiconductor chip is mounted, and the semiconductor In a manufacturing method of a semiconductor device comprising a package substrate having a substrate mounting surface on the back side of a chip mounting surface, a substrate terminal group exposed on the semiconductor chip mounting surface and arranged as a peripheral, and an area inside the substrate terminal group Provided, connected to the substrate terminals of the substrate terminal group by substrate wiring, and formed with substrate electrodes exposed on the substrate mounting surface, and each opening is formed at a plurality of predetermined positions of the substrate insulating layer of the package substrate. Then, one or a plurality of wiring-shaped substrate electrodes are formed by patterning on the substrate mounting surface so as to overlap the substrate terminal group with the substrate insulating layer interposed therebetween. The semiconductor chip mounted on the package substrate formed by the step, the electrical connection of each of the terminal group of the semiconductor chip and the substrate terminal group, and the ground terminal. And a step of selectively connecting the substrate terminal to the substrate electrode having the wiring shape through the opening.
[0020]
  The method for manufacturing a semiconductor device according to the present invention is characterized in that the substrate electrodes exposed on the substrate mounting surface and the wiring-shaped substrate electrodes are collectively provided with solder bumps.
  The semiconductor device according to the present inventionImplementationThe method isA semiconductor device manufactured by the method of manufacturing a semiconductor device according to the present inventionA substrate electrode and a wiring-shaped substrate electrodeBy solderIt is mounted on a substrate.
  The semiconductor device according to the present inventionImplementationThe method is characterized in that when a plurality of wiring-shaped substrate electrodes are formed, an underfill material is injected between the plurality of wiring-shaped substrate electrodes.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described with reference to the drawings showing embodiments thereof.
Embodiment 1 FIG.
1A and 1B are a plan view and a cross-sectional view showing the configuration of a first embodiment of an area array type semiconductor device according to the present invention, and FIG. 1A is a plan view seen from the mounting surface side of the semiconductor device. FIG. 1B is a cross-sectional view taken along the line AA ′ of FIG. In this semiconductor device, an element (not shown), an electrode pad 2 (including 2a and 2b), and two insulating layers 3 and 4 are formed on the surface of a semiconductor chip 1.
[0022]
The insulating layer 3 is formed of an inorganic insulating layer such as silicon oxide, and the insulating layer 4 provided on the surface layer side of the insulating layer 3 is formed of a polyimide organic insulating layer. Although the insulating property is maintained only by the insulating layer 3, the insulating layer 4 is further formed here in order to suppress crosstalk or the like generated between the primary wiring and the secondary wiring. The insulating layer 3 may be organic, and any combination is conceivable, and three or more layers can be formed.
Insulating layers 3 and 4 are provided with openings so as to expose the region of electrode pad 2.
[0023]
A secondary wiring 11 electrically connected to the electrode pad 2 exposed from the opening of the insulating layer 4 is formed on the surface of the insulating layer 4, and the insulating layer 4 and the secondary wiring 11 are further connected to the insulating layer 21. Covered. Openings 22 and 23 are respectively formed in the insulating layer 21 so as to face desired regions 12 and 14 of the secondary wiring 11.
The region 12 is an electrode that can be electrically connected to the outside, and the region 14 is a wiring-shaped electrode that extends along the outer edge portion of the mounting surface, and can be electrically connected to the outside. The secondary wirings 11, 12 (electrodes 12), 14 (wiring-shaped electrodes 14) are formed on the same plane.
[0024]
Among the electrode pads 2, the electrode pads 2 a and 2 b are ground terminals (terminals to which a fixed potential is applied) and are electrically connected to the wiring-shaped electrode 14. In the first embodiment, the ground terminal 2a is also electrically connected to the electrode 12a. However, in some cases, such as when the mounting surface area is small, the electrode 12 that is electrically connected to the ground terminal is not provided. Is also possible.
If there is only one ground terminal, the secondary wiring 11 may be branched and electrically connected by the number of the plurality of wiring-shaped electrodes.
[0025]
In the first embodiment, the wiring-shaped electrode 14 and the ground terminal are electrically connected. However, even when the wiring-shaped electrode 14 is not connected, only the wiring-shaped electrode is present and the bonding strength after mounting is improved. It is possible to prevent the radiation of electromagnetic waves from the semiconductor chip 1 to the outside, the influence of the electromagnetic waves from the outside, and the influence of light from the outside. However, the shielding effect of electromagnetic waves is much improved when electrically connected to the ground terminal.
Further, in the first embodiment, the wiring-shaped electrode 14 is divided into two, but even in this case, it is possible to improve the bonding strength after mounting, and electromagnetic radiation from the semiconductor chip 1 to the outside can be improved. There is an effect of preventing the influence of electromagnetic waves from the outside and the influence of light from the outside.
[0026]
FIG. 8 is an explanatory view showing an example of a mounting state of the semiconductor device. The mounting substrate 81 in FIG. 8 and FIGS. 6 and 7 to be described later is a surface on which a semiconductor device is mounted, and any object such as a printed circuit board, a semiconductor chip, or a semiconductor device can be applied to a mounting object. I can do it.
In the mounted state of the semiconductor device shown in FIG. 8, the external connection terminals 31 and 32 are connected to the electrodes 12 and 14 and the lands 91 and 92 (wirings) on the mounting substrate 81, respectively.
[0027]
FIG. 6 is an explanatory diagram showing an example of a method for obtaining the mounting state of the semiconductor device shown in FIG.
In this method, the material to be the external connection terminals 31 and 32 is previously formed on the lands 91 and 92 of the mounting substrate 81. In this example, paste-like solder to be the external connection terminals 31 and 32 is printed in a desired region by a printing method, the mounting substrate 81 and the semiconductor device are aligned, and heat treatment is performed in a reflow furnace or the like for connection. .
[0028]
2A and 2B are a plan view and a cross-sectional view showing a configuration example in the case where bumps are formed on the electrode 12 and the wiring-shaped electrode 14 of the semiconductor device shown in FIG. 1, and FIG. It is the top view seen from the surface side, FIG.2 (b) is sectional drawing in BB 'of Fig.2 (a).
In this semiconductor device, bumps 31 and 32 made of solder are formed in advance on the electrodes 12 and 14. The bump material is not particularly limited, but in this example, solder is used.
[0029]
FIG. 7 is an explanatory diagram illustrating an example of a method for obtaining a mounting state of the semiconductor device illustrated in FIG. 2 on a mounting substrate.
In the method shown in FIG. 6 described above, solder is printed on the mounting substrate 81. In the example shown in FIG. 7, bumps 31 and 32 made of solder are formed in advance on the semiconductor device. Therefore, it is possible to connect the mounting substrate 81 only by supplying only a flux or a small amount of solder. If the bumps 31 and 32 are formed in advance in the semiconductor device, it is not necessary to adjust the height, inclination, etc. of the semiconductor device when mounting the substrate, so that the semiconductor device can be easily mounted on the mounting substrate.
[0030]
In the first embodiment, the wiring-shaped electrode 14 is divided into two as an example, but this shape has the following advantages. That is, since there is a gap between the bumps connected to the wiring-shaped electrode, it is possible to inject a liquid resin such as an underfill material from the gap after mounting. Therefore, if the injected liquid resin is cured, the bonding strength of the mounting can be further improved.
[0031]
Further, when a material containing particles such as solder paste is printed on a mounting substrate (including a semiconductor device), the metal mask is easier to print than the mesh screen because the printing material can easily pass through. However, when the wiring-shaped electrode 14 is not divided, it is very difficult to produce a mask. However, since it is divided, the mask can be easily produced.
[0032]
FIG. 9 is an explanatory diagram illustrating an example of a manufacturing process of the semiconductor device illustrated in FIGS. 1 and 2. In consideration of productivity, in the case of the semiconductor device shown in FIG. 1, it is preferable that the steps (a) to (c) are manufactured in units of wafers and singulated after the step (c). In the case of the semiconductor device shown in FIG. 2, the steps (a) to (e) are preferably manufactured in wafer units and separated into individual pieces after the step (c). still. In FIG. 9, the entire view of the semiconductor wafer is omitted, and only one semiconductor chip is illustrated.
Below, each process (a)-(e) is demonstrated.
In step (a), an element (not shown), an electrode pad 2, and insulating layers 3 and 4 are formed on the semiconductor chip 1, and openings of the insulating layers 3 and 4 are formed in the region of the electrode pad 2. Is formed.
[0033]
In the step (b), the secondary wirings 11, 12, and 14 are formed on the semiconductor chip 1. The secondary wiring patterning method includes lift-off, electrolytic plating, electroless plating, etching, printing, and the like. Various methods such as a combined method are conceivable, and various wiring materials are also conceivable.
Here, Au / Ni / Cu is formed by electrolytic plating. When the electrode pad 2 is mainly composed of Al, a barrier layer (not shown) such as Ti, Ti-W, or Cr is required. Here, a thin film of Ti—W is formed, and a Cu thin film (not shown) is formed on the entire surface of the semiconductor chip 1 by sputtering so as to adhere and form Cu plating.
[0034]
Next, after applying and drying a photosensitive resist, patterning is performed by photolithography, and Cu, Ni, and Au are formed in this order so that the secondary wirings 11, 12, and 14 have a desired pattern.
After the plating is completed, the resist is removed with a stripping solution, and the Cu and Ti-W sputtering formed film formed in a region other than the wiring pattern is removed with an etching solution using the wiring pattern of the secondary wirings 11, 12, and 14 as a mask. .
[0035]
In the step (c), the insulating layer 21 is formed, and various materials can be considered here as well. In the first embodiment, photosensitive polyimide is used.
First, a varnish of this material is applied and dried. Next, patterning is performed by photolithography, and openings 22 and 23 are provided in the region of the electrode 12 on the secondary wirings 11, 12 and 14 and the region of the wiring-shaped electrode 14, and cured by heat treatment. In the case of the semiconductor device shown in FIG. 1, after the insulating layer 21 is formed, it is separated into pieces by dicing or the like and completed. In order to facilitate the separation, the insulating films 3, 4, and 21 are preferably provided with openings in the dicing region in advance.
[0036]
In the case of the semiconductor device shown in FIG. 2, an example of the manufacturing method is as follows. In this case, considering productivity, after the step (c), the step (d) and the subsequent steps are performed without performing individualization. Various materials and forming methods can be considered for the bumps 31 and 32, but here, a printing method is used which can form the electrode 12 and the wiring-shaped electrode 14 simultaneously and easily. That is, after printing paste solder on the electrode 12 and the wiring electrode 14 in step (d) using a metal mask, in step (e), heat treatment is performed using a reflow furnace or the like. Form bumps. Next, when separated into pieces, the semiconductor device shown in FIG. 2 is completed.
[0037]
Embodiment 2. FIG.
3A and 3B are a plan view and a cross-sectional view showing the configuration of the area array type semiconductor device according to the second embodiment of the present invention, and FIG. FIG. 3B is a cross-sectional view taken along the line CC ′ of FIG. Here, only a configuration different from that of the semiconductor device of Embodiment 1 will be described.
In the first embodiment described above, the wiring is extended from the electrode pad on the semiconductor chip to the wiring-shaped electrode 14 extending along the outer edge portion of the mounting surface. However, in the second embodiment, the wiring shape is Since the electrode 14 is provided on the electrode pad 2, it is effective when the mounting surface of the semiconductor device is small.
[0038]
In the second embodiment, the opening 23 of the insulating layer 21 is provided on the secondary wiring 13 a electrically connected to the ground terminal 2 a of the semiconductor chip 1 on the mounting surface of the semiconductor device. A wiring-shaped electrode 14 is formed so as to cross the line.
On the other hand, an insulating layer 21 exists between the electrode pad 2 other than the ground terminal (or the secondary wiring 13 connected to the electrode pad 2 other than the ground terminal) and the wiring-shaped electrode 14 (FIG. 3 ( (Refer to the vicinity of the right electrode pad 2 drawn in b)), there is no electrical short circuit. Since other configurations are substantially the same as the configuration of the semiconductor device of the first embodiment, the description thereof is omitted.
[0039]
FIG. 10 is an explanatory diagram showing an example of a manufacturing process of the semiconductor device shown in FIG. As in the case of the first embodiment, in consideration of productivity, when the bumps are not formed, it is preferable that the steps (a) to (d) are manufactured in units of wafers and then separated into individual pieces. In the case where bumps are formed as in the semiconductor device shown in FIG. 3, the steps (a) to (f) are preferably manufactured in wafer units and separated into individual pieces after the step (f). In FIG. 10, the entire semiconductor wafer is omitted and only one semiconductor chip is shown.
Below, each process (a)-(f) is demonstrated.
In step (a), an element (not shown), an electrode pad 2, and insulating layers 3 and 4 are formed on the semiconductor chip 1, and openings of the insulating layers 3 and 4 are formed in the electrode pad 2 region. Forming.
[0040]
In the step (b), the secondary wirings 11, 12, and 13 on the semiconductor chip 1 can be formed by various methods as described in the first embodiment. However, here, the material of the secondary wirings 11, 12, and 13 is only Cu.
When the electrode pad 2 is mainly composed of Al, a barrier layer (not shown) such as Ti, Ti-W, or Cr is required. Here, similarly to the first embodiment, a Ti—W thin film is formed, and a Cu thin film (not shown) for closely attaching and forming Cu plating is formed on the entire surface of the semiconductor chip 1 by sputtering.
[0041]
Next, after applying and drying a photosensitive resist, the secondary wirings 11, 12, and 13 are formed in a desired pattern by photolithography, and Cu wiring is formed in the opening of the pattern by electrolytic plating.
After the plating is completed, the resist is removed with a stripping solution, and the Cu and Ti-W sputtering film formed in a region other than the wiring pattern is removed with an etching solution using the wiring pattern of the secondary wirings 11, 12, and 13 as a mask. .
[0042]
In the step (c), photosensitive polyimide is used for patterning by photolithography. Various materials are conceivable as the material of the insulating layer 21. Here, too, photosensitive polyimide is used as in the first embodiment.
However, openings are formed in the region 12 on the secondary wirings 11, 12 and 13 and the regions 13 a and 13 b (see FIG. 3A) on the secondary wiring where the wiring-shaped electrode 14 is formed in a later process. 22 and an opening 23 are provided.
Here, by providing the openings 23 in the regions 13a and 13b, the regions 13a and 13b of the secondary wiring electrically connected to the ground terminals 2a and 2b (see FIG. 3A) and the wiring-shaped electrodes 14 can be electrically connected. The insulating layer 21 is cured by heat treatment after the openings 22 and 23 are formed.
[0043]
In the second embodiment, it is necessary to further provide a wiring-shaped electrode 14. Again, electrolytic plating is used from various methods.
In the step (d), therefore, a Cu thin film is formed by sputtering. If necessary, a metal thin film having good adhesion to the underlying insulating layer 21 and the like may be formed under the Cu layer by sputtering or the like.
Next, a photosensitive resist is applied and dried, and patterning is performed by photolithography to provide a region for forming the wiring-shaped electrode 14 and an opening in the region 12. When the configuration of the wiring-shaped electrode 14 and the electrode 15 formed in the region 12 is Au / Ni / Cu, here, Cu, Ni, and Au are formed by electrolytic plating in this order.
[0044]
The opening of the photosensitive resist may be formed only in the region where the wiring-shaped electrode 14 is formed. In this case, only Cu is formed on the wiring-shaped electrode 14 at this stage, and the photosensitive resist and the Cu plating are formed. After removing the Cu thin film formed on the unnecessary portion other than the pattern, an Au / Ni thin film is further formed on the wiring-shaped electrode 14 and the electrode 15 by electroless plating or the like.
When the external connection terminals 31 and 32 are made of solder, Sn, which is a main component of the solder, is likely to diffuse into Cu. Therefore, it is necessary to form a Cu film with a thickness of several tens of μm or more with an electrode made of Cu alone. Therefore, it is necessary to form Ni as a barrier layer and to form Au in order to prevent oxidation of Ni and improve wettability of solder.
[0045]
As described above, since the process of further forming Au / Ni by electroless plating or the like becomes very complicated, opening of the photosensitive resist is also performed in the region of the electrode 12 and simultaneously with the formation of the wiring-shaped electrode 14. Au / Ni / Cu may be formed. After the Au / Ni / Cu plating is formed, the resist is removed with a stripping solution, and the other regions are formed by sputtering using the Au / Ni / Cu plating layer formed in the region 12 and the wiring-shaped electrode 14 formation region as a mask. Etching is performed on the film.
[0046]
As in the case of the semiconductor device shown in FIG. 1 described above, when bumps are not formed on the electrode 15 and the wiring-shaped electrode 14, the semiconductor wafer is separated into pieces after the step (d) to obtain the semiconductor device. In the case of forming the bumps, productivity is good when the steps (e) and the subsequent steps are performed without dividing into individual pieces.
Various types of bumps and methods for forming the bumps are conceivable. In step (e), solder paste is simultaneously printed on electrode 15 and wiring-shaped electrode 14 by a printing method. In step (f), Bumps are formed by heating using a reflow furnace or the like. Thereafter, the semiconductor device shown in FIG.
[0047]
Embodiment 3 FIG.
4A and 4B are a plan view and a cross-sectional view showing the configuration of Embodiment 3 of the area array type semiconductor device according to the present invention. FIG. 4A is a plan view of the semiconductor device viewed from the mounting surface side. FIG. 4B is a cross-sectional view taken along the line DD ′ of FIG. Here, only the configuration different from that of the semiconductor devices of the first and second embodiments will be described.
The first and second embodiments described above are semiconductor devices in which secondary wiring is formed on the semiconductor chip 1, but the third embodiment is a semiconductor device using the package substrate 41 on which wiring is formed.
[0048]
The package substrate 41 includes a glass fiber containing an epoxy resin, a polyimide material, a ceramic material, and the like, and the wiring is formed in a single layer or a plurality of layers. The mounting method of the semiconductor chip 1 on the package substrate 41 includes a face-up method (the back side of the semiconductor chip 1 is bonded to the package substrate 41, corresponding to FIG. 4), and a face-down method (the element surface side of the semiconductor chip 1 is packaged). Bonded to the substrate 41).
[0049]
In the face-up method, the electrode pad 2 of the semiconductor chip 1 and the wirings 51, 52, 53 of the package substrate 41 are usually electrically connected by a thin metal wire (bonding wire) 61.
In the face-down method, the electrode pad 2 of the semiconductor chip 1 and the wirings 51, 52, 53 of the package substrate 41 are electrically connected using bumps, anisotropic conductive films, and the like.
[0050]
In the third embodiment, as an example, a face-up method is illustrated (FIG. 4). That is, the back surface side of the semiconductor chip 1 is bonded to the package substrate 41 with a die attach material (not shown), and the pads 52 of the package substrate 41 and the electrode pads 2 are electrically connected with a metal thin wire (bonding wire) 61. . The pad 52 is electrically connected to the desired electrode 53 by the wiring 51. The pads 52 a and 52 b electrically connected from the ground terminal of the semiconductor chip 1 by the fine metal wires 61 are provided with an opening 45 in the insulating layer 42 on the back surface thereof, and are formed so as to cross the opening 45. It is electrically connected to the wiring-shaped electrode 54. The pad 52 a is further connected to the electrode 53 a via the wiring 51. The wiring-shaped electrode 54 extends along the outer edge of the mounting surface.
[0051]
In addition, the pad 52 electrically connected to the electrode pad 2 other than the ground terminal is insulated by interposing the insulating layer 42 between the electrode 54 having a wiring shape. The arrangement of the wiring-shaped electrode 54 is effective when the mounting surface of the semiconductor device is small.
In the semiconductor device of the third embodiment, the resin 71 is molded by a method called transfer molding, but there is a method of dropping a liquid resin. Since the semiconductor chip 1 is formed for the purpose of protecting it from physical and chemical damage from the outside, it may be protected by metal, glass, ceramics, etc. in addition to the resin.
[0052]
Embodiment 4 FIG.
5A and 5B are a plan view and a cross-sectional view showing the configuration of Embodiment 4 of the area array type semiconductor device according to the present invention, and FIG. 5A is a plan view seen from the mounting surface side of the semiconductor device. FIG. 5B is a cross-sectional view taken along the line EE ′ of FIG. Here, only a configuration different from that of the semiconductor devices of the first to third embodiments will be described.
The first and second embodiments described above are semiconductor devices in which the secondary wiring is formed on the semiconductor chip 1 and are effective when the electrode pad 2 is disposed on the peripheral (at the outer edge). Further, even if it is not a peripheral type, when the existing semiconductor chip 1 is used, it is effective because electrodes and the like can be arranged freely using secondary wiring.
[0053]
The semiconductor device according to the fourth embodiment is an example in which the electrode pad 2 is arranged at the center of the semiconductor chip 1 and it is not necessary to rearrange the electrodes or the like using the secondary wiring. The mounting surface of the semiconductor chip 1 is covered with an insulating layer 5, and the insulating layer 5 is provided with an opening 6 and an opening 7 so as to expose the electrode pad 2 and the wiring-shaped electrode 2 ′, respectively. Yes.
[0054]
Even in the case where the electrode pads 2 are densely present in a part rather than the entire mounting surface as in the fourth embodiment, the wiring-shaped electrode 2 ′ extending along the outer edge portion of the mounting surface Due to the presence, when the bump is formed and the substrate is mounted, it is possible to prevent problems such as the balance being lost and the semiconductor device being inclined.
As described above, when the semiconductor chip 1 is newly designed, the wiring-shaped electrode 2 ′ can be provided. However, in the existing case, the wiring-shaped electrode 2 ′ is provided as in the first and second embodiments. It can also be formed by plating or the like. At that time, if the secondary wiring is connected to the ground terminal, the electromagnetic wave shielding effect is further improved.
[0055]
The contents described in the first to fourth embodiments are the surface mount type among the area array type semiconductor devices. As another example, pin-shaped external terminals are vertically arranged in a grid shape on the bottom surface of the package. In the case of a pin grid array type arranged upright. In this case, the effect of shielding electromagnetic waves is more important than improving the bonding strength after mounting on the substrate. Thus, the configuration of the present invention can be applied to various area array type semiconductor devices.
[0056]
【The invention's effect】
According to the semiconductor device of the present invention, the bonding strength after mounting on a substrate or the like can be improved, and after mounting on the substrate or the like, electromagnetic radiation from the semiconductor device to the outside and electromagnetic waves from the outside can be improved. A semiconductor device that can prevent the influence and the influence of light from the outside can be realized. In addition, even when the electrodes are densely present in a part rather than the entire mounting surface, it is possible to prevent problems such as the balance being lost and the semiconductor device being inclined.
[0057]
In addition, according to the semiconductor device of the present invention, the bonding strength after mounting on the substrate or the like can be improved, and after mounting on the substrate or the like, electromagnetic radiation from the semiconductor device to the outside, and from the outside A semiconductor device that can prevent the influence of electromagnetic waves and the influence of light from the outside can be realized. In addition, since an insulating material such as an underfill material can be injected, the bonding strength after mounting on a substrate or the like can be further improved. Further, when a printing method is used at the time of bump formation, the pattern can be easily produced because the pattern does not completely surround the masking area by the opening area of the print mask.
[0058]
In addition, according to the semiconductor device of the present invention, the bonding strength after mounting on the substrate or the like can be improved, and after mounting on the substrate or the like, electromagnetic radiation from the semiconductor device to the outside, and from the outside A semiconductor device that can more reliably prevent the influence of electromagnetic waves can be realized.
[0059]
In addition, according to the semiconductor device of the present invention, the bonding strength after mounting on the substrate or the like can be improved, and after mounting on the substrate or the like, electromagnetic radiation from the semiconductor device to the outside, and from the outside A semiconductor device that can prevent the influence of electromagnetic waves and the influence of light from the outside can be realized. Further, even when the mounting surface of the semiconductor device is small, a wiring-shaped electrode can be provided.
[0060]
In addition, according to the semiconductor device of the present invention, the bonding strength after mounting on the substrate or the like can be improved, and after mounting on the substrate or the like, electromagnetic radiation from the semiconductor device to the outside, and from the outside A semiconductor device that can prevent the influence of electromagnetic waves and the influence of light from the outside can be realized. In addition, the ease of mounting can be improved.
[0061]
Further, according to the method for manufacturing a semiconductor device according to the present invention, a method for manufacturing a semiconductor device capable of simultaneously and simply forming a bump on a wiring-shaped electrode and an electrode other than the wiring-shaped electrode is realized. I can do it.
[Brief description of the drawings]
1A and 1B are a plan view and a cross-sectional view showing a configuration of an embodiment of an area array type semiconductor device according to the present invention.
FIGS. 2A and 2B are a plan view and a cross-sectional view illustrating a configuration example when bumps are formed on the electrodes of the semiconductor device and the wiring-shaped electrodes shown in FIG.
3A and 3B are a plan view and a cross-sectional view showing a configuration of an embodiment of an area array type semiconductor device according to the invention.
4A and 4B are a plan view and a cross-sectional view showing a configuration of an embodiment of an area array type semiconductor device according to the invention.
5A and 5B are a plan view and a cross-sectional view showing a configuration of an embodiment of an area array type semiconductor device according to the invention.
6 is an explanatory diagram showing an example of a method for obtaining the mounting state of the semiconductor device shown in FIG. 8; FIG.
7 is an explanatory diagram illustrating an example of a method for obtaining a mounting state of the semiconductor device illustrated in FIG. 2 on a mounting substrate;
FIG. 8 is an explanatory diagram showing an example of a mounted state of a semiconductor device according to the present invention.
9 is an explanatory diagram showing an example of a manufacturing process of the semiconductor device shown in FIGS. 1 and 2. FIG.
10 is an explanatory diagram showing an example of a manufacturing process of the semiconductor device shown in FIG. 3; FIG.
FIG. 11 is a cross-sectional view showing a schematic structure example of a conventional semiconductor device.
FIG. 12 is a cross-sectional view showing a schematic structural example of a semiconductor device having a gull wing structure.
[Explanation of symbols]
1 Semiconductor chip
2 Electrode pads (electrodes)
2 'electrode pad (wiring shaped electrode)
2a, 2b Electrode pads (electrodes, ground terminals (terminals to which a fixed potential is applied))
3, 4, 5, 21, 42, 43 Insulating layer
6, 7, 22, 23, 44, 45 opening
11, 13, 13a, 13b Secondary wiring
12, 12a Secondary wiring (electrode)
14,54 Wiring shaped electrodes
31, 32 Bump
41, 81 Mounting board
51 Wiring
52 Wiring (Pad)
53 Wiring (electrode)
61 Thin metal wire (bonding wire)
91, 92 Wiring (land)

Claims (21)

実装面にペリフェラル配置に形成された端子群と、前記実装面の表層側に設けられ、前記端子群の各端子に開口部を有する第１絶縁層とを有する半導体チップを備える半導体装置において、
前記端子群の内側の領域の前記第１絶縁層の表層側に設けられ、前記端子群の何れかの端子と接続された１又は複数の電極と、前記端子群の外側の領域の前記第１絶縁層の表層側にパターニングにより形成された１又は複数の配線形状の電極と、前記内側の領域に設けられた電極と前記外側の領域に形成された電極とに開口部を有し、前記第１絶縁層の表層側に設けられた第２絶縁層とを備えることを特徴とする半導体装置。 In a semiconductor device comprising a semiconductor chip having a terminal group formed in a peripheral arrangement on a mounting surface and a first insulating layer provided on the surface layer side of the mounting surface and having an opening in each terminal of the terminal group ,
One or a plurality of electrodes provided on the surface layer side of the first insulating layer in a region inside the terminal group and connected to any terminal of the terminal group; and the first region in a region outside the terminal group One or a plurality of wiring-shaped electrodes formed by patterning on the surface layer side of the insulating layer, an electrode provided in the inner region, and an electrode formed in the outer region have openings. A semiconductor device comprising: a second insulating layer provided on a surface layer side of the one insulating layer . 前記端子群の内側の領域の前記第１絶縁層の表層側に設けられ、前記端子群の内の信号端子に電気的に接続された電極を更に備え、前記配線形状の電極は、パターニングにより形成された配線により、前記端子群の内のグランド端子と電気的に接続されている請求項１記載の半導体装置。 The electrode further includes an electrode provided on a surface layer side of the first insulating layer in a region inside the terminal group and electrically connected to a signal terminal in the terminal group, and the wiring-shaped electrode is formed by patterning The semiconductor device according to claim 1, wherein the semiconductor device is electrically connected to a ground terminal in the terminal group by the formed wiring . 実装面にペリフェラル配置に形成され、信号端子及びグランド端子を含む端子群と、前記実装面の表層側に設けられ、前記端子群の各端子に開口部を有する第１絶縁層とを有する半導体チップを備える半導体装置において、
前記端子群の内側の領域の前記第１絶縁層の表層側に設けられ、前記信号端子に配線で接続された電極と、前記第１絶縁層の表層側に設けられた第２絶縁層と、前記端子群に重なるように、前記第２絶縁層の表層側にパターニングにより形成された１又は複数の配線形状の電極とを備え、該配線形状の電極及び前記配線の間に前記第２絶縁層が介在し、該第２絶縁層は、前記端子群の内の前記信号端子及び前記配線を覆うと共に、該信号端子に配線で接続された前記電極に開口部を有し、前記グランド端子を前記配線形状の電極と電気的に接続する為に選択的に設けられた開口部を有していることを特徴とする半導体装置。 A semiconductor chip having a peripheral arrangement on the mounting surface and including a terminal group including a signal terminal and a ground terminal, and a first insulating layer provided on the surface layer side of the mounting surface and having an opening at each terminal of the terminal group. In a semiconductor device comprising:
An electrode that is provided on the surface layer side of the first insulating layer in a region inside the terminal group and connected to the signal terminal by a wiring; a second insulating layer provided on the surface layer side of the first insulating layer; One or more wiring-shaped electrodes formed by patterning on the surface layer side of the second insulating layer so as to overlap the terminal group, and the second insulating layer between the wiring-shaped electrode and the wiring The second insulating layer covers the signal terminal and the wiring in the terminal group, and has an opening in the electrode connected by wiring to the signal terminal, and the ground terminal is A semiconductor device comprising an opening selectively provided for electrical connection with a wiring-shaped electrode . 前記信号端子と配線で接続された電極、及び前記配線形状の電極には、ハンダによるバンプが設けられている請求項１乃至３の何れか１つに記載の半導体装置。 4. The semiconductor device according to claim 1, wherein bumps made of solder are provided on the electrodes connected to the signal terminals by wiring and the wiring-shaped electrodes . 5. 一方の面にペリフェラル配置に形成された端子群を有する半導体チップと、該半導体チップを搭載する半導体チップ搭載面、及び該半導体チップ搭載面の裏側の基板実装面を有するパッケージ基板とを備える半導体装置において、
前記半導体チップ搭載面に露出してペリフェラル配置に形成され、前記半導体チップの端子群とそれぞれ電気的に接続された基板端子群と、該基板端子群の内側の領域に設けられ、該基板端子群の何れかの基板端子と基板配線で接続され、前記基板実装面に露出した基板電極と、前記基板端子群の外側の領域の前記基板実装面にパターニングにより形成された１又は複数の配線形状の基板電極とを備えることを特徴とする半導体装置。 A semiconductor device comprising a semiconductor chip having a terminal group formed in a peripheral arrangement on one surface, a semiconductor chip mounting surface for mounting the semiconductor chip, and a package substrate having a substrate mounting surface on the back side of the semiconductor chip mounting surface In
A substrate terminal group which is exposed to the semiconductor chip mounting surface and formed in a peripheral arrangement, and is electrically connected to each of the terminal groups of the semiconductor chip, and is provided in a region inside the substrate terminal group; One or a plurality of wiring shapes formed by patterning on the substrate mounting surface of the substrate electrodes exposed to the substrate mounting surface and the region outside the substrate terminal group. A semiconductor device comprising a substrate electrode . 前記基板端子群の内側の領域に設けられ、前記半導体チップの端子群の内の信号端子に電気的に接続され、前記基板実装面に露出した基板電極を更に備え、前記配線形状の基板電極は、前記端子群の内のグランド端子に電気的に接続された基板端子に、パターニングにより形成された配線により接続されている請求項５記載の半導体装置。 Provided in a region inside the substrate terminal group, electrically connected to a signal terminal in the terminal group of the semiconductor chip, further comprising a substrate electrode exposed on the substrate mounting surface, the wiring-shaped substrate electrode is 6. The semiconductor device according to claim 5, wherein the semiconductor device is connected to a substrate terminal electrically connected to a ground terminal in the terminal group by wiring formed by patterning . 一方の面にペリフェラル配置に形成され、信号端子及びグランド端子を含む端子群を有する半導体チップと、該半導体チップを搭載する半導体チップ搭載面、及び該半導体チップ搭載面の裏側の基板実装面を有するパッケージ基板とを備える半導体装置において、A semiconductor chip that is formed in a peripheral arrangement on one surface and has a terminal group including a signal terminal and a ground terminal, a semiconductor chip mounting surface on which the semiconductor chip is mounted, and a substrate mounting surface on the back side of the semiconductor chip mounting surface In a semiconductor device comprising a package substrate,
前記半導体チップ搭載面に露出してペリフェラル配置に形成され、前記半導体チップの端子群にそれぞれ電気的に接続された基板端子群と、該基板端子群の内側の領域に設けられ、前記信号端子に電気的に接続された基板端子に基板配線で接続され、前記基板実装面に露出した基板電極と、前記パッケージ基板の基板絶縁層を介在させて前記基板端子群に重なるように、前記基板実装面にパターニングにより形成された１又は複数の配線形状の基板電極とを備え、該配線形状の基板電極及び前記基板配線の間に前記基板絶縁層が介在A substrate terminal group exposed to the semiconductor chip mounting surface and formed in a peripheral arrangement, and electrically connected to each of the terminal groups of the semiconductor chip, and provided in a region inside the substrate terminal group, the signal terminal The board mounting surface is connected to a board terminal electrically connected to the board terminal group via a substrate wiring and exposed to the board mounting surface, and a substrate insulating layer of the package board is interposed therebetween. And one or a plurality of wiring-shaped substrate electrodes formed by patterning, and the substrate insulating layer is interposed between the wiring-shaped substrate electrode and the substrate wiring し、該基板絶縁層は、前記基板端子に基板配線で接続された前記基板電極に開口部を有し、前記グランド端子に電気的に接続された基板端子を、前記配線形状の基板電極と電気的に接続する為に選択的に設けられた開口部を有していることを特徴とする半導体装置。The substrate insulating layer has an opening in the substrate electrode connected to the substrate terminal by substrate wiring, and the substrate terminal electrically connected to the ground terminal is electrically connected to the wiring-shaped substrate electrode. A semiconductor device having an opening portion selectively provided for connection. 前記信号端子に電気的に接続された基板電極、及び前記配線形状の基板電極は、ハンダによるバンプが設けられている請求項５乃至７の何れか１つに記載の半導体装置。8. The semiconductor device according to claim 5, wherein the substrate electrode electrically connected to the signal terminal and the wiring-shaped substrate electrode are provided with solder bumps. 請求項１乃至８の何れか１つに記載の半導体装置がハンダにより実装されていることを特徴とする基板。 Substrate on which the semiconductor device according to any one of 請 Motomeko 1 to 8, characterized in that it is implemented by soldering. 実装面にペリフェラル配置に形成された端子群と、前記実装面の表層側に設けられ、前記端子群の各端子に開口部を有する第１絶縁層とを有する半導体チップを備える半導体装置の製造方法において、Method of manufacturing a semiconductor device comprising a semiconductor chip having a terminal group formed in a peripheral arrangement on a mounting surface and a first insulating layer provided on the surface layer side of the mounting surface and having an opening in each terminal of the terminal group In
前記端子群の内側の領域の前記第１絶縁層の表層側に、前記端子群の何れかの端子と接続された１又は複数の電極と、前記端子群の外側の領域の前記第１絶縁層の表層側に、１又は複数の配線形状の電極とを、一括してパターニングにより形成する工程と、前記内側の領域に設けられた電極と前記外側の領域に形成された電極とに開口部を有する第２絶縁層を、前記第１絶縁層の表層側に形成する工程とを含むことを特徴とする半導体装置の製造方法。One or a plurality of electrodes connected to any terminal of the terminal group on the surface layer side of the first insulating layer in the region inside the terminal group, and the first insulating layer in a region outside the terminal group And forming one or a plurality of wiring-shaped electrodes collectively by patterning on the surface layer side, and opening portions in the electrodes provided in the inner region and the electrodes formed in the outer region. Forming a second insulating layer having a surface of the first insulating layer on a surface layer side of the first insulating layer. 前記パターニングにより形成する工程では、前記端子群の内側の領域の前記第１絶縁層の表層側に、前記端子群の内の信号端子に電気的に接続された電極を形成し、前記配線形状の電極を、前記端子群の内のグランド端子と電気的に接続する請求項１０記載の半導体装置の製造方法。In the step of forming by patterning, an electrode electrically connected to a signal terminal in the terminal group is formed on a surface layer side of the first insulating layer in a region inside the terminal group, and the wiring shape The method for manufacturing a semiconductor device according to claim 10, wherein the electrode is electrically connected to a ground terminal in the terminal group. 実装面にペリフェラル配置に形成され、信号端子及びグランド端子を含む端子群と、前記実装面の表層側に設けられ、前記端子群の各端子に開口部を有する第１絶縁層とを有する半導体チップを備える半導体装置の製造方法において、A semiconductor chip having a peripheral arrangement on the mounting surface and including a terminal group including a signal terminal and a ground terminal, and a first insulating layer provided on the surface layer side of the mounting surface and having an opening at each terminal of the terminal group. In a method for manufacturing a semiconductor device comprising:
前記端子群の内側の領域の前記第１絶縁層の表層側に、前記信号端子に接続された配線及び電極を形成する工程と、前記第１絶縁層の表層側に、前記信号端子及び前記配線を覆うと共に、該信号端子に配線で接続された前記電極に開口部を有し、前記グランド端子に選択的に設けられた開口部を有する第２絶縁層を形成する工程と、該第２絶縁層の表層側に、前記端子群に重なるように、１又は複数の配線形状の電極をパターニングにより形成する工程とを含むことを特徴とする半導体装置の製造方法。Forming a wiring and an electrode connected to the signal terminal on a surface layer side of the first insulating layer in a region inside the terminal group; and the signal terminal and the wiring on a surface layer side of the first insulating layer Forming a second insulating layer having an opening in the electrode connected to the signal terminal by wiring and having an opening selectively provided in the ground terminal, and the second insulation Forming one or more wiring-shaped electrodes by patterning on the surface layer side of the layer so as to overlap the terminal group. 前記信号端子と配線で接続された電極、及び前記配線形状の電極には、一括してハンダによるバンプを設ける請求項１０乃至１２の何れか１つに記載の半導体装置の製造方法。13. The method of manufacturing a semiconductor device according to claim 10, wherein bumps made of solder are collectively provided on the electrodes connected to the signal terminals by wiring and the electrodes having the wiring shape. 請求項１０乃至１３の何れか１つに記載の半導体装置の製造方法により製造された半導体装置の電極と配線形状の電極とをハンダにより基板に実装することを特徴とする半導体装置の実装方法。 Mounting method of a semiconductor device, characterized in that to implement the electrodes of the semiconductor device manufactured by the manufacturing method of the semiconductor device and electrodes of wiring shape to the substrate by soldering as claimed in any one of 請 Motomeko 10-13 . 複数の配線形状の電極を形成した場合は、該複数の配線形状の電極の間からアンダーフィル材を注入する請求項１４記載の半導体装置の実装方法。 The method of mounting a semiconductor device according to claim 14, wherein when a plurality of wiring-shaped electrodes are formed, an underfill material is injected from between the plurality of wiring-shaped electrodes . 一方の面にペリフェラル配置に形成された端子群を有する半導体チップと、該半導体チップを搭載する半導体チップ搭載面、及び該半導体チップ搭載面の裏側の基板実装面を有するパッケージ基板とを備える半導体装置の製造方法において、A semiconductor device comprising a semiconductor chip having a terminal group formed in a peripheral arrangement on one surface, a semiconductor chip mounting surface for mounting the semiconductor chip, and a package substrate having a substrate mounting surface on the back side of the semiconductor chip mounting surface In the manufacturing method of
前記半導体チップ搭載面に露出してペリフェラル配置された基板端子群と、該基板端子群の内側の領域に設けられ、該基板端子群の何れかの基板端子と基板配線で接続され、前記基板実装面に露出した基板電極とを形成し、前記基板端子群の外側の領域の前記基板実装面に１又は複数の配線形状の基板電極をパターニングにより形成する工程と、該工程により形成された前記パッケージ基板への前記半導体チップの搭載と、該半導体チップの端子群及び前記基板端子群それぞれの電気的接続とを行う工程とを含むことを特徴とする半導体装置の製造方法。A substrate terminal group that is exposed on the semiconductor chip mounting surface and is disposed as a peripheral, and is provided in a region inside the substrate terminal group, and is connected to any one of the substrate terminals of the substrate terminal group by a substrate wiring. Forming a substrate electrode exposed on the surface, patterning one or a plurality of wiring-shaped substrate electrodes on the substrate mounting surface outside the substrate terminal group, and the package formed by the step A method of manufacturing a semiconductor device, comprising: mounting the semiconductor chip on a substrate; and electrically connecting the terminal group of the semiconductor chip and each of the substrate terminal group. 前記パッケージ基板を形成する工程は、前記基板端子群の内側の領域に、前記基板実装面に露出した基板電極を形成し、前記配線形状の基板電極と前記基板端子の１又は複数とを接続する配線を、パターニングにより形成し、前記パッケージ基板In the step of forming the package substrate, a substrate electrode exposed on the substrate mounting surface is formed in a region inside the substrate terminal group, and the wiring-shaped substrate electrode and one or more of the substrate terminals are connected. Wiring is formed by patterning, and the package substrate に前記半導体チップを搭載する工程は、前記基板電極を該半導体チップの端子群の内の信号端子に電気的に接続し、前記配線形状の基板電極に接続された前記基板端子を、前記端子群の内のグランド端子に電気的に接続する請求項１６記載の半導体装置の製造方法。The step of mounting the semiconductor chip on the semiconductor chip comprises electrically connecting the substrate electrode to a signal terminal in the terminal group of the semiconductor chip, and connecting the substrate terminal connected to the wiring-shaped substrate electrode to the terminal group. The method of manufacturing a semiconductor device according to claim 16, wherein the semiconductor device is electrically connected to a ground terminal. 一方の面にペリフェラル配置に形成され、信号端子及びグランド端子を含む端子群を有する半導体チップと、該半導体チップを搭載する半導体チップ搭載面、及び該半導体チップ搭載面の裏側の基板実装面を有するパッケージ基板とを備える半導体装置の製造方法において、A semiconductor chip that is formed in a peripheral arrangement on one surface and has a terminal group including a signal terminal and a ground terminal, a semiconductor chip mounting surface on which the semiconductor chip is mounted, and a substrate mounting surface on the back side of the semiconductor chip mounting surface In a method for manufacturing a semiconductor device comprising a package substrate,
前記半導体チップ搭載面に露出してペリフェラル配置された基板端子群と、該基板端子群の内側の領域に設けられ、該基板端子群の基板端子に基板配線で接続され、前記基板実装面に露出した基板電極とを形成し、前記パッケージ基板の基板絶縁層の所定の複数位置に各開口部を形成し、前記基板絶縁層を介在させて前記基板端子群に重なるように、前記基板実装面に１又は複数の配線形状の基板電極をパターニングにより形成する工程と、該工程により形成された前記パッケージ基板への前記半導体チップの搭載と、該半導体チップの端子群及び前記基板端子群それぞれの電気的接続と、前記グランド端子に電気的に接続された基板端子の、前記開口部を通じての選択的な前記配線形状の基板電極への電気的接続とを行う工程とを含むことを特徴とする半導体装置の製造方法。A substrate terminal group exposed on the semiconductor chip mounting surface and arranged as a peripheral, and provided in a region inside the substrate terminal group, connected to a substrate terminal of the substrate terminal group by a substrate wiring, and exposed to the substrate mounting surface Formed on the substrate mounting surface so as to overlap the substrate terminal group with the substrate insulating layer interposed therebetween, and forming openings at predetermined positions of the substrate insulating layer of the package substrate. A step of forming one or a plurality of wiring-shaped substrate electrodes by patterning, mounting of the semiconductor chip on the package substrate formed by the step, and electrical terminals of the semiconductor chip and each of the substrate terminal groups Connecting and electrically connecting the substrate terminal electrically connected to the ground terminal to the substrate electrode of the wiring shape selectively through the opening. The method of manufacturing a semiconductor device according to claim. 前記基板実装面に露出した基板電極、及び前記配線形状の基板電極は、一括してハンダによるバンプを設ける請求項１６乃至１８の何れか１つに記載の半導体装置の製造方法。19. The method of manufacturing a semiconductor device according to claim 16, wherein the substrate electrode exposed on the substrate mounting surface and the wiring-shaped substrate electrode are collectively provided with solder bumps. 請求項１６乃至１９の何れか１つに記載の半導体装置の製造方法により製造された半導体装置の基板電極と配線形状の基板電極とをハンダにより基板に実装することを特徴とする半導体装置の実装方法。 The solder between the substrate electrode and the substrate electrode of the wiring shape of the semiconductor device manufactured by the manufacturing method of the semiconductor device according to any one of 請 Motomeko 16 to 19 wherein a is mounted on the board Implementation method. 複数の配線形状の基板電極を形成した場合は、該複数の配線形状の基板電極の間からアンダーフィル材を注入する請求項２０記載の半導体装置の実装方法。 21. The semiconductor device mounting method according to claim 20, wherein when a plurality of wiring-shaped substrate electrodes are formed, an underfill material is injected from between the plurality of wiring-shaped substrate electrodes .
JP2003112052A 2003-04-16 2003-04-16 Semiconductor device, substrate, semiconductor device manufacturing method, and semiconductor device mounting method Expired - Fee Related JP3949077B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003112052A JP3949077B2 (en) 2003-04-16 2003-04-16 Semiconductor device, substrate, semiconductor device manufacturing method, and semiconductor device mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003112052A JP3949077B2 (en) 2003-04-16 2003-04-16 Semiconductor device, substrate, semiconductor device manufacturing method, and semiconductor device mounting method

Publications (2)

Publication Number Publication Date
JP2004319792A JP2004319792A (en) 2004-11-11
JP3949077B2 true JP3949077B2 (en) 2007-07-25

Family

ID=33472422

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003112052A Expired - Fee Related JP3949077B2 (en) 2003-04-16 2003-04-16 Semiconductor device, substrate, semiconductor device manufacturing method, and semiconductor device mounting method

Country Status (1)

Country Link
JP (1) JP3949077B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100744930B1 (en) * 2006-02-01 2007-08-01 삼성전기주식회사 Method for manufacturing ltcc module
JP2009238905A (en) * 2008-03-26 2009-10-15 Nippon Telegr & Teleph Corp <Ntt> Mounting structure and mounting method for semiconductor element
CN102484101A (en) 2009-08-13 2012-05-30 SKLink株式会社 Circuit board and method for producing same
JP4589450B1 (en) * 2009-08-13 2010-12-01 株式会社ＳＫＬｉｎｋ Circuit board manufacturing method

Also Published As

Publication number Publication date
JP2004319792A (en) 2004-11-11

Similar Documents

Publication Publication Date Title
US11508776B2 (en) Image sensor semiconductor packages and related methods
US10297582B2 (en) BVA interposer
JP3888854B2 (en) Manufacturing method of semiconductor integrated circuit
US7224073B2 (en) Substrate for solder joint
TWI392066B (en) Package structure and fabrication method thereof
JP2008244437A (en) Image sensor package having die receiving opening and method thereof
US6841884B2 (en) Semiconductor device
KR20140064618A (en) Semiconductor device and method for producing the same
JP2009094434A (en) Semiconductor device, and manufacturing method of the same
KR100271676B1 (en) Package and semiconductor device for semiconductor device and their manufacturing method
JP4494249B2 (en) Semiconductor device
JP3618212B2 (en) Semiconductor device and manufacturing method thereof
JP3949077B2 (en) Semiconductor device, substrate, semiconductor device manufacturing method, and semiconductor device mounting method
KR100642748B1 (en) Lead frame and package substrate, and package using the same
JPH11191571A (en) Semiconductor device and manufacture thereof
JP2003031727A (en) Semiconductor chip, production method therefor and semiconductor device using the same
JP3739632B2 (en) Semiconductor device and manufacturing method thereof
JP2005303021A (en) Wiring substrate, semiconductor device and manufacturing method thereof
JP3672885B2 (en) Semiconductor device
JP2004014568A (en) Semiconductor device
KR100246848B1 (en) Land grid array and a semiconductor package having a same
KR20240032441A (en) Semiconductor package and method of manufacturing the semiconductor package
JP2000299399A (en) Semiconductor device
CN116666314A (en) Semiconductor packaging structure and manufacturing method thereof
JP2000068415A (en) Manufacture of chip scale package device and the chip scale package device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050810

A977 Report on retrieval

Effective date: 20051226

Free format text: JAPANESE INTERMEDIATE CODE: A971007

A131 Notification of reasons for refusal

Effective date: 20061017

Free format text: JAPANESE INTERMEDIATE CODE: A131

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061215

A131 Notification of reasons for refusal

Effective date: 20070227

Free format text: JAPANESE INTERMEDIATE CODE: A131

A521 Written amendment

Effective date: 20070326

Free format text: JAPANESE INTERMEDIATE CODE: A523

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Effective date: 20070417

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Effective date: 20070417

Free format text: JAPANESE INTERMEDIATE CODE: A61

R150 Certificate of patent (=grant) or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 3

Free format text: PAYMENT UNTIL: 20100427

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 4

Free format text: PAYMENT UNTIL: 20110427

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120427

Year of fee payment: 5

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 5

Free format text: PAYMENT UNTIL: 20120427

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130427

Year of fee payment: 6

LAPS Cancellation because of no payment of annual fees