JP2009238905A - Mounting structure and mounting method for semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a mounting structure for a semiconductor element which can be applied to a compound semiconductor and can be miniaturized and has a hermetic seal-type sealing structure. <P>SOLUTION: The sealing structure 21 which is formed in an outer peripheral part of a semiconductor element substrate 1 by using a plurality of wiring layers 5, 8, 11 and 14 used for wiring of a function circuit and which surrounds the function circuit is formed. The sealing structure 21 is made to confront with a cap substrate 2 where a sealing structure 22 in a shape mirror-symmetrical to the sealing structure 21 is formed. The sealing structure 21 of the semiconductor element substrate 1 is bonded with the sealing structure 22 of the cap substrate 2 by bonding by a eutectic alloy whose eutectic temperature is not more than 300°C or surface activation bonding. Inter-wiring layer insulating film vias 6, 9 and 12 used for connecting a plurality of wiring layers forming the sealing structure 21 have narrow trench structures. Width of the inter-wiring insulating vias 6, 9 and 12 is set to be within five times the thickness of the upper wiring layers 8, 11 and 14, or to be twice, if desirable. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor element mounting structure and a semiconductor element mounting method, and more particularly to a semiconductor element mounting structure and a semiconductor element mounting method used in a high frequency band.

  Wafer level package (WLP) technology is a very effective means for miniaturization, high performance and economy of semiconductor device packages. Many of the conventional technologies are intended to be mounted on micro-electro-mechanical systems (MEMS) that require hermetic sealing, and most of the semiconductor micromachines are made of silicon (Si). Most of the conventional wafer level package technologies only consider compatibility with the Si process technology.

  For example, FIG. 6 is a schematic diagram showing a cross-sectional structure of a conventional example of a semiconductor element mounting structure. In FIG. 6A, a Si substrate 41 is drilled to produce a cavity structure, a functional circuit (IC) 42 is mounted in the cavity, and a cap substrate 43 that covers the functional circuit (IC) 42 is covered. Are bonded to the Si substrate convex portion 44 formed on the outer peripheral portion of the Si substrate 41 so as to surround the functional circuit (IC) 42 to form an airtight sealing structure.

  FIG. 6B shows a cap substrate 43 having a convex structure in which a functional circuit (IC) 42 is mounted on a Si substrate 41 and a cap convex portion 45 is formed on the outer peripheral portion of the cap substrate 43. A cavity structure for hermetically sealing the circuit 42 is employed. Usually, the material of the cap substrate 43 is often Si or glass.

  Here, Si fusion bonding (Silicon Fusion Bonding) is generally used for bonding between Si, but high temperature treatment of 100 ° C. or higher is required. Further, for joining Si and glass, as described in AVChavan et al .; “Batch-Processed Vacuum-Sealed Capacitive Pressure Sensors” of Non-Patent Document 1, IEEE JMEMS, 10, 580 (2001). Anodic bonding is widely used, but in order to promote the movement of sodium (Na) in the glass, a severe process of a temperature of 180 to 500 ° C. and a voltage of 200 to 1,000 V is required. For this reason, it cannot be applied to a semiconductor element substrate on which a circuit element sensitive to heat and voltage is mounted as the functional circuit 42, and its application is limited.

  In FIG. 6C, a functional circuit (IC) 42 is mounted on the Si substrate 41, and a material other than the Si substrate 41, such as metal, is connected to the outer peripheral portion of the Si substrate 41 as a connection portion with the cap substrate 43. Thus, a sealing structure is produced by forming the convex pattern 46, and a cavity structure for mounting the functional circuit 42 is produced. For bonding the convex pattern 46 having a sealing structure using metal or the like to the Si substrate 41, eutectic alloy bonding, solder bonding, Au thermocompression bonding (Gold Thermo-Compression Bonding) ) Is used.

  Solder bonding is a technique described in, for example, Chaio et al .; “Hermetic wafer bonding based on rapid thermal processing” of Non-Patent Document 2, Sensors and Actuators, A91, 398 (2001). For example, non-patent literature 3 B-W Min et al .; “A low-loss silicon-on-silicon DC-110-GHz resonance-free package”, IEEE MTT, 54, 710 (2006). It is a technique as described in.

  However, in the case of a semiconductor element typified by a compound semiconductor such as GaAs or InP, it is particularly sensitive to heat treatment, and heat treatment at 300 ° C. or higher cannot be performed in a later process. There are few reports of effective metallic materials that can be applied to structures. In addition, ZH. Liang et al .; “A wafer-level hermetic encapsulation for MEMS manufacture application”, IEEE Trans. There are cases of using adhesive bonding with organic materials as described in ADVP, 29, 513 (2006), but bonding strength with organic materials has weak bonding strength and vapor pressure. Is high, has aged deterioration, and cannot be hermetically sealed.

  The only report of wafer level packaging technology for the purpose of hermetic sealing of functional circuits on compound semiconductors is PC-Chien et al .; "MMIC Compatible Wafer-Level Packaging Technology", IPRM, 14 ( 2007), and its structure is shown in FIG. 6 (d). As shown in FIG. 6D, the semiconductor element mounting structure described in Non-Patent Document 5 includes a functional circuit (IC) 42 mounted on a semiconductor element substrate 41, an outer peripheral portion of the semiconductor element substrate 41, and In addition, a convex pattern 47 and a convex pattern 48 are formed on each of the outer peripheral portions of the cap substrate 43 as connection portions to form a sealing structure.

However, although the non-patent document 5 describes that a eutectic alloy is used for joining the convex pattern 47 and the convex pattern 48, there is no report on the material component or composition of the eutectic alloy. Further, a sealing structure using a single wiring layer is formed on both the semiconductor element substrate 41 and the cap substrate 43 on which the functional element 42 is mounted, and the depth of each cavity is at most 8 μm. In general, when the cavity depth is shallow and the cap substrate 43 is present near the semiconductor element substrate 41 on which the functional circuit 42 is mounted, it is mounted on the semiconductor element substrate 41 as a component of the functional circuit (IC) 42. The cap substrate 43 greatly affects the electromagnetic field distribution of the high-frequency element. This effect becomes more serious as the signal frequency handled increases. Further, since the operating characteristics change before and after the cap substrate 43 is mounted, there is a problem that the design of the functional circuit (IC) 42 is not good.
AVChavan et al .; “Batch-Processed Vacuum-Sealed Capacitive Pressure Sensors”, IEEE JMEMS, 10, 580 (2001). Chaio et al .; “Hermetic wafer bonding based on rapid thermal processing”, Sensors and Actuators, A91, 398 (2001) B-W Min et al .; “A low-loss silicon-on-silicon DC-110-GHz resonance-free package”, IEEE MTT, 54, 710 (2006) Z-H. Liang et al .; “A wafer-level hermetic encapsulation for MEMS manufacture application”, IEEE Trans. ADVP, 29, 513 (2006) PC-Chien et al .; “MMIC Compatible Wafer-Level Packaging Technology”, IPRM, 14 (2007)

  As described above, the conventional semiconductor element mounting technology has the following drawbacks.

  (1) Since the target is a functional circuit mounted on a Si substrate, the processing temperature of the mounting process (process process) by wafer level package technology is high, and the temperature-sensitive compound semiconductor device mounting structure Cannot be applied as.

  (2) Although there is a conventional example in which a sealing structure is produced using a convex structure using a single wiring layer, the depth of a cavity serving as a space for housing a semiconductor element substrate is shallow Since the cap substrate is arranged close to the functional circuit mounted on the semiconductor element substrate, the cap substrate greatly influences the high frequency characteristics of the functional circuit. ing.

  The present invention has been made to solve the disadvantages and problems of the prior art, and can be applied to compound semiconductors and can prevent the influence on the electrical operating characteristics of functional circuits. An object of the present invention is to provide a semiconductor element mounting structure having a hermetically sealed sealing structure and a semiconductor element mounting method.

  In order to solve the above-described problems, the present invention mainly employs the following mounting structure and mounting method.

  (1) A sealing structure using a wiring metal used for a functional circuit is provided on the outer peripheral portion of the semiconductor element substrate, and a cap substrate having a similar shaped sealing structure provided on the outer peripheral portion is prepared. By bonding, the hermetic sealing for the functional circuit on the semiconductor element substrate is realized.

  (2) The semiconductor element substrate on which the functional circuit is mounted and the cap substrate employ a eutectic alloy having a eutectic temperature of 300 ° C. or less or surface active bonding for direct connection.

  (3) Using a multilayer wiring layer used for the functional circuit, a sealing structure is formed in which metal wirings laminated in multiple layers are connected by an inter-wiring insulating film via having a narrow trench structure.

  More specifically, it comprises the following technical means.

  The first technical means is that the wiring of the functional circuit mounted on the surface is formed by two or more wiring layers with a wiring interlayer insulating film interposed therebetween, and at least the outer peripheral portion of the surface is used by using the wiring layer. In a semiconductor element mounting structure having a semiconductor element substrate in which a sealing structure surrounding the functional circuit is fabricated and having a cap substrate in which a sealing structure having a mirror image symmetry with the sealing structure of the semiconductor element substrate is formed. The sealing structure of the semiconductor element substrate and the sealing structure of the cap substrate are bonded using a eutectic alloy, or the sealing structure of the semiconductor element substrate and the sealing structure of the mounting substrate are bonded by surface activation bonding. It is characterized by direct bonding.

  According to a second technical means, in the semiconductor element mounting structure according to the first technical means, the cap substrate is made of any one of a semiconductor, ceramic, glass, glass ceramic, and Teflon (registered trademark). And

  According to a third technical means, in the semiconductor element mounting structure according to the second technical means, the semiconductor material forming the cap substrate is any one of GaAs, InP, InAs, InSb, Si, and Ge, or , GaAs, InP, InAs, InSb, Si, and Ge.

  According to a fourth technical means, in the semiconductor element mounting structure according to any one of the first to third technical means, the semiconductor element substrate is any one of GaAs, InP, InAs, InSb, Si, and Ge, Alternatively, it is made of a mixed crystal containing any of GaAs, InP, InAs, InSb, Si, and Ge.

  According to a fifth technical means, in the semiconductor element mounting structure according to any one of the first to fourth technical means, the wiring interlayer insulating film of the semiconductor element substrate is made of polyimide, BCB (benzcyclobutene), polysiloxane, It consists of either a parylene or an epoxy resin.

  According to a sixth technical means, in the semiconductor element mounting structure according to any one of the first to fifth technical means, the sealing structure of the mounting substrate and the sealing structure of the cap substrate are joined by a eutectic alloy. A eutectic alloy having a eutectic temperature of 300 ° C. or less among any one of InSn, SnBi, SnZn, SnAu, SnCu, or a eutectic alloy containing any of InSn, SnBi, SnZn, SnAu, SnCu. It is characterized by joining.

  According to a seventh technical means, in the semiconductor element mounting structure according to any one of the first to sixth technical means, a connection between an upper wiring layer and a lower wiring layer is used as a sealing structure of the semiconductor element substrate. The wiring interlayer insulating film via used in the above has a trench structure, and the width of the wiring interlayer insulating film via is within 5 times the thickness of the upper wiring layer.

  According to an eighth technical means, in the semiconductor element mounting structure according to the seventh technical means, the wiring interlayer insulating film via pattern has a plurality of parallel line structures or lattices as viewed from the upper layer side. It is a pattern including at least one of a mesh-like mesh structure or a staggered structure.

  According to a ninth technical means, in the semiconductor element mounting structure according to any one of the first to eighth technical means, the uppermost wiring layer of the plurality of wiring layers is covered with a metal that is difficult to oxidize. It is characterized by that.

  The tenth technical means uses the first wiring layer of the functional circuit formed on the semiconductor element substrate to produce a sealing structure surrounding the functional circuit on the outer periphery of the semiconductor element substrate; An inter-wiring insulating film is laminated on the first wiring layer, and a wiring interlayer insulating film via hole having a trench structure is formed on the outer periphery of the inter-wiring insulating film, and then a wiring metal is formed on the inter-wiring insulating film. To form a second wiring layer and fill the interlayer insulating film via hole with the wiring metal to connect the first wiring layer and the second wiring layer. Forming a second wiring interlayer insulating film via to form a sealing structure using the second wiring layer and repeating the sealing structure manufacturing process for the required number of wiring layers By the semiconductor element A step of producing a sealing structure in a multilayer on a plate, and a step of preparing a cap substrate and producing a sealing structure having a mirror image symmetry with the sealing structure produced on the semiconductor element substrate on the outer periphery of the cap substrate And a semiconductor element mounting method including at least a step of bonding the sealing structure of the semiconductor element substrate and the sealing structure of the cap substrate using a eutectic alloy, or directly bonding by surface activated bonding, It is characterized by doing.

  According to an eleventh technical means, in the semiconductor element mounting method according to the tenth technical means, a through-substrate via hole penetrating from the back surface of the semiconductor element substrate to the first wiring layer on the front surface is formed. The method further includes the step of filling the through-substrate via hole from the back side to form a through-substrate via and forming an electrode on the back surface of the semiconductor element substrate.

  According to a twelfth technical means, in the semiconductor element mounting method according to the tenth technical means, after forming a cap substrate through via hole penetrating from the wiring layer on the front surface of the cap substrate to the back surface side, The method further includes the step of filling the cap substrate through via hole from the front surface side to form a cap substrate through via and forming an electrode on the back surface of the cap substrate.

  A thirteenth technical means uses a eutectic alloy between the sealing structure of the semiconductor element substrate and the sealing structure of the cap substrate in the semiconductor element mounting method according to any one of the tenth to twelfth technical means. In the case of bonding, the semiconductor device substrate further includes a step of forming the eutectic alloy deposited on the sealing structure of the semiconductor element substrate or the sealing structure of the cap substrate as a spherical ball bump.

  According to the semiconductor element mounting structure and the semiconductor element mounting method of the present invention, the following effects can be obtained.

  (1) By using eutectic alloy bonding or surface activated bonding at 300 ° C. or lower as a bonding method for hermetic sealing, the process temperature at the time of mounting a semiconductor element can be suppressed to a low temperature of 300 ° C. or lower. Even when a compound semiconductor is mounted, it can be mounted without impairing the electrical characteristics of the functional element using the compound semiconductor.

  (2) To increase the number of process steps by creating a metal sealing structure on the outer periphery of the semiconductor element substrate using the same wiring layer as that used for wiring of the functional circuit on the semiconductor element substrate. Without, a sealing structure that at least surrounds the functional circuit can be produced.

  (3) By using a multilayer wiring layer used as a wiring layer of a functional circuit and stacking a sealing structure in multiple layers, a deep cavity structure can be produced as a space for housing a semiconductor element substrate. Therefore, a wiring structure that is not affected by the cap substrate can be manufactured as a functional circuit formed on the semiconductor element substrate, and the design of the functional circuit can be significantly improved. Therefore, even when a semiconductor element having a high frequency characteristic of a quasi-millimeter wave band / millimeter wave band or higher is mounted, the performance can be sufficiently obtained.

  (4) By using a wiring interlayer insulating film via having a narrow trench structure as a sealing structure formed in the outer peripheral portion, the sealing structure can be used as a functional circuit on a semiconductor element substrate in the wiring interlayer insulating film via. It can be made flat without being recessed from the portion, and the connection reliability can be improved.

  (5) The number of process steps can be greatly reduced by performing the metal burying step in the wiring interlayer insulating film via forming the sealing structure together with the manufacturing step of the upper wiring layer without providing it independently. Can do.

  Hereinafter, an example of a semiconductor device mounting structure and a semiconductor device mounting method according to the present invention will be described in detail with reference to the drawings.

(Features of the present invention)
Prior to the description of the embodiments of the present invention, the features of the present invention will be first outlined. The present invention relates to a semiconductor element mounting structure and a mounting method thereof that can be suitably applied as a compound semiconductor hermetic sealing wafer level package technology. A metal sealing structure that at least surrounds the functional circuit is provided on the outer peripheral portion of the semiconductor element substrate on which the functional circuit is formed using the multilayer wiring layer of two or more layers, and the functional circuit is provided, and The sealing structure on the semiconductor element substrate and the cap substrate having a mirror-symmetrical sealing structure are opposed to each other, and the sealing structures are bonded to each other using a eutectic alloy having a low eutectic temperature or surface activated. It is characterized by realizing a hermetic sealing type mounting structure that can be suitably applied even when a compound semiconductor element is mounted by sealing by using either direct bonding or bonding. Yes.

  That is, there are the following three points as the major features of the present invention.

  (1) A metal sealing structure is provided on the outer periphery of the semiconductor element substrate for hermetic sealing. The sealing structure can create a mounting structure with deep cavities without adding an additional process by diverting a multilayer wiring layer used for wiring of a functional circuit mounted on a semiconductor element substrate. It is said.

  (2) A metal sealing structure formed on the outer peripheral portion of the semiconductor element substrate using a multilayer wiring layer is not depressed more than other portions on the semiconductor element substrate in order to improve connection reliability. In order to make it flat, the upper and lower wiring layers are connected by wiring interlayer insulating film vias having a narrow trench structure. The width of the trench structure is within about 5 times the thickness of the upper wiring layer, preferably about twice. In addition, in order to reduce the number of process steps, the metal embedding process in the wiring interlayer insulating film via hole for forming the sealing structure on the outer peripheral portion of the semiconductor element substrate is performed together with the manufacturing process of the upper wiring layer. It is not provided independently.

  (3) Eutectic alloy bonding or surface activation is used for bonding the semiconductor element substrate mounted with the functional circuit wired by the multilayer wiring layer and the upper cap substrate in order to keep the process temperature low in the mounting assembly stage. Bonding (SAB: Surface Activated Bonding) is used. As a material for eutectic alloy bonding, a eutectic alloy having a eutectic temperature of 300 ° C. or lower is used, and SnAu (Sn 95%, Au 5%, eutectic temperature 217 ° C.) is optimal.

(First embodiment)
FIG. 1 is a schematic view illustrating a first embodiment relating to a semiconductor element mounting structure according to the present invention. FIG. 2 is a bird's eye view of the semiconductor mounting element exemplified in the first embodiment of the semiconductor element mounting structure according to the present invention.

  In FIG. 1, a semiconductor element substrate 1 is made of a semiconductor material such as GaAs, InP, InAs, InSb, Si, Ge, or a mixed crystal containing any of GaAs, InP, InAs, InSb, Si, Ge. As shown in FIG. 2A, a functional circuit is formed on the semiconductor element substrate 1 using active circuits such as transistors and diodes and passive elements such as capacitors, resistors and inductors. In the semiconductor element substrate 1, the signal line electrode 3 is disposed as a substrate back electrode on the back surface of the semiconductor element substrate 1 through the substrate through via 4. Through this signal line electrode 3, transmission / reception of a high frequency signal from the outside, application of a DC bias, sharing of a ground potential, and the like are performed. In the present embodiment, the signal line electrode 3 is formed on the back surface of the semiconductor element substrate 1 as the substrate back electrode, but the signal line electrode may be formed on the cap substrate 2 side.

  On the surface side where the functional circuit is formed on the semiconductor element substrate 1, a multilayer wiring layer used for wiring of the functional circuit is fabricated. In the case of FIG. 1, an example of four wiring layers is shown. Each wiring layer such as the first wiring layer 5, the second wiring layer 8, the third wiring layer 11, and the fourth wiring layer 14, and the first to second wiring interlayer insulating film vias 6, the second to second wiring layers. The wiring interlayer insulating film vias 9 and the third to fourth wiring interlayer insulating film vias 12 are either Au, Cu, Al, W or Au, Cu, Al, W. The first-second wiring interlayer insulating film 7, the second-third wiring interlayer insulating film 10, and the third-fourth wiring interlayer insulating film 13 are made of a metal material such as an alloy including any of the following: It is made of any organic material such as polyimide, BCB (benzcyclobutene), polysiloxane, parylene (Parylene, paraxylene resin), and epoxy resin, which are organic materials that can be easily thickened.

  Using the first, second, third, and fourth wiring layers 5, 8, 11, and 14, a sealing structure 21 for hermetic sealing is formed on the outer peripheral portion of the semiconductor element substrate 1. The sealing structure 21 is formed in a shape such as a rectangular frame as shown in FIG. 2 so as to surround the functional circuit on the semiconductor element substrate 1, and the width of the sealing structure 21 is about 10 to 200 μm.

  In order to ensure smoothness in the entire region in the semiconductor element (chip), the first, second, second, third and third wiring interlayer insulating film vias 6 used for the sealing structure 21 are used. , 9 and 12 use a trench structure that is narrower than the wiring width of the lower wiring layer, and the width of the trench structure is within 5 times the wiring thickness of the upper wiring layer, preferably about twice. And Various patterns of wiring interlayer insulating film vias are conceivable, and an example is shown in FIG.

  FIG. 3 is a schematic diagram of the structure of a wiring interlayer insulating film via hole used for connection between the second wiring layer 8 and the third wiring layer 11 of FIG. 1, and the (L) column on the left side of FIG. A top view as viewed from the upper third wiring layer 11 is shown in the right (R) column of FIG. 3, and a cross-sectional view as viewed from the lateral direction is shown. In FIG. 3, as an example, the second to third wiring interlayer insulating film via holes 20 before filling with the metal material of the second to third wiring interlayer insulating film vias 9 are viewed from the upper layer side. 3A shows an example of a plurality of parallel thin line structures in FIG. 3A, a lattice-like mesh structure in FIG. 3B, and a staggered structure in FIG. The film via is desirably a pattern including at least one of these. All of the patterns shown in FIG. 3 have a thin line trench structure, and in order to realize hermetic sealing, the second to third wiring interlayer insulating film via holes 20 are filled with a metal material. The formed second to third wiring interlayer insulating film vias 9 have a continuous structure.

  Note that the wiring layer forming the uppermost layer (fourth wiring layer 14 in the case of FIG. 1) exposes the metal of the wiring layer. In order to prevent this, it may be coated with a metal that is not easily oxidized, such as Au. Further, for the purpose of strengthening the connection with the cap substrate 2 (upper substrate), as shown in FIG. 1, a wiring layer forming the uppermost layer (in the case of FIG. 1, the fourth wiring layer 14) is used. The connection reinforcing wiring layer 17 for connection to the cap substrate 2 may be disposed at a place other than the sealing structure 21.

  The cap substrate 2 is made of a semiconductor such as GaAs, InP, InAs, InSb, Si, or Ge, or a semiconductor such as a mixed crystal containing any of GaAs, InP, InAs, InSb, Si, and Ge, or a ceramic, It is made of any airtight substrate such as glass, glass ceramics, Teflon (registered trademark) and the like, and as shown in FIG. The structure 22 is formed as a cap substrate wiring layer 15 using a metal material such as one of Au, Cu, Al, and W, or an alloy containing one of Au, Cu, Al, and W.

  Further, on the sealing structure 22 on the outer peripheral portion of the cap substrate 2, InSn (eutectic temperature 117 ° C.), SnBi (eutectic temperature 139 ° C.), SnZn (eutectic temperature 198 ° C.), SnAu (eutectic temperature 217 ° C.). 280 ° C.), SnCu (eutectic temperature 227 ° C.), etc., or a eutectic alloy containing any of these, a eutectic alloy having a eutectic temperature of 300 ° C. or lower is a bonding metal. 16, and a sealing structure 22 formed by using the fourth wiring layer 14 of the semiconductor element substrate 1 by eutectic alloy bonding, and a sealing structure 21 formed using the fourth wiring layer 14 of the semiconductor element substrate 1. By bonding through the bonding metal 16, the airtightness of the functional circuit mounted on the semiconductor element substrate 1 is ensured. Further, a cap substrate wiring layer 15 and a bonding metal 16 are formed in a mirror image symmetrical position with respect to the connection reinforcing wiring layer 17 of the semiconductor element substrate 1, and are connected to the connection reinforcing wiring layer 17 of the semiconductor element substrate 1. As a result, the bonding between the semiconductor element substrate 1 and the cap substrate 2 is strengthened.

  As described above, the bonding between the sealing structure 22 of the cap substrate 2 and the sealing structure 21 of the semiconductor element substrate 1 and the bonding between the connection reinforcing wiring layer 17 and the cap substrate wiring layer 15 of the semiconductor element substrate 1 are performed. Instead of using eutectic alloy bonding via the eutectic alloy of metal 16, bonding may be performed using surface activated bonding in which wiring metals forming the respective sealing structures are directly connected to each other. When surface activated bonding is used, it is not necessary to deposit a eutectic alloy as the bonding metal 16 on the sealing structure 22 of the cap substrate 2 or the cap substrate wiring layer 15.

  In the present embodiment, an example in which the signal line electrode 3 (substrate back electrode) is formed on the back surface side of the semiconductor element substrate 1 has been described. However, transmission / reception of a high-frequency signal from the outside, application of a DC bias, For example, the signal line electrode may be formed not on the semiconductor element substrate 1 side but on the back surface side of the cap substrate 2. When the signal line electrode is formed on the back side of the cap substrate 2, the cap substrate 2 used for forming the sealing structure 22 instead of the process of forming the signal line electrode 3 on the semiconductor element substrate 1 described above. After forming a cap substrate through via hole penetrating from the wiring layer on the front surface to the back surface side, filling the cap metal through via hole from the front surface side to form a cap substrate through via, and forming a cap substrate through via hole on the back surface of the cap substrate. What is necessary is just to make it the process of producing an electrode.

(Second Embodiment)
Next, an example of a manufacturing method for manufacturing the semiconductor element mounting structure shown in FIG. 1 will be described with respect to the semiconductor element mounting method according to the present invention. FIG. 4 is a schematic diagram for explaining an example of a manufacturing process related to a semiconductor element mounting method according to the present invention, and shows an example of manufacturing the semiconductor element mounting structure of FIG. 1 in the first embodiment. ing.

  First, a semiconductor element substrate 1 made of a semiconductor material such as GaAs, InP, InAs, InSb, Si, Ge, or a mixed crystal containing any of these is prepared, and a digital circuit, an analog circuit, or a microwave circuit is prepared. Functional circuits such as active circuits such as passive circuits composed of capacitors, resistors, inductors, and the like are manufactured. At the same time, a sealing structure 21 for bonding to the cap substrate 2 side is formed on the outer peripheral side of the semiconductor element substrate 1 by using a functional circuit wiring layer in this step of manufacturing the functional circuit. The wiring metal and wiring interlayer insulating film used for the wiring layer are the same materials as those used in the functional circuit.

  For example, when the wiring metal is Au and the wiring interlayer insulating film is BCB (benzcyclobutene), the first wiring layer 5 of Au has a thickness as shown in the first step of FIG. For example, it is manufactured with a thickness of 1 to 5 μm by using electroplating which is easy to form a film. The sealing structure 21 is also formed on the outer peripheral portion of the semiconductor element substrate 1 with a thickness of 1 to 5 μm and a width of 100 μm, for example, using the first wiring layer 5. Further, as a via hole manufacturing step, the first and second wiring interlayer insulating films 7 using BCB are spin-coated on the first wiring layer 5 with a thickness of, for example, 1 to 10 μm, and then fluorine-based. First and second wiring interlayer insulating film via holes 23 are formed by reactive ion etching.

  Next, as shown in the second step of FIG. 4B, that is, the wiring manufacturing process, the first to second wiring interlayer insulating film via holes 23 are individually filled with metal from the viewpoint of simplifying the manufacturing process ( The first-second wiring interlayer insulating film via hole 23 is filled with metal, that is, the first-second wiring interlayer insulating film via 6 is formed by the second wiring layer 8 which is the upper wiring layer. It is performed in a lump with the formation.

  Here, if the width of the first-second wiring interlayer insulating film via hole 23, that is, the first-second wiring interlayer insulating film via 6 is too large, the second wiring on the first-second wiring interlayer insulating film via-hole 23 will be described. Layer 8 will be depressed. Therefore, for the 1-2 wiring interlayer insulating film via hole 23 on the sealing structure 21, the second wiring layer 8 on the 1-2 wiring interlayer insulating film via hole 23 is used by using a narrow trench structure. The flatness of the sealing structure 21 is ensured. That is, by forming the wiring interlayer insulating film via 6 having a narrow trench structure, the sealing structure 21 is recessed in the wiring interlayer insulating film via 6 from other portions such as the functional circuit on the semiconductor element substrate 1. Therefore, it can be made flat and the connection reliability can be improved.

  The width of the trench structure using the first-second wiring interlayer insulating film via hole 23, that is, the first and second wiring interlayer insulating film vias 6, is equal to the wiring thickness of the second wiring layer 8 which is the upper wiring layer. Within 5 times, preferably around 2 times. For example, when the thickness of the second wiring layer 8 is 2 μm, the width of the trench structure is preferably about 4 μm, which is twice the thickness of the second wiring layer 8.

  Thereafter, as shown in the third process of FIG. 4C, the above-described via hole manufacturing process and the second process, that is, the wiring manufacturing process of FIG. Repeat as a process. In the example of FIG. 4, the semiconductor element mounting structure of FIG. 1 is manufactured, and a case of four layers is shown. In the third step, a wiring layer composed of a plurality of layers necessary for wiring of the functional circuit mounted on the semiconductor element substrate 1, for example, in the case of FIG. 4, the first wiring layer 5 and the second wiring layer 8 are used. In addition to forming four wiring layers of the third wiring layer 11 and the fourth wiring layer 14, the first to second wiring interlayer insulating film vias 6 and the second to third wiring interlayer insulating film vias 9 are formed. By forming the third to fourth wiring interlayer insulating film vias 12, the sealing structure 21 using a multilayer wiring layer surrounds the functional circuit and the wiring of the functional circuit in the outer peripheral portion of the semiconductor element substrate 1. As is produced.

  In the third step, the uppermost fourth wiring layer 14 may be used to form the connection reinforcing wiring layer 17 for strengthening the bonding with the cap substrate 2.

  Next, a through-substrate via hole is formed from the back surface of the semiconductor element substrate 1 so as to penetrate the semiconductor element substrate 1. For example, when the semiconductor element substrate 1 is a semiconductor material such as GaAs, InP, InAs, InSb, Si, Ge, or a mixed crystal containing any of these, chlorine-based reactive ion etching is used. Then, a substrate through via hole penetrating to the first wiring layer 5 on the surface of the semiconductor element substrate 1 is formed. Thereafter, as shown in the fourth step of FIG. 4D, that is, the back surface electrode manufacturing step, a metal such as Au is filled into the through-hole via hole from the back surface side of the semiconductor element substrate 1 to form the first wiring layer 5 and The connected through-substrate via 4 is formed, and the substrate back surface electrode 3, that is, the signal line electrode 3 is manufactured.

  Here, the through-substrate via 4 may be formed before the step of forming a multilayer wiring as shown in FIGS. 4A to 4C. In this case, the through-substrate via 4 is not penetrated into the back surface side of the semiconductor element substrate 1 but is only filled with metal from the front surface side of the semiconductor element substrate 1 into the through-hole via hole, as shown in FIG. After completion of the multilayer wiring through the process of FIG. 4C, the semiconductor element substrate 1 is polished from the back surface to expose the tip of the metal filled as the through-substrate vias 4, and then the substrate back surface electrode 3, that is, The signal line electrode 3 is produced.

  On the other hand, as shown in the fifth step of FIG. 4E, that is, the cap substrate manufacturing step, the cap substrate 2 side is formed on the cap substrate 2 in a mirror image symmetrical shape with the sealing structure 21 of the semiconductor element substrate 1. The sealing structure 22 is produced by the cap substrate wiring layer 15 made of a metal such as Au, and a eutectic alloy is deposited as the bonding metal 16 on the cap substrate wiring layer 15.

  As a eutectic alloy of the bonding metal 16, for example, as described in Japanese Patent No. 3640017 “Lead-free solder bump and its formation method” (Ishii et al.), A 6.2 μm thick SnAu (Au 5 %, Eutectic temperature 217 ° C.), an electron beam evaporation apparatus is used to alternately stack 600 layers of 600 nm Sn and 20 nm Au.

  Here, the bonding metal 16 may be formed not on the cap substrate wiring layer 15 side of the cap substrate 2 but on the fourth wiring layer 14 and connection reinforcing wiring layer 17 side of the semiconductor element substrate 1.

  Finally, the sealing structure 21 of the semiconductor element substrate 1 and the sealing structure 22 of the cap substrate 2 are brought into contact with each other, and the eutectic temperature of the eutectic alloy deposited on the sealing structure 22 of the cap substrate 2 as the bonding metal 16. Using the above temperature, for example, in the case of SnAu (Au 5%, eutectic temperature 217 ° C.), the semiconductor is bonded to each other using, for example, 220 ° C. of SnAu (Au 5%) eutectic temperature 217 ° C. or higher. The element mounting structure is completed.

  Here, the bonding of the semiconductor element substrate 1 and the cap substrate 2 is not performed by using a eutectic alloy as described above, but “low energy bonding by surface activation” (Yuki Suga, Materia, 35 (5), 476 (1996)), and surface activated bonding (SAB) can also be used. In the case of surface activation bonding, the surfaces to be bonded to each other of the two substrates to be bonded are etched by irradiation with an Ar ion beam or the like in vacuum, and then the activated metals are bonded directly. When surface activated bonding is used, it is not necessary to deposit a eutectic alloy as the bonding metal 16 on the sealing structure 22 of the cap substrate 2 as described above.

(Third embodiment)
Next, an example of the semiconductor element mounting method according to the present invention, which is different from the manufacturing method described in the second embodiment, will be described. FIG. 5 is a schematic diagram for explaining an example different from FIG. 4 of the manufacturing process relating to the semiconductor element mounting method according to the present invention, in which the sealing structures of the semiconductor element substrate 1 and the cap substrate 2 are made of eutectic alloy. In the case of bonding by bonding, a case is shown in which a bump insulating film is formed on the bonding surface between the semiconductor element substrate 1 and the cap substrate 2 and then a eutectic alloy is formed as a spherical ball bump. Yes.

  In FIG. 5, the above-described via hole fabrication is performed for the required number of wiring layers from the first step, that is, the functional circuit fabrication step in FIG. 5A, to the second step, that is, the wiring fabrication step in FIG. 5B. The first process of FIG. 4A described above as the second embodiment is repeated until the third process of FIG. 5C in which the process and the second process of FIG. 5B, that is, the wiring manufacturing process are repeated. To the third step of FIG. 4C are the same, and a detailed description thereof is omitted here.

  Thereafter, unlike the case of the second embodiment, as the fourth step of FIG. 5D, that is, the insulating film manufacturing step, the third to fourth wiring interlayer insulating films 13, the fourth wiring layer 14, A bump insulating film 18 made of an organic material such as BCB or polyimide is deposited on the connection reinforcing wiring layer 17. Further, the deposited insulating film 18 for bumps is polished by a chemical-mechanical polishing (CMP) method or a method of sealing structure 21 bonded to the cap substrate 2 side by a method such as drilling a via hole. The upper surfaces of the wiring layer 14 and the connection reinforcing wiring layer 17 are exposed.

  Thereafter, as in the fourth step of FIG. 4D of the second embodiment, that is, the back surface electrode manufacturing step, the semiconductor element substrate 1 penetrates from the back surface to the first wiring layer of the semiconductor element substrate 1. Thus, after the through-substrate via hole is formed, a metal such as Au is filled into the through-substrate via hole from the back surface side of the semiconductor element substrate 1 to form the through-substrate via 4, and the back substrate electrode 3, that is, the signal line electrode 3. Is made.

  On the other hand, as shown in the fifth step of FIG. 5E, that is, the cap substrate manufacturing step, the cap substrate 2 side is formed on the cap substrate 2 in a mirror image symmetrical shape with the sealing structure 21 of the semiconductor element substrate 1. The process until the sealing structure 22 is formed by the cap substrate wiring layer 15 made of a metal such as Au is the same as that in the second embodiment.

  Thereafter, as shown in the fifth step of FIG. 5E, a cap substrate-side bump insulating film 19 made of an organic material such as BCB or polyimide is formed on the cap substrate 2 and the cap substrate wiring layer 15. accumulate. Further, the deposited cap substrate side bump insulating film 19 is polished by chemical mechanical polishing (CMP), or a via hole is drilled in the deposited cap substrate side bump insulating film 19. The upper surface of the cap substrate wiring layer 15 (the sealing structure 22 and the wiring layer for strengthening connection) to be bonded to the first side is exposed. Further, a eutectic alloy for bonding to the semiconductor element substrate 1 side is deposited as the bonding metal 16 on the exposed cap substrate wiring layer 15.

  For example, when SnAu (Au 5%, eutectic temperature 217 ° C.) with a thickness of 6.2 μm is used as the eutectic alloy of the bonding metal 16, 600 nm of Sn and 20 nm of Au are alternately used by using an electron beam evaporation apparatus. 10 layers are laminated.

  Next, the cap substrate 2 is heated at a eutectic temperature of SnAu (Au 5%) of 217 ° C. or higher, for example, 220 ° C., and the eutectic alloy of the bonding metal 16 is bored to form a spherical ball bump. Mold.

  Here, the ball bumps of the bonding metal 16 may be formed not on the cap substrate wiring layer 15 side of the cap substrate 2 but on the fourth wiring layer 14 and the connection reinforcing wiring layer 17 side of the semiconductor element substrate 1. .

  Finally, the sealing structure 21 of the semiconductor element substrate 1 and the sealing structure 22 of the cap substrate 2 are brought into contact with each other. When the ball bumps of the bonding metal 16 are, for example, SnAu (Au 5%), SnAu (Au 5%) The semiconductor element mounting structure is completed by bonding each other at a crystal temperature of 217 ° C. or higher.

(Operational effect of the present invention)
As described in detail above, according to the semiconductor element mounting structure and the mounting method of the present invention, the following operational effects can be obtained.

  (1) When eutectic alloy bonding or surface activation bonding is used as a bonding method for performing hermetic sealing, and eutectic alloy bonding is used, the bonding metal 16 has a eutectic temperature of 300 ° C. or lower. Since the crystal alloy is used, the process temperature during mounting of the semiconductor element can be suppressed to a low temperature of 300 ° C. or lower, and even when the compound semiconductor is mounted, the electric power of the functional element using the compound semiconductor It is possible to mount without impairing the general characteristics.

  (2) By using the same wiring layer as that used for wiring of the functional circuit on the semiconductor element substrate 1, the sealing structure 21 can be manufactured without increasing the number of process steps.

  (3) The first and second, third, and fourth wiring layers 5, 8, 11, and 14 that are used as the wiring layers of the functional circuit are used to form the sealing structure 21 using the multilayer wiring layers. A deep cavity structure can be produced as a space for housing the semiconductor element substrate 1 by laminating the layers. Therefore, a wiring structure that is not affected by the cap substrate 2 can be produced as a functional circuit formed on the semiconductor element substrate 1, and the design of the functional circuit can be significantly improved. Therefore, even when a semiconductor element having a high frequency characteristic of a quasi-millimeter wave band / millimeter wave band or higher is mounted, the performance can be sufficiently obtained.

  (4) The first, second, second, third, and third to fourth wiring interlayer insulating film vias 6, 9, and 12 having a narrow trench structure are used as the sealing structure 21 formed in the outer peripheral portion. Thus, the sealing structure 21 can be made flat without being recessed from other portions such as a functional circuit on the semiconductor element substrate 1, and connection reliability can be improved.

  (5) Steps for forming the first, second, second, third and third wiring interlayer insulating film vias 6, 9, 12 for forming the sealing structure 1 are formed as upper wiring layers. By integrating with the step of performing the steps, the metal burying step in the first, second, second, third and third wiring interlayer insulating film via holes is not provided independently, so the number of process steps is greatly increased. To reduce.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view illustrating a first embodiment relating to a semiconductor element mounting structure according to the present invention; It is a bird's-eye view of the semiconductor mounting element illustrated in 1st Embodiment of the mounting structure of the semiconductor element which concerns on this invention. It is a schematic diagram of the structure of the via hole used for the connection of the 2nd wiring layer of FIG. 1, and a 3rd wiring layer. It is a schematic diagram for demonstrating an example of the manufacturing process regarding the mounting method of the semiconductor element which concerns on this invention. It is a schematic diagram for demonstrating the example different from FIG. 4 of the manufacturing process regarding the mounting method of the semiconductor element which concerns on this invention. It is a schematic diagram which shows the cross-section of the prior art example of a semiconductor element mounting structure.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor element substrate, 2 ... Cap board | substrate, 3 ... Signal line electrode (board | substrate back surface electrode), 4 ... Substrate through-via, 5 ... 1st wiring layer, 6 ... 1st-2nd wiring interlayer insulation-film via | via, 7 ... 1st-2nd wiring interlayer insulation film, 8 ... 2nd wiring layer, 9 ... 2nd-3rd wiring interlayer insulation film via, 10 ... 2nd-3rd wiring interlayer insulation film, 11 ... 3rd wiring layer, 12 ... 3rd-4th wiring interlayer insulation film via, 13 ... 3rd-4th wiring interlayer insulation film, 14 ... 4th wiring layer, 15 ... Cap board wiring layer, 16 ... Bond metal, 17... 4th wiring layer (connection reinforcing wiring layer), 18... Bump insulating film, 19... Cap substrate side bump insulating film, 20. Before filling), 21 ... sealing structure, 22 ... sealing structure, 23 ... first and second wiring interlayer insulating film via holes, 41 ... i substrate (semiconductor element substrate, functional circuit mounting substrate), 42 ... functional element (functional circuit: IC), 43 ... cap (cap substrate), 44 ... Si substrate convex portion (connecting portion with cap), 45 ... cap Convex part (connection part with substrate), 46 ... convex pattern (connection part with cap), 47 ... convex pattern (connection part with cap), 48 ... convex pattern (connection part with substrate).

Claims (13)

  The wiring of the functional circuit mounted on the surface is made of two or more wiring layers with a wiring interlayer insulating film interposed, and a sealing structure that surrounds at least the functional circuit on the outer periphery of the surface by using the wiring layer The semiconductor device mounting structure includes a cap substrate on which a sealing structure having a mirror image symmetrical to the sealing structure of the semiconductor device substrate is formed. The sealing structure of the cap substrate is bonded using a eutectic alloy, or the sealing structure of the semiconductor element substrate and the sealing structure of the mounting substrate are directly bonded by surface activated bonding. Mounting structure of semiconductor elements.   2. The semiconductor element mounting structure according to claim 1, wherein the cap substrate is made of any one of a semiconductor, ceramic, glass, glass ceramic, and Teflon (registered trademark).   3. The semiconductor element mounting structure according to claim 2, wherein a semiconductor material forming the cap substrate is one of GaAs, InP, InAs, InSb, Si, and Ge, or GaAs, InP, InAs, InSb, and Si. , Ge comprising a mixed crystal containing any one of Ge and Ge.   4. The semiconductor element mounting structure according to claim 1, wherein the semiconductor element substrate is one of GaAs, InP, InAs, InSb, Si, and Ge, or GaAs, InP, InAs, InSb, and Si. , Ge comprising a mixed crystal containing any one of Ge and Ge.   5. The semiconductor element mounting structure according to claim 1, wherein the wiring interlayer insulating film of the semiconductor element substrate is made of any one of polyimide, BCB (benzcyclobutene), polysiloxane, parylene, and epoxy resin. A mounting structure of a semiconductor element, characterized in that   6. The semiconductor device mounting structure according to claim 1, wherein when the mounting substrate sealing structure and the cap substrate sealing structure are bonded together by a eutectic alloy, InSn, SnBi, SnZn, SnAu, SnCu. Or a eutectic alloy containing any one of InSn, SnBi, SnZn, SnAu, and SnCu, which is bonded by a eutectic alloy having a eutectic temperature of 300 ° C. or lower. Mounting structure.   7. The semiconductor element mounting structure according to claim 1, wherein a wiring interlayer insulating film via used for connection between an upper wiring layer and a lower wiring layer has a trench structure as a sealing structure of the semiconductor element substrate. And a width of the wiring interlayer insulating film via is within 5 times the thickness of the upper wiring layer.   The semiconductor element mounting structure according to claim 7, wherein the wiring interlayer insulating film via pattern has a plurality of parallel line structures, a lattice-like mesh structure, or a staggered structure as viewed from the upper layer side. A mounting structure of a semiconductor element, wherein the pattern includes at least one of the following.   9. The semiconductor element mounting structure according to claim 1, wherein the uppermost wiring layer of the plurality of wiring layers is covered with a metal that is difficult to oxidize.   Using the first wiring layer of the functional circuit formed on the semiconductor element substrate to produce a sealing structure surrounding the functional circuit on the outer periphery of the semiconductor element substrate; and An inter-wiring insulating film is stacked thereon, a wiring interlayer insulating film via hole having a trench structure is formed in an outer peripheral portion of the inter-wiring insulating film, and then a wiring metal is stacked on the inter-wiring insulating film, A first wiring interlayer insulating film that connects the first wiring layer and the second wiring layer by forming the second wiring layer and filling the interlayer insulating film via hole with the wiring metal. A sealing structure manufacturing step of forming a via and forming a sealing structure using the second wiring layer and repeating the sealing structure manufacturing step for the required number of wiring layers, Sealing structure A plurality of layers, a step of preparing a cap substrate, a step of forming a sealing structure mirror-symmetrical with the sealing structure formed on the semiconductor element substrate on the outer periphery of the cap substrate, and the semiconductor element A method for mounting a semiconductor device, comprising at least a step of bonding a sealing structure of a substrate and a sealing structure of the cap substrate using a eutectic alloy or directly bonding by surface activated bonding.   11. The method of mounting a semiconductor element according to claim 10, wherein after forming a through-substrate via hole penetrating from the back surface of the semiconductor element substrate to the first wiring layer on the front surface, the wiring metal is connected to the through-substrate via hole from the back surface side. A method for mounting a semiconductor device, further comprising the steps of forming a through-substrate via and forming an electrode on the back surface of the semiconductor device substrate.   11. The method of mounting a semiconductor element according to claim 10, wherein after forming a cap substrate through via hole penetrating from the wiring layer on the front surface of the cap substrate to the back surface side, the wiring metal is filled into the via hole through the cap substrate from the front surface side. Then, a method of mounting a semiconductor device, further comprising the steps of forming a through-cap via and forming an electrode on the back surface of the cap substrate.   13. The method of mounting a semiconductor element according to claim 10, wherein when the sealing structure of the semiconductor element substrate and the sealing structure of the cap substrate are bonded using a eutectic alloy, the sealing of the semiconductor element substrate is performed. A method for mounting a semiconductor device, further comprising forming the eutectic alloy deposited on the structure or the sealing structure of the cap substrate as a spherical ball bump.

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