TWI550732B - Manufacturing method of chip package structure - Google Patents

Description

Chip package structure manufacturing method

The present invention relates to a method of fabricating a package structure, and more particularly to a method of fabricating a chip package structure.

Currently, in a semiconductor process, a chip package carrier is one of the package components that are often used. The chip package carrier is, for example, a multilayer circuit board which is mainly composed of a plurality of circuit layers and a plurality of dielectric layers alternately stacked.

In general, the above multilayer wiring board conventionally fabricates a multilayer wiring and a multilayer dielectric layer on a core substrate, and the core substrate is a carrier having a certain thickness. The multilayer wiring and the multilayer dielectric layer are alternately stacked on the core substrate by a fully additive process, a semi-additive process, a subtractive process, or other suitable method. . As the electronic components are thinned, if the thickness of the core substrate cannot be effectively reduced, it is disadvantageous to reduce the total thickness of the chip package structure. The thickness of the core substrate is thus required to be thinned to be disposed in a limited space of the electronic component. However, when the thickness of the core substrate is reduced, the thinned core substrate is insufficient in rigidity, so that it is easy to increase the difficulty in the substrate process and the packaging process and the defective rate.

The invention provides a method for fabricating a chip package structure, which has a chip package structure which does not have a carrier core layer structure and thus has a thin package thickness.

The present invention provides a method of fabricating a chip package structure that includes the following steps. First, a first carrier is provided. The first carrier includes a first surface and a patterned metal layer. The patterned metal layer is disposed on the first surface. Next, a dielectric layer is formed on the first surface to cover the patterned metal layer. Then, the patterned metal layer and the dielectric layer on the first carrier are transferred to a second carrier. Next, a plurality of wafers are disposed on the patterned metal layer to electrically connect the wafer to the patterned metal layer. Thereafter, an encapsulant is formed on the second carrier, and the encapsulant covers the wafer, the patterned metal layer, and the dielectric layer. Next, the second carrier is removed. Thereafter, the encapsulant and the dielectric layer between the wafers are diced to form a plurality of wafer package structures.

The present invention provides a method of fabricating a chip package structure that includes the following steps. First, a first carrier is provided. The first carrier includes a metal layer disposed on the first carrier. Next, a dielectric layer is formed on the metal layer. Transferring the metal layer and the dielectric layer on the first carrier to a second carrier, wherein the dielectric layer is attached to the second carrier. Next, the first carrier is removed to expose the metal layer, and the metal layer is subjected to a patterning process to form a patterned metal layer, the patterned metal layer comprising a plurality of conductive traces. Thereafter, a plurality of wafers are disposed on the patterned metal layer to electrically connect the wafer to the patterned metal layer. Next, an encapsulant is formed on the second carrier, and the encapsulant covers the wafer, the patterned metal layer, and the dielectric layer. After that, the second carrier is removed. Next, the encapsulant and the dielectric layer between the wafers are diced to form a plurality of wafer package structures.

Based on the above, the present invention forms a patterned metal layer and a dielectric layer on the first carrier, and then transfers the patterned metal layer and the dielectric layer to the second carrier for subsequent wafer bonding, encapsulation, etc. After the process, the second carrier is removed and the subsequent wafer packaging process is continued. In addition, the present invention can also form a metal layer and a dielectric layer on the first carrier, and then transfer the metal layer and the dielectric layer to the second carrier, and then pattern the metal layer and perform subsequent The wafer is bonded, covered by the encapsulant, and the like, and then the second carrier is removed to continue the subsequent wafer packaging process. Thus, the chip package structure process of the present invention can produce a chip package structure without a carrier core layer structure, thereby reducing the thickness of the chip package structure. In addition, the present invention firstly combines a patterned metal layer with a dielectric layer, and then forms an encapsulant covering the wafer, the patterned metal layer, and the dielectric layer, thereby enabling the wafer package structure of the present invention to have the two-stage sealing operation. Two kinds of adhesive layers, so it is possible to adjust the warpage of the package structure by selecting two different coefficients of thermal expansion (CTE).

The above described features and advantages of the invention will be apparent from the following description.

100, 200, 300, 400‧‧‧ chip package structure

100a, 200a, 300a, 400a‧‧‧ ball grid array package

100b, 200b, 300b, 400b‧‧‧Pat array package

110, 210, 310, 410‧‧‧ first carrier

112, 212, 312‧‧‧ first surface

120, 220, 320, 420‧‧‧ metal layers

122, 222, 322, 422‧‧‧ patterned metal layers

124a, 224a, 324a, 424a‧‧‧ pads

130, 230, 330, 430‧‧‧ dielectric layer

132, 432‧‧‧ openings

140, 240, 340, 440‧‧‧ second carrier

150, 250, 350, 450‧‧‧ wafers

160, 260, 360, 460‧‧‧ encapsulant

170, 270, 370, 470‧‧ ‧ solder balls

180, 280, 380, 480‧‧‧ mat type terminals

226, 324‧‧‧ connection layer

226a, 326a‧‧‧ conductive traces

228‧‧‧patterned coating

1A through 1I are cross-sectional views showing a method of fabricating a chip package structure in accordance with an embodiment of the present invention.

2A through 2I are cross-sectional views showing a method of fabricating a chip package structure in accordance with another embodiment of the present invention.

3A to 3I are diagrams showing a chip package structure according to another embodiment of the present invention. A schematic cross-sectional view of the fabrication process.

4A through 4I are cross-sectional views showing a method of fabricating a chip package structure in accordance with another embodiment of the present invention.

1A through 1I are cross-sectional views showing a method of fabricating a chip package structure in accordance with an embodiment of the present invention. Referring to FIG. 1A and FIG. 1B simultaneously, in the embodiment, the method for fabricating the chip package structure includes the following steps: First, a first carrier 110 is provided. The first carrier 110 includes a first surface 112 and a patterned metal layer 122. The patterned metal layer 122 is disposed on the first surface 112. In detail, in the embodiment, the method of disposing the patterned metal layer 122 on the first surface 112 may first form a metal layer 120 on the first surface 112 of the first carrier 110 as shown in FIG. 1A. Next, as shown in FIG. 1B, a metallization process is performed on the metal layer 120 to form the patterned metal layer 122. The patterned metal layer 122 includes a plurality of conductive traces 122a, wherein the patterning process is, for example, etching. Process.

Next, referring to FIG. 1C, a dielectric layer 130 is formed on the first surface 112. In the present embodiment, the dielectric layer 130 covers the patterned metal layer 122 in a comprehensive manner. Specifically, the dielectric layer 130 is, for example, an encapsulant and is overlaid on the patterned metal layer 122 by, for example, mold filling, but the present invention does not limit the material of the dielectric layer 130 and its formation on the first surface 112. On the way. Next, referring to FIG. 1C and FIG. 1D, the patterned metal layer 122 and the dielectric layer 130 on the first carrier 110 in FIG. 1C are transferred to the second carrier 140 of FIG. 1D. In detail, transferring the patterned metal layer 122 and dielectric The layer 130 is applied, for example, by attaching the second carrier 140 to the surface of the dielectric layer 130 of FIG. 1C, and then removing the first carrier 110 to expose the patterned metal layer 122.

Referring to FIG. 1E, a plurality of wafers 150 are disposed on the patterned metal layer 122, and the wafer 150 is electrically connected to the patterned metal layer 122. Thereafter, an encapsulant 160 is formed on the second carrier 140, and the encapsulant is encapsulated. The 160 covers the wafer 150, the patterned metal layer 122, and the dielectric layer 130. In the present embodiment, the wafer 150 is disposed on the patterned metal layer 122 in a flip-chip bonding manner, for example, but the present invention does not limit the manner in which the wafer 150 is disposed on the patterned metal layer 122. In the illustrated embodiment, the wafer 150 can also be disposed on the patterned metal layer 122, for example, by wire bonding.

Next, referring to FIG. 1E and FIG. 1F, the second carrier 140 of FIG. 1E is removed to expose the dielectric layer 130, and then a plurality of openings 132 as shown in FIG. 1F are formed in the dielectric layer 130. Where the opening 132 exposes a portion of the patterned metal layer 122. Then, the conductive material is filled in the opening 132 to form a plurality of pads 124a, wherein the pads 124a are electrically connected to the conductive traces 122a of the patterned metal layer 122, respectively. Thereafter, as shown in FIG. 1G, a singulation process is performed, that is, the encapsulant 160 and the dielectric layer 130 between the wafers 150 are diced to separate the wafers 150 from each other to form a plurality of wafer package structures 100. Thus, the process of the chip package structure 100 of the present embodiment is completed.

It should be noted that, in an embodiment of the present invention, a plurality of solder balls 170 may be separately disposed on the pads 124a, and then a singulation process may be performed to form a plurality of ball grid arrays as shown in FIG. 1H. (Ball Grid Array, BGA) package 100a enables the chip package structure to be connected to other electronic components through solder balls 170. In other embodiments of the present invention, a plurality of pads 124a may be formed to form a solder resist layer on the dielectric layer 130 and the pads. 124a, and corresponding pads 124a form a plurality of openings on the solder resist layer to define a ball placement area, and then a solder ball 170 is disposed in the ball placement area to connect the solder balls 170 to the pads 124a. Of course, in another embodiment of the present invention, a plurality of pad terminals 180 may be disposed on the pads 124a instead of the solder balls 170, and then a singulation process may be performed to form a plurality of pads as shown in FIG. A Land Grid Array (LGA) package 100b enables the chip package structure to be connected to other electronic components through the pad type terminal 180.

As such, the chip package structure 100 formed in this embodiment does not have a carrier core layer structure and a solder mask, thereby reducing the package thickness. In addition, in this embodiment, the encapsulant is used as the dielectric layer 130, and then the encapsulant 160 covering the wafer 150, the patterned metal layer 122, and the dielectric layer 130 is formed, and the two-stage sealing operation is performed to make the embodiment. The chip package structure 100 has two layers of encapsulant, so that the warpage of the chip package structure 100 can be adjusted by using two different encapsulation colloids of different coefficient of thermal expansion (CTE).

2A through 2I are cross-sectional views showing a method of fabricating a chip package structure in accordance with another embodiment of the present invention. It should be noted that the method of fabricating the chip package structure of the present embodiment is substantially similar to the method of fabricating the chip package structure of FIGS. 1A to 1I, and therefore the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the previous embodiment, and the detailed description is not repeated herein.

Referring to FIG. 2A to FIG. 2C simultaneously, the method for fabricating the chip package structure of the present embodiment is to first provide the first carrier 210, wherein the first carrier 210 includes the first surface 212 and the patterned metal layer 222, and is patterned. The metal layer 222 is disposed on the first surface 212. In this embodiment, the patterned metal layer 222 is disposed on the first surface 212. As shown in FIG. 2A, a metal layer 220 is formed on the first carrier 210 and surface-treated on the metal layer 220 to form a patterned plating layer 228. Next, as shown in FIG. 2B, the metal layer 220 is patterned by using the patterned plating layer 228 as a mask to form a patterned metal layer 222. The patterned metal layer 222 includes a connecting layer 226 and a plurality of connections. Pad 224a, and pad 224a is located on connection layer 226. In detail, the patterning process is, for example, a half etching process, that is, only a plurality of pads 224a are etched on the metal layer 220 of FIG. 2A, and the pads 224a are still connected to each other by the connection layer 226.

Next, as shown in FIG. 2C, a dielectric layer 230 is formed on the first surface 212. In this embodiment, the dielectric layer 230 is at least filled between the pads 224a and exposes one surface of the pad 224a. In other embodiments of the invention not shown, the dielectric layer 230 may also be completely Covering pads 224a. Specifically, the dielectric layer 230 is, for example, a solder resist layer, and is filled between the pads 224a by printing and coating. Of course, the invention is not limited thereto. Next, referring to FIG. 2C and FIG. 2D, the patterned metal layer 222 and the dielectric layer 230 on the first carrier 210 in FIG. 2C are transferred to the second carrier 240 of FIG. 2D. In this embodiment, the method of transferring the patterned metal layer 222 and the dielectric layer 230 is, for example, attaching the second carrier 240 to the exposed surface of the dielectric layer 230 and the pad 224a in FIG. 2C, and then removing the second carrier 240. The first carrier 210 exposes the connection layer 226 of the patterned metal layer 222. Next, referring to FIG. 2D and FIG. 2E, a patterning process is performed on the connection layer 226 in FIG. 2D to form a plurality of conductive traces 226a corresponding to the pads 224a in FIG. 2E.

Next, as shown in FIG. 2F, a plurality of wafers 250 are disposed on the conductive traces 226a of the patterned metal layer 222, so that the wafers 250 are electrically connected to the conductive traces 226a, and then reshaped. The encapsulant 260 is formed on the second carrier 240, and the encapsulant 260 covers the wafer 250, the patterned metal layer 222, and the dielectric layer 230. In the present embodiment, the wafer 250 is disposed on the patterned metal layer 222 in a flip-chip bonding manner, for example, but the present invention does not limit the manner in which the wafer 250 is disposed on the patterned metal layer 222. 2F and 2G, the second carrier 240 of FIG. After being covered by the dielectric layer 230, after the second carrier 240 is removed, the corresponding pad 224a forms an opening in the dielectric layer 230 to expose the surface of the pad 224a. Then, a singulation process is performed, that is, the encapsulant 260 and the dielectric layer 230 between the wafers 250 are diced to form a plurality of chip package structures 200. Thus, the process of the chip package structure 200 of the present embodiment is completed.

It should be noted that in an embodiment of the present invention, it may also be as in the previous embodiment. The plurality of solder balls 270 are respectively disposed on the exposed surface of the pad 224a, and then subjected to a singulation process to form a plurality of the ball grid array packages 200a as shown in FIG. 2H, so that the chip package structure can be transmitted through the solder. Ball 270 is coupled to other electronic components. In other embodiments of the present invention, after the second carrier 240 is removed and the pads 224a are exposed, a solder resist layer is formed on the dielectric layer 230 and the pads 224a, and correspondingly connected. The pad 224a forms a plurality of openings in the solder resist layer to define a ball placement area, and then a solder ball 270 is disposed in the ball placement area to connect the solder balls 270 to the pads 224a. In another embodiment of the present invention, a plurality of pad type terminals 280 may be disposed on the exposed surface of the pad 224a instead of the solder balls 280, and then singulation process may be performed to form a plurality of soldering lines as shown in FIG. 2I. The pad array package 200b enables the chip package structure to be connected to other electronic components through the pad type terminal 280.

3A through 3I are diagrams of a wafer package junction in accordance with another embodiment of the present invention. A cross-sectional view of the fabrication method of the structure. It should be noted that the method of fabricating the chip package structure of the present embodiment is substantially similar to the method of fabricating the chip package structure of FIGS. 1A to 1I, and therefore the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the above embodiment, and the description is not repeated herein.

Referring to FIG. 3A to FIG. 3C simultaneously, the method for fabricating the chip package structure of the present embodiment is also to provide a first carrier 310, wherein the first carrier 310 includes a first surface 312 and a patterned metal layer 322, and the patterned metal Layer 322 is disposed on first surface 312. In this embodiment, the method of disposing the patterned metal layer 322 on the first surface 312 may first provide a metal layer 320 as shown in FIG. 3A. The metal layer 320 includes a connection layer 324 and a plurality of conductive traces. 326a, the conductive traces 326a are located on the connection layer 324, that is, the conductive traces 326a are connected to each other by the connection layer 324. Next, referring to FIG. 3B, the metal layer 320 is disposed on the first carrier 310, and the conductive trace 326a is attached to the first carrier 310. Thereafter, please refer to FIG. 3B and FIG. 3C simultaneously to the metal in FIG. 3B. The connection layer 324 of the layer 320 is patterned to form a plurality of pads 324a corresponding to the conductive traces 326a. The patterned metal layer 322 is formed by the conductive traces 326a and the pads 324a of the corresponding conductive traces 326a.

Next, referring to FIG. 3D, a dielectric layer 330 is formed on the first surface 312. In this embodiment, the dielectric layer 330 is at least filled between the pads 324a and the conductive traces 326a and exposes a surface of the pads 324a. In other embodiments of the invention, the dielectric layer The 330 can also completely cover the pads 324a. Specifically, the dielectric layer 330 is, for example, a solder resist layer, and is filled between the pads 324a and the conductive traces 326a by printing coating, or the dielectric layer 330 is, for example, an encapsulant, and is filled with, for example, a mold. Way to fill in The pad 324a and the conductive trace 326a are disposed between the pads 324a. Of course, the invention is not limited thereto. Then, referring to FIG. 3D and FIG. 3E, the patterned metal layer 322 and the dielectric layer 330 on the first carrier 310 in FIG. 3D are transferred to a second carrier 340. In this embodiment, the method of transferring the patterned metal layer 322 and the dielectric layer 330 is, for example, attaching the second carrier 340 to the exposed surface of the dielectric layer 330 and the pad 324a of FIG. 3D, and then removing the A carrier 310 is exposed to expose conductive traces 326a.

In the above, please refer to FIG. 3F, a plurality of wafers 350 are disposed on the conductive traces 326a of the patterned metal layer 322, and the wafers 350 are electrically connected to the conductive traces 326a. Thereafter, an encapsulant 360 is formed on the second carrier 340, and the encapsulant 360 covers the wafer 350, the patterned metal layer 322, and the dielectric layer 330. Next, referring to FIG. 3F and FIG. 3G, the second carrier 340 of FIG. 3F is removed to expose the pad 324a. In other embodiments of the invention, if the pad 324a is dielectrically After the layer 330 is covered, after the second carrier 340 is removed, the corresponding pad 324a forms an opening in the dielectric layer 330 to expose the surface of the pad 324a. A singulation process is then performed to form a plurality of wafer package structures 300. Thus, the process of the chip package structure 300 of the present embodiment is completed. It should be noted that, in an embodiment of the present invention, a plurality of solder balls 370 may be separately disposed on the exposed surface of the pad 324a, and then subjected to a singulation process to form a plurality of balls as shown in FIG. 3H. The array package 300a enables the chip package structure to be connected to other electronic components through solder balls 370. In other embodiments of the present invention, after the second carrier 340 is removed and the pads 324a are exposed, a solder resist layer is formed on the dielectric layer 330 and the pads 324a, and corresponding pads are formed. 324a forms a plurality of openings in the solder resist layer to define a ball placement area, and then sets a solder ball 370 in the ball placement area to connect the solder balls 370 to the pads 324a. In this hair In another embodiment, a plurality of pad terminals 380 may be disposed on the pads 324a instead of the solder balls 370, and then a singulation process may be performed to form a plurality of pad array packages 300b as shown in FIG. The chip package structure can be connected to other electronic components through the pad type terminal 380.

4A through 4I are cross-sectional views showing a method of fabricating a chip package structure in accordance with another embodiment of the present invention. It should be noted that the method of fabricating the chip package structure of the present embodiment is substantially similar to the method of fabricating the chip package structure of FIGS. 1A to 1I, and therefore the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the above embodiment, and the description is not repeated herein.

Referring to FIG. 4A, the method for fabricating the chip package structure of the embodiment includes the following steps: First, a first carrier 410 is provided. The first carrier 410 includes a metal layer 420 disposed on the first carrier 410. Next, as shown in FIG. 4B, a dielectric layer 430 is formed on the metal layer 420. Thereafter, referring to FIG. 4B and FIG. 4C, the metal layer 420 and the dielectric layer 430 on the first carrier 410 in FIG. 4B are transferred to the second carrier 440 in FIG. 4C. In this embodiment, the metal layer 420 and the dielectric layer 430 are transferred, for example, by attaching the second carrier 440 to the surface of the dielectric layer 430 of FIG. 4B, and then removing the first carrier 410 to expose A metal layer 420 is exited. Next, referring to FIG. 4C and FIG. 4D, a metallization process is performed on the metal layer 420 of FIG. 4C to form the patterned metal layer 422 of FIG. 4D, wherein the patterned metal layer 422 includes a plurality of conductive traces 422a. In other words, the chip package structure of the present embodiment is formed by first forming a metal layer 420 on the first carrier 410, then placing the dielectric layer 430 on the metal layer 420, and then transferring the metal layer 420 and the dielectric layer. 430 to the second carrier 440, after which the patterning process is performed to form the patterned metal layer 422. The foregoing embodiment forms a pattern at the beginning. The metal layer is on the first carrier, and then the steps of disposing the dielectric layer, transferring the patterned metal layer, and the dielectric layer to the second carrier are performed.

Referring to FIG. 4E, a plurality of wafers 450 are disposed on the patterned metal layer 422, and the wafer 450 is electrically connected to the patterned metal layer 422. Thereafter, an encapsulant 460 is formed on the second carrier 440. The encapsulant 460 covers the wafer 450, the patterned metal layer 422, and the dielectric layer 430. In the present embodiment, the wafer 450 is disposed on the patterned metal layer 422 in a flip-chip bonding manner, for example. Next, referring to FIG. 4E and FIG. 4F, the second carrier 440 of FIG. 4E is removed to expose the dielectric layer 430, and then a plurality of openings 432 are formed in the exposed dielectric layer 430. The opening 432 exposes a portion of the patterned metal layer 422. A conductive material is then filled in the opening 432 to form a plurality of pads 424a. Thereafter, as shown in FIG. 4G, a singulation process is performed, that is, the encapsulant 460 and the dielectric layer 430 between the wafers 450 are diced to form a plurality of wafer package structures 400. Thus, the process of the chip package structure 400 of the present embodiment is completed. It should be noted that, in an embodiment of the present invention, a plurality of solder balls 470 may be separately disposed on the pads 424a, and then singulated to form a plurality of ball grid array packages as shown in FIG. 4H. 400a enables the chip package structure to be connected to other electronic components through solder balls 470. In another embodiment of the present invention, a plurality of pad terminals 480 may be disposed on the pads 424a instead of the solder balls 470, and then a singulation process may be performed to form a plurality of pad array packages as shown in FIG. 4I. 400b, the chip package structure can be connected to other electronic components through the pad type terminal 480.

In summary, the present invention forms a patterned metal layer and a dielectric layer on the first carrier, and then transfers the patterned metal layer and the dielectric layer to the second carrier for subsequent wafer bonding and over-packaging. After the colloid and other processes, then remove the second carrier and continue Into the subsequent chip packaging process. In addition, the present invention can also form a metal layer and a dielectric layer on the first carrier, and then transfer the metal layer and the dielectric layer to the second carrier, and then pattern the metal layer and perform subsequent The wafer is bonded, covered by the encapsulant, and the like, and then the second carrier is removed to continue the subsequent wafer packaging process. Thus, the chip package structure process of the present invention can produce a chip package structure without a carrier core layer structure, thereby reducing the thickness of the chip package structure. In addition, the present invention firstly combines a patterned metal layer with a dielectric layer, and then forms an encapsulant covering the wafer, the patterned metal layer, and the dielectric layer, thereby enabling the wafer package structure of the present invention to have the two-stage sealing operation. Two kinds of adhesive layers, so it is possible to adjust the warpage of the package structure by selecting two different coefficients of thermal expansion (CTE).

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧ Chip package structure

122‧‧‧ patterned metal layer

122a‧‧‧conductive traces

124a‧‧‧ pads

130‧‧‧Dielectric layer

132‧‧‧ openings

150‧‧‧ wafer

160‧‧‧Package colloid

Claims (17)

A method of fabricating a chip package structure includes: providing a first carrier, the first carrier comprising a first surface and a patterned metal layer, wherein the patterned metal layer is disposed on the first surface; forming a dielectric layer An electric layer is disposed on the first surface to cover the patterned metal layer; the patterned metal layer and the dielectric layer on the first carrier are transferred to a second carrier; and a plurality of wafers are disposed thereon On the patterned metal layer, the wafers are electrically connected to the patterned metal layer; an encapsulant is formed on the second carrier, and the encapsulant covers the wafer, the patterned metal layer and the dielectric layer Removing the second carrier; and cutting the encapsulant between the wafers and the dielectric layer to form a plurality of wafer package structures. The method of fabricating a chip package structure according to claim 1, wherein the first carrier is provided, and the step of the first carrier including the first surface and the patterned metal layer further comprises: forming a metal layer On the first carrier; and performing a patterning process on the metal layer to form the patterned metal layer, the patterned metal layer comprising a plurality of conductive traces. The method of fabricating a chip package structure according to claim 2, wherein the dielectric layer on the first carrier and the dielectric layer are transferred to the second carrier, the dielectric layer Attach the second carrier. The method for fabricating a chip package structure according to claim 3, further comprising: after removing the second carrier, forming a plurality of openings in the exposed dielectric layer, the openings exposing portions thereof The patterned metal layer; The conductive material is filled in the openings to form a plurality of pads, and the pads are electrically connected to the conductive traces respectively. The method for fabricating a chip package structure according to claim 4, further comprising: separately providing a plurality of solder balls on the pads. The method of fabricating a chip package structure according to claim 1, wherein the first carrier is provided, and the step of the first carrier including the first surface and the patterned metal layer further comprises: forming a metal layer On the first carrier; and performing a patterning process on the metal layer to form the patterned metal layer, the patterned metal layer includes a connection layer and a plurality of pads, wherein the pads are located on the connection layer on. The method of fabricating a chip package structure according to claim 6, wherein the dielectric layer is at least filled between the pads. The method of fabricating a chip package structure according to claim 7, wherein the dielectric layer on the first carrier and the dielectric layer are transferred to the second carrier Attach the second carrier. The method for fabricating a chip package structure according to claim 8 , further comprising: after transferring the patterned metal layer on the first carrier and the dielectric layer to the second carrier, The connecting layer performs a patterning process to form a plurality of conductive traces corresponding to the pads, so that the wafers are disposed on the conductive traces, and the transistors are electrically connected to the conductive traces. The method for fabricating a chip package structure according to claim 9 further includes: after removing the second carrier, respectively, a plurality of solder balls are disposed on the pads. A method of fabricating a chip package structure according to claim 1, wherein Providing the first carrier, the first carrier including the first surface and the patterned metal layer further comprising: providing a metal layer, the metal layer comprising a connection layer and a plurality of conductive traces a conductive trace is disposed on the connection layer; the metal layer is disposed on the first carrier, the conductive traces are attached to the first carrier; and the connection layer of the metal layer is patterned Forming a plurality of pads corresponding to the conductive traces, wherein the patterned metal layer includes the conductive traces and the pads. The method of fabricating a chip package structure according to claim 11, wherein the dielectric layer is at least filled between the conductive traces and the pads. The method of fabricating a chip package structure according to claim 12, wherein the dielectric layer on the first carrier and the dielectric layer are transferred to the second carrier, the dielectric layer Attach the second carrier. The method for fabricating a chip package structure according to claim 13 further includes: after removing the second carrier, respectively, a plurality of solder balls are disposed on the pads. A method for fabricating a chip package structure includes: providing a first carrier, the first carrier comprising a metal layer disposed on the first carrier; forming a dielectric layer on the metal layer; Transferring the metal layer and the dielectric layer on a carrier to a second carrier, wherein the dielectric layer is attached to the second carrier; removing the first carrier to expose the metal layer; The metal layer is subjected to a patterning process to form a patterned metal layer, the patterned metal layer includes a plurality of conductive traces; and a plurality of wafers are disposed on the patterned metal layer to electrically connect the wafers to the pattern a metal layer; forming an encapsulant on the second carrier, and the encapsulant covers the wafer, the patterned metal layer and the dielectric layer; removing the second carrier; and cutting the inter-wafer The encapsulant and the dielectric layer form a plurality of wafer package structures. The method for fabricating a chip package structure according to claim 15, further comprising: after removing the second carrier, forming a plurality of openings in the exposed dielectric layer, the openings exposing portions thereof The patterned metal layer is filled with the conductive material in the openings to form a plurality of pads, and the pads are electrically connected to the conductive traces respectively. The method for fabricating a chip package structure according to claim 16, further comprising: separately providing a plurality of solder balls on the pads.