TW200802764A - Chip package with array pads and method for manufacturing the same - Google Patents

Chip package with array pads and method for manufacturing the same

Info

Publication number
TW200802764A
TW200802764A TW95119569A TW95119569A TW200802764A TW 200802764 A TW200802764 A TW 200802764A TW 95119569 A TW95119569 A TW 95119569A TW 95119569 A TW95119569 A TW 95119569A TW 200802764 A TW200802764 A TW 200802764A
Authority
TW
Taiwan
Prior art keywords
chip package
wire
bonding
chip
connecting pads
Prior art date
Application number
TW95119569A
Other languages
Chinese (zh)
Other versions
TWI308383B (en
Inventor
Hung-Tsun Lin
Original Assignee
Chipmos Technologies Inc
Chipmos Technologies Bermuda
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipmos Technologies Inc, Chipmos Technologies Bermuda filed Critical Chipmos Technologies Inc
Priority to TW95119569A priority Critical patent/TWI308383B/en
Publication of TW200802764A publication Critical patent/TW200802764A/en
Application granted granted Critical
Publication of TWI308383B publication Critical patent/TWI308383B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

Disclosed is a chip package, for solving the rusting problem on sawed exposed surface of leads in leadframe-based leadless chip package and providing contact pads with array fashion. The chip package mainly includes a plurality of wire-connecting pads, a chip, a plurality of bonding wires, and an encapsulant. Each of the wire-connecting pads has an electrocasted core made of copper with an upper bonding layer thereon and a lower bonding layer beneath. The bonding wires elctrically connect the chip to the upper bonding layers of the wire-connecting pads. The encapsulant encapsulates the bonding wires, the electrocasted cores, and the upper bonding layers, only the lower bonding layers are exposed therefrom.
TW95119569A 2006-06-02 2006-06-02 Chip package with array pads and method for manufacturing the same TWI308383B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW95119569A TWI308383B (en) 2006-06-02 2006-06-02 Chip package with array pads and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW95119569A TWI308383B (en) 2006-06-02 2006-06-02 Chip package with array pads and method for manufacturing the same

Publications (2)

Publication Number Publication Date
TW200802764A true TW200802764A (en) 2008-01-01
TWI308383B TWI308383B (en) 2009-04-01

Family

ID=44765482

Family Applications (1)

Application Number Title Priority Date Filing Date
TW95119569A TWI308383B (en) 2006-06-02 2006-06-02 Chip package with array pads and method for manufacturing the same

Country Status (1)

Country Link
TW (1) TWI308383B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI550732B (en) * 2013-05-17 2016-09-21 南茂科技股份有限公司 Manufacturing method of chip package structure
TWI720796B (en) * 2020-01-21 2021-03-01 南茂科技股份有限公司 Semiconductor package structure and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI550732B (en) * 2013-05-17 2016-09-21 南茂科技股份有限公司 Manufacturing method of chip package structure
CN104167369B (en) * 2013-05-17 2017-03-01 南茂科技股份有限公司 Manufacturing method of chip packaging structure
TWI720796B (en) * 2020-01-21 2021-03-01 南茂科技股份有限公司 Semiconductor package structure and manufacturing method thereof

Also Published As

Publication number Publication date
TWI308383B (en) 2009-04-01

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees