1308383 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體晶片之封裝構造 關於-種無外接腳式晶片封裝構造及其製造方法。、 【先前技術】 在已知的封裝技術中，一種導線架基底晶片封裝構造得 為無外接腳式。其係導線架中引腳之下表面對外表 取代習知的導線架之外引腳，具有表面覆蓋區 小之優點。通常導線架之基礎層材料係包含有銅（cu)，以利 姓刻成形。雖'然具有導熱佳'導電性佳與低製造成本之優 勢’但銅本身容易在大氣與高溫環境中生鏽，終會影響晶片 封裝構造之產品可靠性。 如第1及2圖所示’ _種習知無外接腳式晶片封裝構造 ⑽係包含-具有腳⑴之導線架、一晶片12〇、複數個 銲線：30以及一封膠體140。習知的導線架之引腳i"之基 礎層係為銅，並在封奘箭__|§*、#447_^)_.*1 体耵衮剛一體連接至該導線架之框條（圖未 繪出)。該導線架可另具有一晶片承座112。該晶片120係黏 口於U承座11 2上。並以打線形成之該些銲線i 3 〇電性 連接該晶片120之複數個銲墊121至該些引腳ιη之上表面 113。而1¾封膠體140係密封該晶# 12〇與該些鲜線並 固著該些引腳111。該些引腳1H之下表面114可外露於該 封膠體140之外，並藉由該導線架之框條導通，以在該些下 表面114電鍍上一電鍍層115。當該封膠體】4〇與該電鍍層 115皆形成之後’方進行一單體化切割（singulation)的步驟。 1308383 如第1圖所示，該此引腳niA + u - 1會在該封膠體140之側面形成 露鋼之引腳外露表面丨丨6。兮此 、 °亥些外露表面116依現有製程無BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package structure of a semiconductor wafer, a substrate-less package structure and a method of fabricating the same. [Prior Art] In the known packaging technology, a lead frame base wafer package is constructed without an external pin type. The lower surface of the lead in the lead frame replaces the pin outside the conventional lead frame and has the advantage of a small surface coverage. Usually the base layer material of the lead frame contains copper (cu) for the formation of the surname. Although it has good thermal conductivity, good electrical conductivity and low manufacturing cost, copper itself is prone to rust in the atmosphere and high temperature environment, which will ultimately affect the reliability of the product in the package structure. As shown in Figs. 1 and 2, the conventional external chip package structure (10) includes a lead frame having a leg (1), a wafer 12, a plurality of bonding wires 30, and a gel 140. The base layer of the conventional lead frame i" is copper, and the frame ___|§*, #447_^)_.*1 is connected to the frame of the lead frame ( The figure is not shown). The leadframe can have a further wafer holder 112. The wafer 120 is bonded to the U-bearing 112. The plurality of bonding pads 121 formed by the bonding wires are electrically connected to the plurality of pads 121 of the wafer 120 to the upper surface 113 of the pins. The 13⁄4 sealant 140 seals the crystal and the fresh wires and fixes the pins 111. The lower surface 114 of the pins 1H may be exposed outside the encapsulant 140 and electrically connected by the frame of the lead frame to plate a plating layer 115 on the lower surfaces 114. When the encapsulant is formed and the plating layer 115 is formed, a singulation step is performed. 1308383 As shown in Figure 1, the pin niA + u - 1 forms an exposed surface 丨丨6 of the exposed steel pin on the side of the encapsulant 140.兮This, ° Hai exposed surface 116 according to the existing process
法被該電鍍層115所覆蓋俥嘴 .,^ B 復盖保遵’故容易由該些外露表面116 開始生鏽，影響了產品可责# ,, 等1座〇口了靠性。此外，該些引腳111之外露 表面11 6亦會造成高頻訊號 — j 丁傻形成天線效應。再者， 如第2圖所示，由於該些π 网11之每一外端皆須延伸至該 封膠體140之側邊’該些引 卿之排列方式只能單排或是多排 的交錯排列，無法進一步達古 7硬到回岔度之晶片封裝。 【發明内容】 本發明之主要目的係在於提 何供種具陣列接墊之晶片封 裝構造及其製造方法，利用電鐘 鑄也成之打線接墊，其電鎢核 心完全被封膠體所密封，並使装 、僅有打線接墊之下接合層是 顯露在一封膠體之外，具有防 電鑄核心生鏽的功效以提昇 產品可靠性’並能避免習知導線架之引腳之天線效應。此 外，打線接墊之陣列形成能達到高密度之晶片封裝。 本广月之次一目的係在於提供一種具陣列接塾之晶片封 及其製造方法，用以避免顯露在封膠體底面之下接合 層被刮傷或磨損，兼具有增進防鏽功效。 〇 本發明之再一目的係在於提供-種具陣列接墊之晶片封 裝構造之製造方法，在封裝製 ' 衮裝％中持續使用一剛性導電模板 進行電鑄、黏晶、打線與封裝的步驟，不需要中途更換載呈， 以達封裝作業的一貫性。 、科八 本發明的目的及解決其括 升筏術問題主要是採用以下 技術方案來實現的。一種晶 日片封裝構造係主要包含複數個 J308383 打線接墊、一晶片、複數個銲線以及一封膠體。該些打線接 墊係陣列形成在同一平面，每一打線接墊係包含有一下接合 • 層、一電鑄核心與一上接合層，其中該電鑄核心之材質係包 • 含銅。該晶片係具有複數個電極。該些銲線係電性連接該些 電極與該些打線接墊之上接合層。該封膠體係結合該晶片與 該些打線接墊為一體並密封該些銲線、該些電鑄核心與該些 上接合層，其中在該些打線接墊中僅有該些下接合層是顯露 參 在該封膠體之外。此外，本發明另揭示該晶片封裝構造之製 造方法。 前述的晶片封裝構造，其中另包含有—晶片承座，以 供固著該晶片。 刖述的晶片封裝構造，另包含有複數個承載接墊，以供 固著該晶片。 前述的晶片封裝構造’其中該些承載接墊與該些打線接 塾係為等尺寸並為棋盤排列。The method is covered by the plating layer 115. The ^B is covered and covered, so that it is easy to start rusting from the exposed surfaces 116, which affects the product responsibilities, and the like. In addition, the exposed surface 116 of the pins 111 also causes a high frequency signal to form an antenna effect. Furthermore, as shown in FIG. 2, since each of the outer ends of the π nets 11 must extend to the side of the sealant 140, the arrangement of the guides can only be staggered in a single row or in multiple rows. Arranged, it is impossible to further reach the ancient 7 hard-to-return chip package. SUMMARY OF THE INVENTION The main object of the present invention is to provide a chip package structure for manufacturing an array pad and a manufacturing method thereof, which are also formed by an electric bell casting, and the electric tungsten core is completely sealed by the sealing body. And the bonding layer under the mounting and only the wire bonding pad is exposed outside the gel, which has the function of preventing the rust of the electroforming core to improve the reliability of the product, and can avoid the antenna effect of the pin of the conventional lead frame. . In addition, the array of wire pads forms a high density wafer package. The second objective of the present invention is to provide a wafer package with an array of contacts and a method of manufacturing the same, in order to avoid scratching or abrasion of the bonding layer exposed under the bottom surface of the sealing body, and to enhance the rust preventing effect. A further object of the present invention is to provide a method for fabricating a chip package structure having an array pad, and continuously using a rigid conductive template for electroforming, die bonding, wire bonding, and packaging in a packaged armor % It is not necessary to replace the loading in the middle to achieve the consistency of the packaging operation. The purpose of the invention and the solution to its augmentation problem are mainly achieved by the following technical solutions. A crystal wafer package structure mainly comprises a plurality of J308383 wire bonding pads, a wafer, a plurality of bonding wires and a gel. The wire bonding arrays are formed on the same plane, and each wire bonding pad comprises a lower bonding layer, an electroforming core and an upper bonding layer, wherein the electroforming core is made of a material containing copper. The wafer has a plurality of electrodes. The bonding wires are electrically connected to the bonding layers of the electrodes and the bonding wires. The encapsulation system is integrated with the wire bonding pads and seals the bonding wires, the electroforming cores and the upper bonding layers, wherein only the lower bonding layers are in the wire bonding pads It is revealed that the reference is outside the sealant. Further, the present invention further discloses a method of fabricating the wafer package structure. The aforementioned wafer package construction further includes a wafer holder for holding the wafer. The wafer package construction described above further includes a plurality of carrier pads for mounting the wafer. In the foregoing chip package construction, the carrier pads and the wire bonding wires are of equal size and arranged in a checkerboard.
1述的日日#封I構造’其中該些下接合層之防鏽性係較 優於該些電鑄核心。 別述的晶片封裝構造，其中該些下接合層係選自於鎳_ 金層,、鎳-鈀-金層、锡層與錫鉛共晶層之其中之一。 刖述的晶片封裝播、主 4+ .1 構W，其中該些上接合層係選自於鎳_ 金層、鎳-鈀-金層與銀層之其中之一。 月1j述的晶片封裝方崔、皮. 其中該二下接合層係與該封膠體 之底面為共平面。 【實施方式1 J308383 如第3及4圖所示，在本發明之第一具體實施例中，一 種具陣列接墊之晶片封裝構造2〇〇主要包含複數個打線接墊 210、一晶片220、複數個銲線230以及一封膠體240。如第 4圖所示，該些打線接墊21〇係為陣列排列，可任意多排的 排列’其係由電鑄技術形成（容後詳述）。並且，如第3圖所 示，該些打線接墊210係形成在同一平面。每一打線接墊21〇 係包含有一下接合層211、一電鑄核心212與一上接合層 213，其中該電鑄核心212之材質係包含銅，其係一種導電 性佳、導熱性佳且易於電鍍之電屬。該些電鑄核心212之厚 度大於對應下接合層211之厚度及大於對應上接合層213之 厚度。在本實施例中，該晶片封裝構造2〇〇另包含有一晶片 承座250,以供固著該晶片220,該晶片承座25〇亦能以電 鑄方法开> 成，可同樣具有一電鏵核心212與上下接合層 213、211，一接地銲線可接合在該晶片承座25〇上。在不同 實施例中，當該晶片承座2 5 0不需要打線銲接時，則該晶片 承座250可不需要該上接合層213。 該晶片220係具有一主動面221、一背面222與複數個電 極223,該些電極223係可形成於該晶片22〇之該主動面221 上，該些電極223除了可以如第3圖所示為銲墊形狀，但亦 可為凸塊形狀。該晶片220之該背面222係可利用膠膜類、 B階膠體 '液體膠專黏晶材料黏著於該晶片承座2 $ 〇。 打線形成之該些銲線230係電性連接該晶片22〇之該些 電極223與該些打線接墊210之上接合層213,通常該些銲 線230係可為金線。該封膠體240係結合該晶片22〇與該些 .1308383In the above description, the rust resistance of the lower bonding layers is superior to the electroforming cores. A wafer package structure, wherein the lower bonding layer is selected from the group consisting of a nickel-gold layer, a nickel-palladium-gold layer, a tin layer, and a tin-lead eutectic layer. The wafer package is described, and the main bonding layer is selected from one of a nickel-gold layer, a nickel-palladium-gold layer and a silver layer. The wafer package of the month 1j is Cui, Pi. The two lower bonding layers are coplanar with the bottom surface of the encapsulant. [Embodiment 1] J308383 As shown in FIGS. 3 and 4, in a first embodiment of the present invention, a chip package structure 2 of an array pad mainly includes a plurality of wire bonding pads 210 and a wafer 220. A plurality of bonding wires 230 and a colloid 240 are provided. As shown in Fig. 4, the wire bonding pads 21 are arranged in an array, and can be arranged in any number of rows, which are formed by electroforming technology (described later in detail). Further, as shown in Fig. 3, the wire bonding pads 210 are formed on the same plane. Each of the wire bonding pads 21 includes a lower bonding layer 211, an electroforming core 212, and an upper bonding layer 213. The material of the electroforming core 212 is copper, which is excellent in electrical conductivity and thermal conductivity. Easy to electroplating electricity. The thickness of the electroformed cores 212 is greater than the thickness of the corresponding lower bonding layer 211 and greater than the thickness of the corresponding upper bonding layer 213. In this embodiment, the chip package structure 2 further includes a wafer holder 250 for fixing the wafer 220. The wafer holder 25 can also be opened by electroforming, and can have the same The core 212 and the upper and lower bonding layers 213, 211, a ground bonding wire can be bonded to the wafer holder 25A. In various embodiments, the wafer carrier 250 may not require the upper bonding layer 213 when the wafer carrier 250 does not require wire bonding. The wafer 220 has an active surface 221, a back surface 222 and a plurality of electrodes 223. The electrodes 223 are formed on the active surface 221 of the wafer 22, and the electrodes 223 can be as shown in FIG. It is a pad shape, but it can also be a bump shape. The back surface 222 of the wafer 220 can be adhered to the wafer holder 2 $ by a film, a B-stage colloidal liquid adhesive material. The bonding wires 230 formed by the bonding are electrically connected to the electrodes 223 of the wafer 22 and the bonding layer 213 of the bonding pads 210. Generally, the bonding wires 230 may be gold wires. The encapsulant 240 is bonded to the wafer 22 and the .1308383
打線接墊210為一體並密封該些銲線23〇、該些電禱核心2i2 與該些上接合層2丨3。可利用壓模、印刷或點膠方式提供該 封膠體240，通常該封膠體240係為絕緣材料，包含無機填 充劑、固化劑與色料等等。其中，如第3圖所示，在該些打 線接墊210中僅有該些下接合層211是顯露在該封膠體24〇 之外，該些電鑄核心212不會有外露於該封膠體24〇之部 份，以避免氧化生鏽。較佳地，該些下接合層21丨之外露表 面係與該封膠體240之底面241為共平面，以避免在產品搬 運與使用過程該些下接合層2n被刮傷或磨損。並且具有該 些下接合層211内嵌於該封膠體24〇之型態，更可以避免該 些下接合層211與該些電鑄核心212之界面外露於大氣中， 以增進防鏽功效。在本實施例中，該些下接合層211之防鏽 性應較優於該些電鑄核心212。例如相對於銅質之電鑄核心 212,該些下接合層211之材質係可選自於鎳_金層、鎳-鈀_ 金層、制與錫錯共晶層之其中之―，《其它可供表面接合 之抗氧化金屬。而該些上接合層213之材質係可選自於鎳_ 金層、鎳-鈀-金層與銀層之其中之一，或其它可供銲接之金 屬。 因此，上述之晶片封裝構造2〇〇具有以下的功效：一、 具有防止電鑄核心2 12由側面產生生鏽的功效以提昇產品可 靠性；二、能避免習知導線架之引腳之天線效應；三、該些 打線接墊21〇之陣列排列能符合高密度之晶片封裂。 關於該晶片封裝構造2〇〇之製造方法，配合第5、6Α〜6〇 圖說明如後。首先’如第5圖與6A圖所示’提供_剛性導 •1308383 電模板260 ’其係具有一平坦表面，用以定義上述形成該些 打線接墊210之共平面。再形成一電鑄遮罩27〇於該導電模 .板上，該電鎊遮罩27G係可由液態光阻與感光性乾膜所 .構成。如第6B圖所示’利用曝光顯影的技術使得該電禱遮 罩270圖案化’而具有開孔圖案271。如第6c圖所示，依該 電鑄遮罩270之開孔圖案π，並在該導電模板26〇之導通 下，能以電鑄技術依序形成一下接合層211、一電鑄核心2 Η _ 與一上接合層213在該開孔圖案27i内，以構成複數個之該 些打線接墊210於該導電模板26〇上，如此便能使該些打線 接墊210陣列形成在同一平面。在本實施例中，並可同時形 成該晶片承座250。如第6D圖所示，在移除該電鑄遮罩27〇 之後，设置至少一之上述晶片22〇於該導電模板2⑼之上 方，在本實施例中，該晶片220係黏固於該晶片承座25〇。 如第6E圖所示，在不需要移除該導電模板26〇之條件下， 接著，打線形成複數個銲線230,其係電性連接該些電極223 • 與該些打線接墊210之上接合層213。如第6F圖所示，之 後，以半導體封裝技術形成一封膠體24〇於該導電模板26〇 上，该封膠體240係結合該晶片220與該些打線接墊2丨〇為 一體並密封該些銲線230、該些電鑄核心212與該些上接合 層213，其中該些下接合層211仍是貼合於該導電模板26^。 最後在該封膠體240形成之後，剝離該導電模板，可使 在該些打線接整2H)中僅有該些下接合層211是顯露在該封 膠體240之外，而製得如第3圖所示之晶片封襄構造2〇〇。 因此，在前述之製造方法中，該導電模板26〇持續被使用在 1308383 不需要中途更換載具， 電鑄、黏晶、打線與封裝的步驟過程 以達封裝作業的一貫性。The wire bonding pads 210 are integrated and seal the bonding wires 23〇, the electrical prayer cores 2i2 and the upper bonding layers 2丨3. The encapsulant 240 can be provided by stamping, printing or dispensing. Typically, the encapsulant 240 is an insulating material comprising an inorganic filler, a curing agent and a colorant, and the like. As shown in FIG. 3 , only the lower bonding layers 211 are exposed outside the sealing body 24 , and the electroforming cores 212 are not exposed to the sealing body. 24 parts to avoid oxidative rust. Preferably, the exposed surfaces of the lower bonding layer 21 are coplanar with the bottom surface 241 of the encapsulant 240 to prevent the lower bonding layer 2n from being scratched or worn during product handling and use. Moreover, the lower bonding layer 211 is embedded in the sealing body 24, and the interface between the lower bonding layer 211 and the electroforming core 212 is prevented from being exposed to the atmosphere to enhance the rust preventing effect. In this embodiment, the lower bonding layer 211 should have better rust resistance than the electroforming cores 212. For example, with respect to the electroformed core 212 of copper, the material of the lower bonding layer 211 may be selected from the group consisting of a nickel-gold layer, a nickel-palladium-gold layer, and a tin-malignant eutectic layer. An anti-oxidation metal that can be surface bonded. The materials of the upper bonding layer 213 may be selected from one of a nickel-gold layer, a nickel-palladium-gold layer and a silver layer, or other metal for soldering. Therefore, the above-mentioned chip package structure 2 has the following effects: 1. It has the effect of preventing the rust of the electroforming core 2 12 from being flanked by the side to improve the reliability of the product; 2. The antenna for avoiding the pin of the conventional lead frame Effect; Third, the array of wire bonding pads 21〇 can conform to high-density wafer sealing. The manufacturing method of the chip package structure 2 is described later in conjunction with the fifth, sixth, and sixth drawings. First, 'providing a rigid guide as shown in Figs. 5 and 6A', 1308383, an electrical template 260' has a flat surface for defining the above-described coplanar formation of the wire bonding pads 210. Further forming an electroformed mask 27 on the conductive mold plate, the electric pound mask 27G can be composed of a liquid photoresist and a photosensitive dry film. The electroporation mask 270 is patterned by the technique of exposure development as shown in Fig. 6B to have an aperture pattern 271. As shown in FIG. 6c, according to the opening pattern π of the electroformed mask 270, and under the conduction of the conductive template 26, the lower bonding layer 211 and the electroforming core 2 can be sequentially formed by electroforming. _ and an upper bonding layer 213 are formed in the opening pattern 27i to form a plurality of the bonding pads 210 on the conductive template 26, so that the arrays of the bonding pads 210 are formed on the same plane. In the present embodiment, the wafer holder 250 can be formed at the same time. As shown in FIG. 6D, after removing the electroformed mask 27, at least one of the wafers 22 is disposed above the conductive template 2 (9). In the embodiment, the wafer 220 is adhered to the wafer. The seat is 25 inches. As shown in FIG. 6E, under the condition that the conductive template 26 is not required to be removed, the wire is then formed into a plurality of bonding wires 230 electrically connected to the electrodes 223. Bonding layer 213. As shown in FIG. 6F, a semiconductor package is formed on the conductive template 26A by a semiconductor encapsulation technique, and the encapsulant 240 is bonded to the bonding pads 2 and sealed. The bonding wires 230 , the electroforming cores 212 and the upper bonding layers 213 , wherein the lower bonding layers 211 are still attached to the conductive template 26 . Finally, after the encapsulant 240 is formed, the conductive template is peeled off, so that only the lower bonding layer 211 is exposed outside the encapsulant 240 in the wire bonding 2H), and is prepared as shown in FIG. The illustrated wafer package structure is 2". Therefore, in the foregoing manufacturing method, the conductive template 26 is continuously used in 1308383, and there is no need to replace the carrier, electroforming, die bonding, wire bonding, and packaging steps to achieve the consistency of the packaging operation.
如第7及8圖所示’在本發明之第二具體實施例中，揭 示另一種具陣列接墊之晶片封裝構造300,纟要包含與第一 具你實施例大致相同之複數個打線接墊31〇、一晶片32〇、 複數個銲線330以及一封膠體34〇 ’並可另包含複數個承載 接墊35G，以供固著該晶片32卜該些打線接墊31()與該些 承載接墊350係由電鑄技術形成，為陣列排列。較佳地，該 些承載接墊3 5 0與該些打線接墊3丨〇係為等尺寸並為棋盤排 列，不需要額外規劃與界定晶片承座的位置與尺寸，達到共 用公板並兼具有分散承載晶片應力之功效。並且，如第7圖 所示，該些打線接墊310係形成在同一平面。其中，每一打 線接墊310或/及承載接墊35〇係包含有一下接合層3ιι、一 電鑄核心312與一上接合層313。 該晶片320係具有複數個電極321。打線形成之該些銲線 330係電性連接該晶片32〇之該些電極321與該些打線接墊 310之上接合層313。該封膠體34〇係結合該晶片32〇、該些 打線接墊310與該些承載接墊35〇為一體並密封該些銲線 330、該些電鑄核心312與該些上接合層313。其中，如第7 圖所示，在該些打線接墊310與該些承載接墊350中僅有該 些下接合層3 11是顯露在該封膠體34〇之外，該些電鑄核心 312不會有外露於該封膠體34〇之部份，以避免氧化生鏽。 本發明可進一步應用至非打線類型之不同晶片封裝構 造。如第9圖所示，在第三具體實施例中，一種具陣列接墊 1308383As shown in FIGS. 7 and 8 , in a second embodiment of the present invention, another chip package structure 300 having an array pad is disclosed, which includes substantially the same number of wires as the first embodiment. Pad 31〇, a wafer 32〇, a plurality of bonding wires 330, and a glue body 34′′ may further include a plurality of carrier pads 35G for fixing the wafer 32 to the wire bonding pads 31() and the The carrier pads 350 are formed by electroforming techniques and are arranged in an array. Preferably, the bearing pads 350 and the wire bonding pads 3 are equal in size and arranged in a checkerboard, and no additional planning and definition of the position and size of the wafer holder are required, so as to achieve the common public board and It has the effect of dispersing the load of the wafer. Further, as shown in Fig. 7, the wire bonding pads 310 are formed on the same plane. Each of the wire pads 310 or/and the carrier pads 35 includes a lower bonding layer 3, an electroforming core 312 and an upper bonding layer 313. The wafer 320 has a plurality of electrodes 321 . The bonding wires 330 formed by the bonding are electrically connected to the electrodes 321 of the wafer 32 and the bonding layer 313 of the bonding pads 310. The sealing body 34 is bonded to the wafer 32, and the bonding pads 310 are integrated with the bearing pads 35 and seal the bonding wires 330, the electroforming cores 312 and the upper bonding layers 313. As shown in FIG. 7 , only the lower bonding layers 3 11 of the bonding pads 310 and the carrier pads 350 are exposed outside the sealing body 34 , and the electroforming cores 312 . There will be no exposed parts of the sealant 34 to avoid oxidative rust. The invention can be further applied to different wafer package configurations of the non-wire type. As shown in FIG. 9, in the third embodiment, an array of pads 1308383
層413所覆蓋。該晶片420係具有複數個電極422，通常在 該些電極422係電性 該些電極422係為凸 形成在該晶片420之同一表面421上。 連接至該些接墊4 1 0。在本實施例中， 塊，該晶片420係以覆晶接合方式設置於該些接墊4ι〇上 ，例如該些接塾 420之電極422 較佳地’該些接墊410之排列方式為共用型 41 0係為等尺寸並為棋盤排列。而依該晶片 數量不同變化，使得該些接墊41〇之數量能大於該些電極 422，而使部分之該些接墊41〇為無電性傳遞的虛置墊 • 41〇A(dummy pad)(如第9圖所示）。該封膠體430係結合該 晶片420與該些接墊410為一體並密封該些電鑄核心412之 側面412A，其中在該些接墊41〇中僅有該些下接合層411 是顯露在該封膠體430之外，以避免該些電鑄核心412之鏽 化。較佳地，該些下接合層411係與該封膠體43〇之底面431 為共平面，以使該些下接合層411内嵌於該封膠體43〇，使 該些下接合層411免於被刮傷或磨損，更可以避免該些下接 合層411與該些電鑄核心412之界面外露於大氣中，以增進 12 上3〇8383 明：上所述’僅是本發明的較佳實施例而已，並非對本發 上任何形式上的限制’雖然本發明已以較佳實施例揭露如 脫離*而並非用以限疋本發明，任何熟悉本項技術者，在不 本發明之申請專利範圍内 性 間所作的任何簡皁修改、等效 變化與修飾’皆涵蓋於本發明的技術範圍内。 L圖式簡單說明】 圖1知無接腳式晶片封裝構造之截面示意圖。 圖.習知晶片封裝構造之頂面透視圖。 依據本發明之第—具體實施例，一種具陣列接塾之 晶片封裝構造之截面示意圖。 依據本發明之第—呈科举# , i 弟/、體實施例，繪示該晶片封裝構 造之晶片與打線接墊之頂面示意圖。 依據本發明之第—具體實施例’在該晶片封裝構造 第6A $之製程中所提供之導電模板之頂面示意圖。 弟6A至6G圖：依據本發 裝槿帛具體實施例，該晶片封 凌構w於製程中之截面示意圖。 依據本發明之第_ 弟一具體實施例，另一種具陣列接墊 片封裝構造之截面示意圖。 依據本發明之 佐_ 第一八體實施例’該晶片封裝構造之 坻面示意圖。 依據本發明之第=1俨宭故h $曰μ 弟一/、體實施例，另一種具陣列接墊 r 日日封裝構造之戴面示意圖。 L主要元件符號說明】 1〇〇晶片封裝構造 第 第 圖 圖 第7圖 第8圖 13 1308383Covered by layer 413. The wafer 420 has a plurality of electrodes 422. Typically, the electrodes 422 are electrically conductive. The electrodes 422 are convexly formed on the same surface 421 of the wafer 420. Connected to the pads 4 1 0. In this embodiment, the 420 is placed on the pads 4 iv in a flip-chip bonding manner. For example, the electrodes 422 of the interfaces 420 are preferably arranged in a shared manner. Type 41 0 is of equal size and is arranged on a checkerboard. Depending on the number of the wafers, the number of the pads 41 能 can be larger than the electrodes 422, and some of the pads 41 〇 are dummy pads for non-electrical transmission. 41 〇 A (dummy pad) (as shown in Figure 9). The sealing body 430 is integrated with the pads 410 and seals the side surfaces 412A of the electroforming cores 412. Among the pads 41A, only the lower bonding layers 411 are exposed. Outside the encapsulant 430, rusting of the electroformed cores 412 is avoided. Preferably, the lower bonding layer 411 is coplanar with the bottom surface 431 of the encapsulant 43 such that the lower bonding layer 411 is embedded in the encapsulant 43 〇 to protect the lower bonding layer 411 from the lower bonding layer 411. If it is scratched or worn, the interface between the lower bonding layer 411 and the electroforming cores 412 can be prevented from being exposed to the atmosphere to enhance the above-mentioned 3's. The present invention is not limited to any form of the present invention. Although the present invention has been disclosed in the preferred embodiments as being without the limitation of the present invention, it is not intended to limit the invention. Any simple soap modification, equivalent change and modification made by the internals are encompassed within the technical scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view showing a pinless chip package structure. Figure. A top perspective view of a conventional wafer package construction. In accordance with a first embodiment of the present invention, a cross-sectional view of a chip package structure having an array of contacts is shown. According to the first embodiment of the present invention, the invention shows a top view of the wafer and the bonding pad of the chip package structure. A top plan view of a conductive template provided in the process of the chip package construction No. 6A$ according to the first embodiment of the present invention. Figure 6A to 6G: A schematic cross-sectional view of the wafer package structure in accordance with a specific embodiment of the present invention. Another cross-sectional view of an array pad package construction in accordance with a first embodiment of the present invention. A schematic view of the wafer package structure in accordance with the present invention. According to the present invention, the first embodiment of the present invention is another schematic diagram of the wearing surface of the array package r. L main component symbol description] 1〇〇 chip package structure Fig. 7 Fig. 8 Fig. 13 1313838
111 引腳 112 晶片承座 113 上表面 114 下表面 116 引腳外露表面 120 晶片 121 銲墊 130 銲線 140 封膠體 200 晶片封裝構造 210 打線接墊 211 下接合層 213 上接合層 220 晶片 221 主動面 223 電極 230 銲線 241 底面 250 晶片承座 270 電鑄遮罩 271 開孔圖案 300 晶片封裝構造 3 10 打線接墊 311 下接合層 313 上接合層 320 晶片 330 銲線 340 封膠體 400 晶片封裝構造 410 接墊 410A虛置墊 411 下接合層 412 電鑄核心 413 上接合層 420 晶片 421 表面 430 封膠體 431 底面 115電鍍層 212電鑄核心 222背面 240封膠體 2 6 0導電板板 312電鑄核心 321電極 350承載接墊 412A側面 422電極 14111 pin 112 wafer holder 113 upper surface 114 lower surface 116 pin exposed surface 120 wafer 121 pad 130 bonding wire 140 encapsulant 200 chip package structure 210 wire bond pad 211 lower bonding layer 213 upper bonding layer 220 wafer 221 active surface 223 electrode 230 bonding wire 241 bottom surface 250 wafer holder 270 electroforming mask 271 opening pattern 300 chip package structure 3 10 wire bonding pad 311 lower bonding layer 313 upper bonding layer 320 wafer 330 bonding wire 340 sealing body 400 wafer package structure 410 Pad 410A dummy pad 411 lower bonding layer 412 electroforming core 413 upper bonding layer 420 wafer 421 surface 430 sealing body 431 bottom surface 115 plating layer 212 electroforming core 222 back 240 sealing body 2 6 0 conductive plate 312 electroforming core 321 Electrode 350 carrying pad 412A side 422 electrode 14