TW201143018A - A three dimensional chip stacking electronic package with bonding wires - Google Patents

Abstract

This invention provides the three dimensional chip stacking electronic package, where stacking chip has via structure with conductive material to achieve electrical connection. The package applies electric pads to stack each stacking chips, and utilized wire bonding technology to achieve electrical connection between stacking chip and substrate, where the bonding structure is protected by molding compound. The package can be electrically connected with another substrate to achieve board-level package.

Description

201143018 VI. Description of the Invention: [Technical Field] The three-dimensional wafer stack structure and the substrate are connected [0001] The present invention relates to an electronic package structure, in particular to a stacked package structure The purpose of the connection. In recent years, with the semiconductor industry and technology booming, unfinished business"

The ultra-high-telecom contacts of electronic components are in turn, and the demand for products is thin and thin. The electronic package structure consists of the original single-day t-chip 'two-dimensional planar multi-chip to the current three-dimensional stacking heart = exhibition 'Advanced packaging structures are gradually developed such as Wafer Level Package (WLP), Multi-Chip Package Module (MCM) and System-in-Package (System 1P sip). Among them, sip is a general term for extensively integrated ages, including two micro-planar wafers to two-dimensional stacked packages. The three-dimensional stacking package is more advanced in recent years. (4) The main trend of development 'Many package structures have been extensively developed' including the inclusion of through silicon vias (Through Silicon Via' TSV)

Bonding) stacking and introduction of interposer structure and other techniques to reduce the size and weight of the stacked package in the direction of the thicker household, thus meeting the needs of the new package structure for thin: small. [Prior Art] U.S. Patent No. 7,615,413 discloses the use of wire bonding to connect the electronic contacts of the stacked chips to the substrate for the purpose of telecommunications bonding, as shown in Figure 1; Board 2; external telecommunication contact 3; electrode 4; first bonding layer 6; first bonding wire 7; second bonding layer 9 Form No. A0101 Page 3 of 23 201143018 'Second bonding wire 10; sealant 11; stacked form semiconductor component 50 'semiconductor unit 51; package structure 52; circuit board 53; first semiconductor unit 54; second semiconductor unit 55; sealant 56; layer 57; then layer 58; passive component 59; 6〇. The wire bonding technique utilized in this patent 'can be applied to a different type of wafer package than a single type of wafer stack package' or even an electronic package in which the package structure and the wafer are stacked. The Republic of China Patent No. J269460 proposes a three-dimensional stacked package unit having a conductive support bottom plate, as shown in FIG. 2; comprising: a substrate 101, a telecommunication contact 102; a fixed structure 103 having a telecommunication transmission; and a first package unit Body 110; second package unit body 120. This structure can achieve multi-wafer stacking by means of telecommunication contacts on both sides of the package unit. Moreover, the package unit can apply the advantages of the batch process, greatly reduce the production cost of the single package unit and provide the telecommunication transmission by using the support substrate with conductive characteristics, or can be used as the ground terminal to improve the electrical characteristics of the package structure. Moreover, the bottom plate is also a good conductor of heat, which can effectively improve the heat dissipation effect of the package structure and improve the service life of the package structure. SUMMARY OF THE INVENTION [0003] The object of the present invention is to provide a process-oriented and reliable three-dimensional wafer stack electronic package structure, in addition to the use of advanced 矽 via hole process to achieve the purpose of wafer stacking, while applying mature technology The technology combines the stacked wafers with the substrate to meet the needs of a wide range of electronic packaging applications. In order to achieve the foregoing objective, the present invention provides a three-dimensional wafer-stack electronic package structure comprising a singular or a plurality of stacked wafers having a singular or plural number of through-hole via structures, and an insulating layer coated with an insulating property. No. A0101 Page 4 of 23 201143018 The surface of the sheet and the via hole is filled with a conductive material to form a singular or plural conductive via structure with a conductive structure. The telecommunications contact layer structure is used to connect the telecommunication contacts between different stacked wafers, and is connected to a single or a plurality of telecommunication contacts on the bottom wafer, and the bottom wafer is bonded to the substrate by the bonding layer. The singular or plurality of telecommunication contacts of the stacked chip are electrically connected to a single or a plurality of telecommunication contacts on the substrate by a single or a plurality of wire bonding wires. The gelatin resin material is used to coat a single or multiple wire conductors, a singular or a plurality of stacked wafers, and an underlying wafer to complete the three-dimensional wafer stack electronic package structure of the present invention. [Embodiment] The present invention discloses an electronic package structure which is a three-dimensional wafer stack form electronic package structure. In detail, the present invention proposes a conductive via structure filled with a conductive material to carry out a telecommunication connection of the stacked wafers, and is further matched with a wire bonding structure and a wire bonding technique, and can be further connected with other basic electronic package structures. . The embodiments of the present invention are described in detail below, but the embodiments are merely illustrative and are not intended to limit the invention. 3 is a cross-sectional view of a three-dimensional wafer stack package structure 300 of the present invention. The package structure 300 mainly includes a single or a plurality of stacked wafers 302 stacked on a single bottom wafer 301, wherein the lower surface of the bottom wafer 301 is utilized. The layer 310 is then bonded to the upper surface of the substrate 350. The adhesive layer 310 can be any adhesive material having an adhesive effect, and the substrate 350 can be an organic substrate such as BT, FR4, ABF, or a material such as germanium. The stacked wafer 302 has a single or a plurality of vias 303 for making vias for telecommunications connections. The via hole is covered by the insulating layer 311, and the insulating layer 311 is in the form of A0101, page 5/23, 201143018, and partially or completely covers the stacked crystal 2 to achieve the effect of protecting the wafer telecommunications; Reaching telecommunications insulation materials such as BCB (benz〇cycl〇butene),

ABF (Ajin〇m〇t〇Built-uP Film), PI (P〇lyimid, etc.) or cerium oxide. The through hole 2 is covered with insulating material 311 to make another through hole 312 for filling The hole-filling conductive material (10) can pass through the stacking crystal 2 for the purpose of transmission. Further, the wafer 3G2 is completely or partially covered with an insulating layer 311, and the surface of the insulating layer is formed with a plurality of or a plurality of telecommunication contacts. 32. The first telecommunications contact 32 is completely covered, partially or uncovered on the surface of the insulating layer 310, and completely or partially covered with the filling conductive material 320; the first telecommunication contact 321 can be directly formed in the filling hole The conductive material 320 is formed on the surface of the insulating layer 310 after being rewired; and the singular or plural second telecommunication contacts 322 are formed on the other surface. The second telecommunication contact 322 is completely, partially or not. Covering the surface of the insulating layer 310, and completely or partially covering the hole-filling conductive material 32. On the bottom board, a single or a plurality of third telecommunications contacts 323 are formed.

The third telecommunications contact 323 for insulation purposes is partially or completely coated on the upper surface of the underlying wafer 3〇1. The stacked wafer 302 having the insulating layer 311, the vias 303 and 312, the via-hole conductive material 320, the first telecommunications contact 321, and the second telecommunications contact 322 is structured by a telecommunication contact layer 325, and the second telecommunications contact The 322 is electrically connected to the third telecommunications contact 323 formed on the bottom wafer 301. The telecommunications contact layer 325 can be any conductive material such as tin, tin-silver alloy, tin-lead alloy, electroplated copper or the like. The first telecommunication contact 321 of the stacked chip 302 is connected to the fourth telecommunication contact 324 by using a singular or a plurality of wire bonding wires 330 to achieve a telecommunication connection with the substrate 350. The substrate 350 is completely or partially fabricated. Wrapped singular or form number A0101 Page 6 / Total 23 pages 2 〇 1143 〇 18 A plurality of fourth telecommunication contacts 324. The wire conductor 330 is fully or partially covered with or without the use of the sealing resin 340 to protect the reliability of the wire bonding 330. [6] In the aforementioned three-dimensional wafer stack package structure 300, the stacked wafer 302 or the underlying wafer 301 may be a combination of active electronic components, sensing components, test components, MEMS wafers or electronic components thereon. The conductive material filled by the hole-filling conductive material 320 may be a conductive metal such as tin, aluminum, copper, silver, tungsten, lead or a metal material of the above or other conductive material φ. The conductive material is also applicable to any conductive-related structure such as the first telecommunications contact 321, the second telecommunications contact 322, the third telecommunications contact 323, the fourth telecommunications contact 324, and the telecommunication contact layer 325. [0007] One possible manufacturing method of the three-dimensional wafer stack package structure 300 can be divided into main steps: one: fabricating a stacked wafer 302 having through holes 303 or vias 312; second: bonding without vias 303 or none The underlying wafer 301 of the via 312 structure is on the surface of the substrate 350; third: the singular or plural stacked wafers 302 are bonded by the telecommunication contact layer 325 by a hot stamping process; and the fourth: using the wire bonding technique to wire the wire 330 The first telecommunication contact 321 of the stack structure is connected to the fourth telecommunication contact 324 on the surface of the substrate 350, and is only protected by the sealant tree. [0008] One possible fabrication method of the stacked wafer 302 having the via 303 or the via 312 is to use a photolithography or laser process to form a singular or plural number of stacked wafers 302 for performing electronic component functions. The hole 3〇3; the continuous pressure or the money process (4) edge layer 311 is formed on the stacked wafer side - or both sides, the insulating layer 311 can completely or partially cover the stacked wafer surface, the form number A0101 and the layer will Completely or partially fill the through hole 3〇3; use the light on page 7/total 23 5 201143018 lithography button or laser process, in the through hole 303 which is completely or partially filled by the insulating layer 3ΐ Filling the hole-filled conductive material with the hole-through hole 312 structure, filling the hole-filled conductive material 32〇, such as electro-recording steel or electric ray process; connecting _ electricity (four) _ process, with photolithography etching process A singular or plural number of telecommunication contacts 321 and a second telecommunication contact 322 are formed on the surface of the stacked wafer 302. A possible method for manufacturing the surface of the underlying wafer 3〇1 and the substrate 350 is as follows: #Using an electric or reduced clock process, with light lithography The engraving process is performed on the surface of the bottom wafer 301 to form a single or a plurality of third telecommunication contacts 323; and subsequently, the bonding layer 31 is formed on the surface of the underlying wafer 3〇1 or the germanium substrate 350 by spin coating or hot pressing. A plurality of or a plurality of fourth telecommunication contacts 324 are formed on the surface of the substrate 35 by the associated telecommunications contact process; and the underlying wafer 301 is bonded to the substrate 35 () by a hot pressing or arranging process. [0010] One possible manufacturing method for bonding the singular or plural stacked wafers 302 using the telecommunication contact layer 325 is to form the telecommunication contact layer 325 on the surface of the stacked wafer 302 by electroplating or sputtering. The second telecommunications contact 322, or the third telecommunications contact 323 on the surface of the bottom wafer 301, continues to bond the stacked wafer 302 and the bottom wafer 301 through the telecommunication contact layer 325 by a hot press or reflow process. [0011] One possible manufacturing method of connecting the first telecommunication contact 321 of the stacked structure to the fourth telecommunication contact 321 of the surface of the substrate 350 is to make the wire bonding wire 330 on the stacked chip 302 by using a wire bonding technique. The first telecommunication contact 321 on the surface is connected to the fourth telecommunication contact 324 on the surface of the substrate 350. The wire material can be gold, silver, form number A0101, page 8 / 23 pages 201143018 Aluminum, copper and other materials with conductive properties. The encapsulating resin 340 is completely or partially covered with the wire bonding wire 330, the stacked stacked wafer 302 and the underlying wafer 301 structure, and the substrate 350 are successively formed by a molding process. 4 is a structural cross-sectional view of a three-dimensional stacked package structure 400 applied to a ball array package form. The package structure is provided with a three-dimensional stacked package structure, and the first substrate 450 is provided with a single or a plurality of fourth telecommunication contacts 424 connected to the surface of the first substrate 450, and a singular or plural ball array structure. 470 telecommunications connection. The ball array structure 470 is a telecommunications connection for the three-dimensional three-dimensional stacked package structure 400 and the second substrate 460. This ball array package is described for the embodiment of the board level package and is not intended to limit the invention. [0013] FIG. 5 is a second embodiment of the present invention, which is a three-dimensional wafer stack package structure 500 fabricated using a plurality of stacked wafers. An underlying wafer 501 followed by a substrate 550, a first stacked wafer 502 stacked on the underlying wafer 501, a second stacked wafer 503 stacked on the second stacked wafer 502, and a third stacked wafer 504 stacked on the second stacked wafer 503 are included. . Successively, the telecommunication contacts of the third stacked wafer 504 are electrically connected to the substrate 550 by wire bonding wires 530, and then the structure is covered or partially covered with the sealing resin 540. The foregoing embodiment structure is described with respect to only three stacked wafers, and the number of stacked wafers and other structures are not intended to limit the present invention. 6 is a third embodiment of the present invention, which is a structural cross-sectional view of a three-dimensional stacked package structure fabricated by using a plurality of stacked wafers in combination with a ball array package. The package structure is provided with a three-dimensional stacked package structure 600, and the telecommunication connection between the first substrate 650 and the second substrate 660 is achieved through the singular or plural ball array structure 670. The foregoing implementation form number A0101 Page 9 of 23 201143018 The example structure is described with respect to only three stacked wafers, and the number of stacked wafers and other structures are not intended to limit the present invention. 7 is a fourth embodiment of the present invention, which is a structural cross-sectional view of a three-dimensional stacked package structure fabricated by using a plurality of stacked wafers of different sizes, in combination with a ball array package. The package structure has a three-dimensional stacked package structure 700, the size of the bottom wafer 701 can be greater than, equal to, or smaller than the size of the stacked wafer 702, or the size of the stacked wafer 702 can be greater than, equal to, or smaller than the size of the stacked wafer 703. The foregoing embodiment structure is merely illustrative of the stacked wafer and underlying wafer dimensions and is not intended to limit the invention. [0016] FIG. 8 is a fifth embodiment of the present invention, which is a three-dimensional stacked package structure including a communication contact after rewiring. The package structure has a three-dimensional stacked package structure 800, wherein the first telecommunications contact 821 connected to the wire bonding structure 830 is electrically connected to the hole-filled conductive material 820 via the rewiring structure 822. The foregoing embodiment structure is merely illustrative of the rewiring structure and is not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS [0017] The embodiments of the present invention are supplemented by the following figures in the above description for the purpose of detailed explanation: FIG. 1 is a three-dimensional stacked electronic package structure using a wire bonding technique. [0018] FIG. 2 is a perspective view of a three-dimensional stacked electronic package structure utilizing a conductive support substrate. [0019] FIG. 3 is a cross-sectional view showing a three-dimensional stacked package structure according to a first embodiment of the present invention. Form No. A0101 Page 10 of 23 201143018 [0020] FIG. 4 is a cross-sectional view showing the structure of a first embodiment of the present invention applied to a ball array package. [0021] FIG. 5 is a cross-sectional view showing an electronic package structure of a plurality of stacked wafers using the stacked wafer structure of the present invention in accordance with a second embodiment of the present invention. 6 is a cross-sectional view of an electronic package structure in which a plurality of stacked wafers are applied by the stacked wafer structure of the present invention and applied to a ball array package form, in accordance with a third embodiment of the present invention. [0023] FIG. 7 is a fourth embodiment of the present invention, in which a plurality of stacked wafers of different sizes are used for the stacked wafers of the present invention, and the underlying wafers are also different in size, and are applied to electronic packages of ball array packages. Structural section view. 8 is a cross-sectional view of an electronic package structure for fabricating a stacked wafer surface telecommunication contact using a rewiring structure according to a fifth embodiment of the present invention. [Main component symbol description] [0025] 2 circuit board 3 external telecommunication contact 4 electrode 6 first bonding layer 7 first bonding wire 9 second bonding layer 10 second bonding wire 11 sealing paste 50 stacked semiconductor element 51 semiconductor unit Form No. A0101 Page 11 / Total 23 Page 201143018 52 Package Structure 53 Circuit Board 54 First Semiconductor Unit 55 Second Semiconductor Unit 56 Sealant 57 Next Layer 58 Next Layer 59 Passive Element 60 Electrode

101 substrate 102 telecommunication contact 103 fixed structure with telecommunication transmission 110 first package unit body 120 second package unit body 300 three-dimensional wafer stack package structure 301 underlying wafer 302 stacked wafer

303 through hole 310 next layer 311 insulating layer 312 through hole 320 filling conductive material 321 first telecommunication contact 322 second telecommunication contact 323 third telecommunication contact 324 fourth telecommunication contact form number A0101 12/23 Page 201143018 325 Telecommunications contact layer Next layer 330 Wire conductor 340 Sealing resin 350 Substrate 400 Three-dimensional stacked package structure 424 Fourth telecommunications junction 450 First substrate 460 Second substrate 470 Ball array structure

501 bottom wafer 502 first stacked wafer 503 second stacked wafer 504 third stacked wafer 530 wire bonding wire 540 Fengsheng tree 550 substrate 600 three-dimensional stacked package structure

650 First substrate 660 Second substrate 670 Ball array structure 700 Three-dimensional stacked package structure 701 Underlying wafer 702 Stacked wafer 703 Stacked wafer 800 Three-dimensional stacked package structure 820 Filled hole conductive material Form No. A0101 Page 13 of 23 201143018

821 First telecommunications contact 822 Rewiring structure 830 Wire drawing Form No. A0101 Page 14 of 23

Claims (1)

201143018 VII. Patent application scope: 1. An electronic package structure comprising at least: a single bottom wafer having a single or multiple telecommunication contacts on the surface, which is bonded to the substrate by an adhesive layer; the substrate has a single or multiple telecommunication connections a single or a plurality of stacked wafers stacked on the surface of the underlying wafer for the purpose of a three-dimensional stacked package structure; the stacked wafer has a single or a plurality of through holes, and is completely or partially covered with an insulating layer; the insulation The layer structure has a single or a plurality of through holes for filling the hole-filling conductive material; the surface of the hole-filled conductive material and the surface of the insulating layer are completely or partially covered with telecommunication contacts, so that the stacked wafer has a single number or a plurality of telecommunications Contact; the telecommunication contact can be directly fabricated on the surface of the hole-filled conductive material or fabricated by rewiring; the telecommunication contact is connected to the stacked wafer of different layers or the underlying wafer by the telecommunication contact layer The telecommunication contacts on the surface of the stacked wafer are connected to the telecommunications contacts of the substrate through the wire bonding wires; Sealant resin support structure to carry out the above-described partially or completely coated. 2. If the patent application is the electronic package structure of item 1, the telecommunications φ connection may include the purpose of connection such as conduction, insulation, and grounding. 3. The electronic package structure of claim 1, wherein the substrate is an organic substrate such as FR4 'BT, _ABF, or germanium, gallium arsenide, or other materials or a combination thereof. 4. The electronic package structure according to claim 1, wherein the hole-filled conductive material having conductive properties may be copper, tin, silver, lead, tungsten or a metal material of the above or other conductive material. combination. 5. The electronic package structure of claim 1, wherein the stacked wafer and the bottom wafer are active electronic components, sensing components, and test component form number A0101, page 15 / 23, 201143018, for the machine Power supply or a combination of the above electronic components. 6. The electronic package structure of claim 1, wherein the through-hole structure can be fabricated by, for example, laser drilling, photolithographic etching, mechanical drilling, or the like. 7. The electronic package structure of claim 1, wherein the adhesive layer is BCB, ABF, PI or other adhesive material. 8. The electronic package structure of claim 1, wherein the stacking or bonding process is performed by, for example, hot pressing, reflow soldering or the like. 9. An electronic package structure comprising: a plurality of underlying wafers having a singular or plurality of telecommunication contacts on the surface, the substrate being bonded to the substrate by a bonding layer; the substrate having a single or a plurality of telecommunication contacts; the singular or plural stacking a wafer stacked on the surface of the bottom wafer to achieve a three-dimensional stacked package structure; the stacked wafer has a single or a plurality of through holes, and is completely or partially covered with an insulating layer; the insulating layer structure has a single or a plurality of a through hole for filling the hole-filled conductive material; the surface of the hole-filled conductive material and the surface of the insulating layer are completely or partially covered with telecommunication contacts, so that the stacked wafer has a single number or a plurality of telecommunication contacts; the telecommunication contact borrows The telecommunication contact layer is connected to the stacked wafers of different layers or the underlying wafer; the telecommunication contacts on the surface of the stacked wafer are electrically connected to the telecommunication contacts of the substrate through the wire bonding wires; the above-mentioned supporting structure is carried out by making the sealing resin Partially or completely covered; the aforementioned three-dimensional stacked package structure can be formed by another electronic package form, and another Board telecommunication connection. 10. The electronic package structure of claim 9, wherein the telecommunications connection may include a conductive, insulating, grounding, etc. connection purpose. 11. The electronic package structure of claim 9, wherein the other electronic package form may include a ball array package, a needle array package, a wire seal form number A0101, page 16 / 23 pages 201143018, or other Electronic package form, or a combination of the above electronic package forms. Form No. A0101 Page 17 of 23