WO2024032023A1

WO2024032023A1 - Package structure and preparation method therefor

Info

Publication number: WO2024032023A1
Application number: PCT/CN2023/089746
Authority: WO
Inventors: 刘莹
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-08-08
Filing date: 2023-04-21
Publication date: 2024-02-15
Also published as: CN117577588A

Abstract

A package structure and a preparation method therefor. The package structure comprises a package substrate (100), a stacked-chip group (200), and wires (300). The stacked-chip group (200) is arranged inside the package substrate (100). The stacked-chip group (200) comprises a first chip (210) and a second chip (220). The first chip (210) comprises first chip bonding pads (211) and first contact pads (212). The first contact pads (212) and the first chip bonding pads (211) are respectively located on two opposite faces of the first chip (210). The first chip (210) is provided with first conductive interconnection structures (213) penetrating to the first contact pads (212). The first conductive interconnection structures (213) are electrically connected to the first chip bonding pads (211). The second chip (220) comprises second contact pads (221). The second contact pads (221) are located on one face of the second chip (220) and are bonded to the first contact pads (212). The wires (300) are connected to a first substrate bonding pad (110) and the first chip bonding pads (211).

Description

Packaging structure and preparation method thereof

Cross-references to related applications

This disclosure claims priority to the Chinese patent application filed with the China Patent Office on August 8, 2022, with application number 2022109460433 and the invention title "Packaging Structure and Preparation Method thereof", the entire content of which is incorporated into this disclosure by reference.

Technical field

The present disclosure relates to the field of integrated circuit technology, and in particular to a packaging structure and a preparation method thereof.

Background technique

With the development of semiconductor technology, three-dimensional stacking technology has emerged that can effectively improve packaging integration. Three-dimensional stacking technology stacks chips in the vertical direction. Each vertically stacked chip is connected to the first substrate pad on the packaging substrate through wires.

However, in traditional three-dimensional stacking technology, due to different chip stacking heights, the lead lengths of each chip connected to the same first substrate pad are also different. At this time, the signal transmission time between the same first substrate pad and the chips connected thereto is inconsistent, thus causing a signal time delay problem.

Contents of the invention

According to various embodiments of the present disclosure, a packaging structure and a preparation method thereof are provided.

According to various embodiments of the present disclosure, a packaging structure is provided, including:

The packaging substrate has a groove inside and includes a first substrate pad;

A stacked chipset, placed in the groove, includes:

The first chip includes a first chip bonding pad and a first contact pad. The first contact pad and the first chip bonding pad are respectively located on opposite sides of the first chip, and the first contact pad is the signal transmission end of the first chip, the first chip is provided with a first through hole, the first through hole is connected to the first contact pad, and the first through hole is filled with a first conductive An interconnection structure, the first conductive interconnection structure is electrically connected to the first chip pad;

The second chip includes a second contact pad. The second contact pad is located on a side of the second chip close to the first chip and is bonded to the first contact pad. The second contact pad is The signal transmission end of the second chip;

Draw leads to connect the first substrate pad and the first chip pad.

In some embodiments, the first contact pad is located on the front side of the first chip, and the second contact pad is located on the front side of the second chip.

In some embodiments, the first chip pad covers the first via.

In some embodiments,

The first chip also includes a first dielectric layer, the first dielectric layer and the first contact pad are located on the same side of the first chip,

The second chip further includes a second dielectric layer, the first dielectric layer and the second contact pad are located on the same side of the second chip;

The first dielectric layer is bonded to the second dielectric layer while the first contact pad is bonded to the second contact pad.

In some embodiments, the packaging substrate is further provided with wiring holes inside, and the wiring holes are located below the groove and connected with the groove.

In some embodiments,

The stacked chip set includes a stacked first stacked stack and a second stacked stack, and the second chip of the first stacked stack is connected to the second chip of the second stacked stack. , and the first chip of the second laminate group is bonded to the bottom of the groove;

The first substrate pad includes a first pad and a second pad, the first pad is located on the front side of the packaging substrate, and the second pad is located on the back side of the packaging substrate;

The lead wires include a first lead wire and a second lead wire. The first lead wire connects the first bonding pad and the first chip pad of the first stacked group. The second lead wire passes through the lead wire. The wire hole connects the second bonding pad and the first chip bonding pad of the second stacked group.

In some embodiments, the packaging structure includes an adhesive layer, the second chip of the first stacked group is located on one side of the adhesive layer, and the second chip of the second stacked group The chip is located on the other side of the adhesive layer.

In some embodiments, the packaging substrate further includes a second substrate pad and a substrate through hole. The second substrate pad is located on the back side of the packaging substrate and is connected to the first solder pad through the substrate through hole. disk connection.

In some embodiments, the length of the second lead is greater than the length of the first lead.

In some embodiments,

A conductive layer is provided inside the packaging substrate. The conductive layer includes a first conductive part and a second conductive part. The first conductive part is connected to the first pad through an interconnection hole located above it. The third conductive part is connected to the first pad through an interconnection hole located above it. The two conductive parts are connected to the second pad through interconnect holes located below them.

In some embodiments, the distance between the conductive layer and the front side of the packaging substrate is a first distance, the distance between the conductive layer and the back side of the packaging substrate is a second distance, and the first distance is equal to the second distance. distance, the length of the second lead is equal to the length of the first lead.

In some embodiments,

The stacked chip set includes a first stacked stack group and a third stacked stacked group, and the first chip pad of the first stacked stack group and the first stacked stacked panel of the third stacked stacked group are chip pad bonding;

The lead wire connects the first substrate pad and the first chip pad of the first stack group.

In some embodiments,

In the third stacked group and the first stacked group, the first chip is further provided with a third dielectric layer on the side provided with the first chip pad, and the third dielectric layer of the first stacked group is Three dielectric layers are bonded to the third dielectric layer of the third stacked layer group.

In some embodiments, the packaging structure further includes a packaging layer covering the stacked chipset and the wiring.

According to various embodiments of the present disclosure, a method for preparing a packaging structure is also provided, including:

A first wafer, a second wafer and a packaging substrate are provided. The first wafer includes a plurality of first chips. A first contact pad is provided on one side of the first chip. The second wafer includes a plurality of second chips. The second A second contact pad is provided on one side of the chip, a groove is provided inside the packaging substrate, and includes a first substrate pad;

The first wafer and the second wafer are bonded through the first contact pad and the second contact pad, and a first through hole is formed in the first chip, and the first through hole is formed in the first chip. A first conductive interconnect structure is formed in the through hole, and a first chip pad is formed on the other side of the first chip. The first through hole is connected to the first contact pad, and the first chip pad is electrically connected. the first conductive interconnect structure;

Cutting the first wafer and the second wafer bonded together to form a stacked chip set;

Place the stacked chipset in the groove;

The first substrate pad and the first chip pad are connected by wire bonding.

In some embodiments, the packaging substrate is also provided with wiring holes inside, the wiring holes are located below the groove and communicate with the groove, and the stacked chip set includes a first stacked set. And a second stacked group, the first substrate pad includes a first pad and a second pad, and the lead wire includes a first lead and a second lead;

After cutting the first wafer and the second wafer that are bonded together, the method further includes:

Connect the second chip of the first laminate group to the second chip of the second laminate group;

The step of placing the stacked chipset in the groove includes:

Bond the first chip of the second laminate group to the bottom of the groove;

The method of connecting the first substrate pad and the first chip pad by wiring includes:

Connect the first bonding pad and the first chip bonding pad of the first stacked group through the first lead;

The second bonding pad is connected to the first chip bonding pad of the second stacked group by passing the second lead wire through the wiring hole.

In some embodiments, the stacked chipset includes a first stacked group and a third stacked group,

bonding the first chip pad of the first stack group to the first chip pad of the third stack group;

The first substrate pad and the first chip pad of the first stacked group are connected by wire bonding.

The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will become apparent from the description, drawings, and claims.

Description of drawings

In order to more clearly explain the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings needed to be used in the description of the embodiments or the traditional technology will be briefly introduced below. Obviously, the drawings in the following description are only for the purpose of explaining the embodiments or the technical solutions of the traditional technology. For some disclosed embodiments, those of ordinary skill in the art can also obtain other drawings based on these drawings without exerting creative efforts.

Figures 1 to 6 are structural schematic diagrams of packaging structures provided in different embodiments;

Figure 7 is a schematic view of the back of the first pad provided in an embodiment;

Figure 8 is a schematic diagram of the preparation process of the packaging structure provided in an embodiment;

Figure 9 is a schematic structural diagram of a packaging substrate provided in an embodiment;

Figure 10 is a schematic diagram of the bonding of the first wafer and the second wafer in an embodiment;

FIG. 11 is a schematic diagram of cutting the first wafer and the second wafer bonded together in one embodiment.

To better describe and illustrate embodiments and/or examples of those inventions disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the drawings should not be construed as limiting the scope of any of the disclosed inventions, the embodiments and/or examples presently described, and the best modes currently understood of these inventions.

Detailed ways

To facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. There is illustrated in the accompanying drawings a preferred embodiment of the present disclosure. However, the present disclosure may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein in the description of the disclosure is for the purpose of describing specific embodiments only and is not intended to limit the disclosure.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer. A layer may be on, adjacent to, connected to, or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. layer.

It will be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or Sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

Spatial relational terms such as "under", "under", "under", "under", "on", "above", etc., in This may be used to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "under" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" may include both upper and lower orientations. Additionally, the device may be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

As used herein, the singular forms "a," "an," and "the" may include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that when the terms "consist" and/or "comprise" are used in this specification, the presence of stated features, integers, steps, operations, elements and/or parts may be identified but not to the exclusion of one or more other The presence or addition of features, integers, steps, operations, elements, parts and/or groups. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.

It should be noted that when a component is considered to be "connected" to another component, it can be directly connected to the other component. A component, or connected to another component via a centered component. In addition, "connection" in the following embodiments should be understood as "electrical connection" if there is transmission of electrical signals or data between the connected objects.

Embodiments of the present disclosure should not be limited to the specific shapes illustrated in the drawings of the specification but include deviations in shapes due to, for example, manufacturing techniques.

In one embodiment, please refer to FIG. 1 , a packaging structure is provided, including a packaging substrate 100 , a stacked chipset 200 and leads 300 .

The packaging substrate 100 may include, but is not limited to, a ceramic substrate. For example, it may also be a glass substrate or the like. The package substrate 100 is provided with a groove 100a inside. The groove 100a may be formed by machining the package substrate 100. The package substrate 100 includes a first substrate pad 110 . The first substrate pad 110 is used for wire bonding with the chips in the stacked chipset 200 .

The stacked chipset 200 is placed in the groove 100a, and may include a plurality of stacked chips. As an example, some chips in the stacked chipset 200 may be located inside the groove 100a. Of course, it is also possible to arrange that all chips in the stacked chipset 200 are located inside the groove 100a. The comparison here is not limited. The arrangement form of each chip in the laminated chip set 200 in the groove can be adjusted according to actual needs.

Specifically, the stacked chipset 200 includes a first chip 210 and a second chip 220 . The first chip 210 and the second chip 220 are bonded together.

The first chip 210 includes a first chip pad 211 and a first contact pad 212 . The first chip pad 211 is used for wire connection with the packaging substrate 100 . The first contact pad 212 is used for bonding with the second chip 220 . The first contact pad 212 and the first chip pad 211 are respectively located on opposite sides of the first chip 210 .

At the same time, the first chip 210 is also provided with a first through hole 210a. As an example, the first through hole 210a may be a through silicon via.

The first through hole 210a is connected to the first contact pad 212. Moreover, the first through hole 210a fills the first conductive interconnection structure 213, so that the first conductive interconnection structure 213 and the first contact pad 212 are in contact and conductive. At the same time, the first conductive interconnection structure 213 is electrically connected to the first chip pad 211, so that the signal on the first chip pad 211 can be transmitted to the first contact pad 212, or the signal on the first contact pad 212 can be transmitted to on the first chip pad 211.

Specifically, a plurality of first through holes 210a can be provided on the first chip 210, so that various signals (such as input and output signals of the chip, control signals, etc.) can be transmitted.

For example, as shown in FIG. 1 , two rows of multiple first through holes 210a are provided. The figure shows that in addition to the two first through holes 210a located on the same cross-section, the two first through holes 210a may be located in two rows of first through holes 210a respectively.

As an example, the first chip pad 211 may cover the first through hole 210a, so that the first chip pad 211 and the first conductive interconnection structure 213 may be directly connected. Of course, the first chip pad 211 and the first conductive interconnection structure 213 can also be connected through other conductive lines, which is not limited here.

At the same time, the materials of the first chip pad 211, the first contact pad 212 and the first conductive interconnection structure 213 may include metal materials, such as Au, Ni, W, Cu, Al, etc. Among them, the materials of any two materials may be the same or different, and the comparison is not limited here.

The second chip 220 includes second contact pads 221 . The material of the second contact pad 221 may also include a metal material, which may be the same as the material of the first contact pad 212 or may be different.

The second contact pad 221 is located on a side of the second chip 220 close to the first chip 210 and is bonded to the first contact pad 212 . Specifically, the second contact pad 221 and the first contact pad 212 may be directly bonded, or may be bonded through bumps formed of solder or the like (not shown). When bump bonding is used, bumps can be formed on the second contact pad 221 before bonding, bumps can also be formed on the first contact pad 212, or bumps can be formed between the second contact pad 221 and the first contact pad 212. Bumps are formed on the pads 212 .

Meanwhile, as an example, the first chip 210 may also include a first dielectric layer 214 , and the first dielectric layer 214 and the first contact pad 212 are located on the same surface of the first chip 210 . The second chip 220 may further include a second dielectric layer 222 , and the second dielectric layer 222 and the second contact pad 221 are located on the same surface of the second chip 220 . While the first contact pad 212 and the second contact pad 221 are bonded, the first dielectric layer 214 can be bonded with the second dielectric layer 222, so that the first chip 210 and the second chip 220 are reliably connected and stacked.

At this time, on the one hand, the first chip 210 and the second chip 220 are connected together, and on the other hand, the first contact pad 212 and the second contact pad 221 are conductively connected. Therefore, the signal on the first chip pad 211 can be transmitted to the second contact pad 221 , or the signal on the second contact pad 221 can be transmitted to the first chip pad 211 .

At the same time, the first contact pad 212 can be used as a signal transmission end of the first chip 210 , and the second contact pad 221 can be used as a signal transmission end of the second chip 220 . Therefore, the first chip pad 211 can transmit signals with the first chip 210 and the second chip 220 at the same time.

It can be understood that the number of the first contact pads 212 may be multiple, and the first contact pads 212 serving as the signal transmission end of the first chip 210 may be part of the first contact pads 212 therein. And the first through holes 210a are connected to the first contact pads 212 serving as signal transmission ends. The other part of the first contact pads 212 may be used only for bonding. Of course, in some embodiments, the first contact pad 212 which is only used for bonding may not be provided. At this time, all first contact pads 212 serve as signal transmission terminals.

Correspondingly, the number of second contact pads 221 may be multiple, and the second contact pads 221 serving as the signal transmission end of the second chip 220 may be part of the second contact pads 221 therein. The other part of the second contact pads 221 may be used only for bonding. Of course, in some embodiments, the second contact pad 221 which is only used for bonding may not be provided. At this time, all the second contact pads 221 serve as signal transmission terminals. The lead wire 300 may be a gold wire, for example. The lead wire 300 connects the first substrate pad 110 and the first chip pad 211 .

At this time, the first substrate pad 110 can be connected to the first chip 210 through the lead wire 300, the first chip pad 211, the first conductive interconnection structure 213 in the first through hole 210a, and the first contact pad 212 in sequence. signal transmission between. Furthermore, the first substrate pad 110 may be connected to the first substrate pad 110 by sequentially connecting the leads 300, the first chip pad 211, the first conductive interconnection structure 213 in the first through hole 210a, the first contact pad 212, and the second contact pad 221. Signal transmission is performed between the second chips 220 .

Therefore, in this embodiment, the first chip 210 and the second chip 220 can be connected to the same first substrate pad 110 of the same signal channel, and the first substrate pad 110 is connected to the first chip 210 and the second chip 220 The length of the signal transmission path between them is basically the same, which can effectively improve the time delay problem.

At the same time, in this embodiment, since the stacked chipset 200 is placed in the groove 100a of the packaging substrate 100, the first chip pad 211 on the first chip 210 and the first chip pad 211 on the packaging substrate 100 can be effectively reduced. The height difference between the substrate pads 110. At this time, the length of the lead wire 300 connecting the first chip pad 211 and the first substrate pad 110 The degree can be effectively reduced, thereby reducing the length of the signal transmission path between the first substrate pad 110 and the first chip 210 and the second chip 220 connected thereto, thereby effectively reducing the resistance in the signal transmission path.

In one embodiment, please refer to FIG. 1 , the first contact pad 212 is located on the front side of the first chip 210 , and the second contact pad 221 is located on the front side of the second chip 220 .

Specifically, conductive circuits may also be provided on the front side of the first chip 210, and the conductive circuits are connected to semiconductor devices (such as memory cells) in the first chip 210 for signal transmission therewith.

Conductive circuits may also be provided on the front side of the second chip 220, and the conductive circuits are connected to the semiconductor devices (such as memory cells) in the second chip 220 for signal transmission therewith.

Disposing the first contact pad 212 on the front surface of the first chip 210 and the second contact pad 221 on the front surface of the second chip 220 can ensure the signal reception or output of the semiconductor devices in the first chip 210 and the second chip 220 . The transmission times of the signals are consistent.

At the same time, the first contact pad 212 is disposed on the front side of the first chip 210, so that external signals can be quickly transmitted to the semiconductor device in the first chip 210 through the first substrate pad 110. The semiconductor device in the first chip 210 can Signals can also be quickly transmitted to the outside, thus effectively reducing the length of the signal transmission path.

Similarly, the second contact pad 221 is disposed on the front surface of the second chip 220, which allows external signals to be quickly transmitted to the semiconductor device in the second chip 220 via the first substrate pad 110. The semiconductor device in the second chip 220 The signal can also be quickly transmitted to the outside, so the length of the signal transmission path can be effectively reduced.

Of course, in other embodiments, the arrangement forms of the first contact pad 212 and the second contact pad 221 may also be different.

For example, please refer to the first stack group 200a in FIG. 4 , the first contact pad 212 can also be disposed on the back of the first chip 210 , and the second contact pad 221 can be disposed on the back of the second chip 220 . At this time, the first chip bonding pad 211 is provided on the front side of the first chip 210 . The signal on the first chip pad 211 can be transmitted from the first through hole 210a to the first contact pad 212 connected thereto. At the same time, the first contact pad 212 can be connected to another first contact pad 212 by providing conductive traces on the back of the first chip 210 . The first chip 210 and the second chip 220 may form second through holes 20b on both sides of the other first contact pad 212, and through the second through holes 20b, signals can be led to the first chip 210 and the second chip 220. The front side of chip 220. At this time, it can also be ensured that the transmission time of the received signal or the output signal of the semiconductor devices in the first chip 210 and the second chip 220 is consistent.

Alternatively, in some embodiments, please refer to the first stack group 200a in FIG. 5 , the first contact pad 212 can also be provided on the back side of the first chip 210 , and the second contact pad 221 can be provided on the front side of the second chip 220 . At this time, the first chip bonding pad 211 is disposed on the front side of the first chip 210, so that signals can be directly transmitted to the semiconductor device in the first chip 210 through the conductive lines on the front side. At the same time, the first chip pad 211 can perform signal transmission with the semiconductor device in the second chip 220 through the first conductive interconnection structure 213, the first contact pad 212, and the second contact pad 221 in the first through hole 210a.

At this time, compared to the first chip 210, the signal transmission path of the second chip 220 mainly includes the first conductive interconnection structure 213 in the first through hole 210a. However, the chip thickness is relatively thin, which is much smaller than the length of the lead wire. That is, the length of the first through hole 210a is much shorter than the length of the lead wire. Therefore, the first conductive interconnection structure 213 in the first through hole 210a has less influence on transmission signal transmission. Therefore, at this time, the signals of the first chip 210 and the second chip 220 Transmission time consistency will also be improved relative to traditional technology.

Alternatively, in some embodiments, referring to the first stacked group 200a in FIG. 6 , the first contact pad 212 is located on the front side of the first chip 210 and the second contact pad 221 is located on the back side of the second chip 220 . At this time, the first chip bonding pad 211 is provided on the back side of the first chip 210, and can communicate with the semiconductor in the first chip 210 through the first conductive interconnection structure 213 and the first contact pad 212 in the first through hole 210a. device for signal transmission. At the same time, a second through hole 20b may be provided in the second chip 220 to be connected to the second contact pad 221 and form a second conductive interconnection structure with the second through hole. At this time, the first chip pad 211 can pass through the first conductive interconnection structure 213 in the first through hole 210a, the first contact pad 212, the second contact pad 221, and the second conductive interconnection in the second through hole 20b. structure to perform signal transmission with the semiconductor device in the second chip 220 .

At this time, compared to the first chip 210 , the second conductive interconnection structure in the second through hole is mainly added to the signal transmission path of the second chip 220 . However, the chip thickness is relatively thin, which is much smaller than the length of the lead wire. That is, the length of the second through hole is much shorter than the length of the lead wire. Therefore, the second conductive interconnection structure in the second through hole has less influence on transmission signal transmission. Therefore, at this time, the signal transmission time consistency between the first chip 210 and the second chip 220 will also be improved compared to the traditional technology.

In one embodiment, please refer to FIG. 9 , the packaging substrate 100 is also provided with wiring holes 100b inside, and the wiring holes 100b are located below the groove 100a and connected with the groove 100a.

At this time, both sides of the packaging substrate 100 can be connected by wire bonding, thereby making the wire bonding more flexible.

In one embodiment, please refer to FIG. 1 or FIG. 2 , the stacked chipset 200 includes a first stacked group 200a and a second stacked group 200b arranged in a stack.

The first chip 210 of the second lamination group 200b is bonded to the bottom of the groove 100a.

Specifically, the first chip 210 of the second stack group 200b can be bonded to the bottom of the groove 100a through conductive glue. Conductive adhesive contains silver components, which are good conductors of heat and have good heat dissipation properties. Therefore, at this time, while connecting the first chip 210 of the second stacked group 200b and the packaging substrate 100, the heat dissipation performance can also be taken into consideration. Of course, the first chip 210 of the second stacked group 200b can also be bonded to the bottom of the groove 100a through non-conductive glue, which is not limited here.

At the same time, the second chip 220 of the first stacked group 200a is connected to the second chip 220 of the second stacked group 200b, so that the first stacked group 200a and the second stacked group 200b are stacked together.

As an example, the packaging structure may be provided to include an adhesive layer 400 . The adhesive layer may be a DAF (Die attach film) layer.

The second chip 220 of the first laminated group 200a is located on one side of the adhesive layer 400, and the second chip 220 of the second laminated group 200b is located on the other side of the adhesive layer 400. The first laminate group 200a and the second laminate group 200b can be reliably connected through the adhesive layer 400. Of course, the first laminate group 200a and the second laminate group 200b can also be connected through other methods (such as bonding methods). This is not limited here.

At this time, the first stacked group 200a and the second stacked group 200b can be connected to different substrate pads of different signal channels.

Specifically, at this time, the first substrate pad 110 includes a first pad 111 and a second pad 112 .

The first pad 111 is located on the front side of the package substrate 100 to provide signals to the chips in the first stack group 200a or to receive signals on the chips in the first stack group 200a. The second pad 112 is located on the back side of the package substrate 100 to provide signals to the chips in the second stack group 200b or to receive signals on the chips in the second stack group 200b.

Specifically, referring to FIG. 7 , the first substrate pad 110 may include a plurality of first pads 111 and a corresponding plurality of second pads 112 .

The plurality of first bonding pads 111 can transmit multiple different signals, and each first bonding pad 111 independently transmits a signal. The same signal transmitted through the same first pad 111 can be provided to the first chip 210 and the second chip 220 in the first stack group 200a at the same time.

Similarly, the plurality of second bonding pads 112 may transmit a plurality of different signals, with each first bonding pad 112 independently transmitting a signal. The same signal transmitted through the same second pad 112 can be provided to the first chip 210 and the second chip 220 in the second stack group 200b at the same time.

The lead wire 300 includes a first lead wire 310 and a second lead wire 320 .

The first lead 310 connects the first bonding pad 111 to the first chip bonding pad 211 of the first stacked group 200a, thereby realizing signal transmission between the first bonding pad 111 and the chips in the first stacked group 200a.

The second lead 320 passes through the wiring hole 100b to connect the second bonding pad 112 and the first chip bonding pad 211 of the second stacked group 200b, thereby realizing the connection between the second bonding pad 112 and the chip in the second stacked group 200b. Signal transmission. Specifically, the package structure may be provided with a plurality of second bonding pads 112, and the bonding wires 300 connected to the plurality of second bonding pads 112 may pass through the same bonding hole 100b and be connected to the corresponding first chip bonding pad of the second stack group 200b. 211.

In this embodiment, the lengths of the signal transmission paths between the first chip 210 and the second chip 220 of each stacked chip set are basically the same. At the same time, the two stacked chip groups (the first stacked group 200a and the second stacked group 200b) are connected, which can effectively improve the signal time delay problem and effectively increase the packaging integration level.

At the same time, the arrangement of the wiring holes 100b allows both sets of stacked chips to be connected to the first substrate pad 110 on the packaging substrate 100 at a nearby location, thereby enabling simple and effective signal transmission.

In one embodiment, referring to FIG. 1 , the package substrate 100 further includes a second substrate pad 120 and a substrate through hole 100c.

The second substrate pad 120 is located on the back side of the packaging substrate 100, and is located on the same surface of the packaging substrate 100 as the second pad 112 of the first substrate pad 110, and can be processed and formed at the same time.

At the same time, the second substrate pad 120 is connected to the first pad 111 of the first substrate pad 110 through the substrate through hole 100c, so that the signal can be introduced to the first pad 111 or the signal on the first pad 111 can be received. .

Specifically, a third conductive interconnection structure 130 may be disposed in the substrate through hole 100c, and the third conductive interconnection structure 130 connects the second substrate pad 120 and the first pad 111 of the first substrate pad 110 .

At this time, the first solder ball 140 and the second solder ball 150 may also be provided on the package substrate 100 . The first solder ball 140 may be located under the second pad 112 of the first substrate pad 110 , and the second solder ball 150 may be located under the second substrate pad 120 . The package structure can be soldered to the printed circuit board through the first solder ball 140 and the second solder ball 150 to connect with an external circuit.

As an example, the length of the second lead wire 320 may be set to be greater than the length of the first lead wire 310 .

For the first stacked group 200a, in its signal transmission path, the second solder ball 150 sequentially passes through the second substrate pad 120, the third conductive interconnection structure 130 in the substrate through hole 100c, the first pad 111, the first The lead 310 is connected to the first chip pad 211 to perform signal transmission with the first chip 210 and the second chip 220 of the first stacked group 200a.

For the second stacked group 200b, in its signal transmission path, the first solder ball 140 is connected to the first chip pad 211 through the second pad 112 and the second lead 320, thereby connecting with the second stacked group 200b. Signal transmission is performed between the first chip 210 and the second chip 220 .

In the signal transmission path of the first stacked group 200a, the second substrate pad 120 and the third conductive interconnection structure 130 in the substrate through hole 100c are required to guide the signal on the second solder ball 150 to the first pad 111. In the signal transmission path of the second stacked group 200b, there is no need for the second substrate pad 120 and the third conductive interconnection structure 130 in the substrate through hole 100c to guide the signal on the first solder ball 140 to the second pad. 112.

At this time, setting the length of the second lead 320 to be greater than the length of the first lead 310 can facilitate signal transmission between the two stacked chip groups (the first stacked group 200a and the second stacked group 200b). The lengths of the transmission paths are basically the same, which can more effectively improve the signal time delay problem.

Specifically, the thickness of the packaging substrate 100, the thickness of the wiring hole 100b, etc. can be adjusted to achieve the length of the signal transmission path between the two stacked chip groups (the first stacked group 200a and the second stacked group 200b). are basically consistent.

In one embodiment, please refer to FIG. 2 , a conductive layer 160 is provided inside the packaging substrate 100 . The conductive layer 160 includes a first conductive part 161 and a second conductive part 162 . The first conductive part 161 may be connected to the first pad 111 through an interconnection hole above it. The second conductive part 162 may be connected to the second pad 112 through an interconnection hole thereunder.

Specifically, the packaging substrate 100 may also be provided with a third substrate pad 170 . A third solder ball 180 may be provided under the third substrate pad 170 . The third solder ball 180 can solder the package structure to the printed circuit board to connect with external circuits. At the same time, the third substrate pad 170 can connect the first conductive part 161 and the second conductive part 162 through the interconnection hole, so that signals can be obtained from the conductive layer 160 or signals can be transmitted to the conductive layer 160 .

At this time, for the first stacked group 200a, in the signal transmission path, the third solder ball 180 passes through the third substrate pad 170, the first conductive part 161, the first pad 111, and the first lead 310 in order to connect with the first lead 310. A chip pad 211 is connected to perform signal transmission with the first chip 210 and the second chip 220 of the first stack group 200a.

For the second stacked group 200b, in its signal transmission path, the third solder ball 180 passes through the third substrate pad 170, the second conductive part 162, the second pad 112, and the second lead 320 in order to be bonded to the first chip. The disk 211 is connected to perform signal transmission with the first chip 210 and the second chip 220 of the second stacked group 200b.

As an example, the distance between the conductive layer 160 and the front surface of the packaging substrate 100 may be a first distance. At the same time, the distance between the conductive layer 160 and the back surface of the packaging substrate 100 is the second distance. The first distance may be set equal to the second distance. At the same time, the length of the second lead 320 is equal to the length of the first lead 310 .

At this time, the lengths of the signal transmission paths between the two stacked chip groups (the first stacked group 200a and the second stacked group 200b) can also be basically the same, so that the signal can be improved more effectively. Time delay issue.

Of course, there may also be a certain deviation between the first distance and the second distance. At this time, the difference between the two can be controlled within the first preset range, thereby effectively controlling the signal time delay problem. The first preset range can be set according to actual requirements.

There may also be a certain deviation between the length of the second lead 320 and the length of the first lead 310 . At this time, the difference between the two can be controlled within the second preset range, thereby effectively controlling the signal time delay problem. The second preset range can be set according to actual requirements.

In one embodiment, referring to FIG. 3 , the stacked chipset 200 includes a stacked first stacked set 200a and The third stack group 200c. The first chip pads 211 of the first laminate group 200a and the third laminate group 200c are bonded to each other.

Specifically, at this time, the first chip pads 211 of the first stacked group 200a and the third stacked group 200c may be directly bonded, or may be bonded through bumps formed of solder or the like (not shown). When bump bonding is used, bumps may be formed on the first chip pad 211 of the first stack group 200a before bonding, or may be formed on the first chip pad 211 of the third stack group 200c. Bumps can be formed on both.

Meanwhile, as an example, the first chip 210 of the first stacked group 200a may also be provided with a third dielectric layer 215 on the side where the first chip pad 211 is provided. At the same time, the first chip 210 of the third stacked group 200c may also be provided with a third dielectric layer 215 on the side where the first chip pad 211 is provided. At this time, while the first chip pads 211 of the first stacked group 200a and the third stacked group 200c are bonded to each other, the third dielectric layers 215 of the two can also be bonded at the same time, so that the first stacked group is 200a and the third stack group 200c are reliably connected together.

At the same time, the first chip pad 211 of the first stack group 200a can be used for wire bonding, and its length can be greater than the length of the first chip pad 211 of the third stack group 200c, so that the first stack group The same first chip pad 211 on the first chip pad 211 of 200a can also be conveniently used for wire bonding while bonding.

At this time, during the preparation process of the packaging structure, the edge of the third stack group 200c can be cut off, thereby exposing the first chip pad 211 of the first stack group 200a for wiring. The third dielectric layer 215 at the edge of the third stack group 200c can be removed, thereby exposing the first chip pad 211 of the first stack group 200a for wiring.

In this embodiment, by bonding the first chip pads 211 of the first stacked group 200a and the third stacked group 200c to each other, they can be stacked. At the same time, the mutually bonded first chip pads 211 can make the lengths of the signal transmission paths between the stacked first stack group 200a and the third stack group 200c substantially consistent. At this time, the signal time delay problem can be effectively improved, and the packaging integration level can be effectively improved.

Here, it can be understood that the package structure illustrated in the figure simultaneously includes a first stack group 200a, a second stack group 200b, and a third stack group 200c. However, in some embodiments, the packaging structure may also include only the first stack group 200a and the third stack group 200c.

In one embodiment, referring to FIG. 1 , the packaging structure further includes an packaging layer 500 . The encapsulation layer 500 covers the stacked chipset 200 and the lead wires 300, thereby insulating oxygen and water to the chips in the stacked chipset 200 and the lead wires 300, thereby protecting them.

In one embodiment, referring to Figure 8, a method for preparing a packaging structure is also provided, including:

Step S10, please refer to FIG. 9 and FIG. 10 to provide a first wafer 10, a second wafer 20 and a packaging substrate 100. The first wafer 10 includes a plurality of first chips 210, and a first contact pad is provided on one side of the first chip 210. 212. The second chip 20 includes a plurality of second chips 220. The second chip 220 is provided with a second contact pad 221 on one side. The package substrate 100 is provided with a groove 100a inside and includes the first substrate pad 110;

Step S20, please refer to FIG. 10, the first chip 10 and the second chip 20 are bonded through the first contact pad 221 and the second contact pad 212, and the first through hole 210a is formed in the first chip 210, and A first conductive interconnection structure 213 is formed in the first through hole 210a, and a first chip bonding pad 211 is formed on the other side of the first chip 210. The first through hole 210a is connected to the first contact pad 212, and the first chip bonding pad 211 electrically connects the first conductive interconnection structure 213;

Step S30, please refer to FIG. 11, cutting the first wafer 10 and the second wafer 20 bonded together to form a stacked chipset 200;

Step S60, please refer to Figure 1, place the stacked chipset 200 in the groove 100a;

Step S70 , please refer to FIG. 1 , connecting the first substrate pad 110 and the first chip pad 211 through the lead wire 300 .

In step S10 , please refer to FIG. 9 . The materials of the first contact pad 212 and the second contact pad 221 may include metal materials, such as Au, Ni, W, Cu, Al, etc. The two can be the same or different, and there is no restriction on the comparison here.

As an example, the first contact pad 212 is located on the front side of the first chip 210 , and the second contact pad 221 is located on the front side of the second chip 220 .

Referring to FIG. 9 , the packaging substrate 100 may include, but is not limited to, a ceramic substrate. For example, it may also be a glass substrate or the like. The package substrate 100 is provided with a groove 100a inside. The groove 100a may be formed by machining the package substrate 100.

In step S20 , please refer to FIG. 10 . There is no necessary sequence between the steps of bonding the first wafer 10 and the second wafer 20 , forming the first through hole 210 a , and forming the first chip pad 211 . Choose based on your needs.

During the bonding process of the first wafer 10 and the second wafer 20 , the second contact pad 221 and the first contact pad 212 may be bonded directly or through bumps formed by solder or the like (not shown). When bump bonding is used, bumps can be formed on the second contact pad 221 before bonding, bumps can also be formed on the first contact pad 212, or bumps can be formed between the second contact pad 221 and the first contact pad 212. Bumps are formed on the pads 212 .

As an example, the side of the first chip 210 provided with the first contact pad 212 may also be provided with a first dielectric layer 214 , and the side of the second chip 220 provided with the second contact pad 221 may also be provided with a second dielectric layer 222 .

At this time, while the first wafer 10 and the second wafer 20 are bonded through the first contact pad 212 and the second contact pad 221 , they can also be bonded through the first dielectric layer 214 and the second dielectric layer 222 .

Meanwhile, as an example, the first through hole 210a may be a through silicon via. The material of the first conductive interconnection structure 213 filled in the first through hole 210a may also include metal materials, such as Au, Ni, W, Cu, Al, etc.

At the same time, the material of the first chip pad 211 may also include metal materials, such as Au, Ni, W, Cu, Al, etc.

In step S30 , please refer to FIG. 11 , after performing the cutting process, multiple stacked chip sets 200 may be formed.

In step S60 , please refer to FIG. 1 , the stacked chipset 200 can be bonded in the groove 100 a through conductive glue or non-conductive glue.

In step S70 , referring to FIG. 1 , a wiring process is performed to form a wiring line connecting the first substrate pad 110 and the first chip pad 211 .

After step S70, it may also include:

Step S80 , forming a packaging layer 500 on the stacked chipset 200 and the lead wires 300 .

In this embodiment, the lengths of the signal transmission paths between the same first substrate pad 110 and the first chip 210 and the second chip 220 connected thereto are basically the same, thereby effectively improving the time delay problem.

At the same time, in this embodiment, since the stacked chipset 200 is placed in the groove 100a of the packaging substrate 100, the first chip pad 211 on the first chip 210 and the first chip pad 211 on the packaging substrate 100 can be effectively reduced. Substrate Pad height difference between 110. At this time, the length of the lead wire 300 connecting the first chip bonding pad 211 and the first substrate bonding pad 110 can be effectively reduced, thereby reducing the length of the first chip 210 and the second chip 220 connected to the first substrate bonding pad 110. The length of the signal transmission path between them effectively reduces the resistance in the signal transmission path.

Meanwhile, the stacked chipset 200 includes a first stacked group 200a and a second stacked group 200b. The first stacked group 200a and the second stacked group 200b may be two of the plurality of stacked chip groups 200 formed after the cutting process in step S30.

The first substrate pad 110 includes a first pad 111 and a second pad 112 . The first bonding pad 111 is located on the front side of the packaging substrate 100 , and the second bonding pad 112 is located on the back side of the packaging substrate 100 . The lead wire 300 includes a first lead wire 310 and a second lead wire 320 .

At the same time, please refer to Figure 1. After step S30, it also includes:

Step S40: Connect the second chip 220 of the first stacked group 200a to the second chip 220 of the second stacked group 200b. As an example, the two may be connected through an adhesive layer 400 .

Step S60 includes: bonding the first chip 210 of the second stack group 200b to the bottom of the groove 100a.

Step S70 includes:

Step S71, connect the first bonding pad 111 and the first chip bonding pad 211 of the first stacked group 200a through the first lead 310;

Step S72: Connect the second bonding pad 112 to the first chip bonding pad 211 of the second stacked group 200b by passing the second lead wire 320 through the wiring hole 100b.

There is no necessary sequence between step S71 and step S72 and can be set according to the actual situation.

Specifically, as an example, the package substrate 100 may further include a second substrate pad 120 and a substrate through hole 100c. The second substrate pad 120 is located on the back side of the packaging substrate 100, and is located on the same surface of the packaging substrate 100 as the second pad 112 of the first substrate pad 110, and can be processed and formed at the same time.

At this time, the length of the second lead 320 can be set to be greater than the length of the first lead 310, and the thickness of the packaging substrate, the thickness of the wiring hole 100b, etc. can be adjusted to realize two sets of stacked chips (the first stack). The lengths of the signal transmission paths between the group 200a and the second stacked group 200b) are basically the same, so that the signal time delay problem can be more effectively improved.

In one embodiment, the stacked chipset 200 includes a first stacked group 200a and a third stacked group 200c. The first stacked group 200a and the third stacked group 200c may be two of the plurality of stacked chip groups 200 formed after the cutting process in step S30.

At the same time, please refer to Figure 3. After step S30, it also includes:

Step S50: Bond the first chip pad 211 of the first stack group 200a to the first chip of the third stack group 200c. Disk 211 bonding.

As an example, the first chip 210 of the first stack group 200a may also be provided with a third dielectric layer 215 on the side where the first chip pad 211 is provided. At the same time, the first chip 210 of the third stacked group 200c may also be provided with a third dielectric layer 215 on the side where the first chip pad 211 is provided. At this time, while the first chip pads 211 of the first stacked group 200a and the third stacked group 200c are bonded to each other, the third dielectric layers 215 of the two can also be bonded at the same time, so that the first stacked group is 200a and the third stack group 200c are reliably connected together.

At the same time, step S70 includes:

Step S73, connect the first substrate pad 110 and the first chip pad 211 of the first stacked group 200a through the wire 300.

The technical features of the above embodiments can be combined in any way. To simplify the description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, all possible combinations should be used. It is considered to be within the scope of this manual.

The above-described embodiments only express several implementation modes of the present disclosure, and their descriptions are relatively specific and detailed, but should not be construed as limiting the scope of the patent application. It should be noted that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present disclosure, and these all fall within the protection scope of the present disclosure. Therefore, the protection scope of the patent disclosed should be determined by the appended claims.

Claims

A packaging structure including:

The packaging substrate (100) is provided with a groove (100a) inside and includes a first substrate pad (110);

The stacked chipset (200) is placed in the groove (100a) and includes:

The first chip (210) includes a first chip bonding pad (211) and a first contact pad (212). The first contact pad (212) and the first chip bonding pad (211) are respectively located on the first chip bonding pad (211). Two opposite sides of a chip (210), and the first contact pad (212) is the signal transmission end of the first chip (210). The first chip (210) is provided with a first through hole ( 210a), the first through hole (210a) is connected to the first contact pad (212), and the first through hole (210a) is filled with a first conductive interconnect structure (213), the first A conductive interconnect structure (213) electrically connects the first chip pad (211);

The second chip (220) includes a second contact pad (221). The second contact pad (221) is located on a side of the second chip (220) close to the first chip (210) and is connected to the first chip (210). The first contact pad (212) is bonded, and the second contact pad (221) is the signal transmission end of the second chip (220);

Draw leads (300) to connect the first substrate pad (110) and the first chip pad (211).
The package structure according to claim 1, wherein the first contact pad (212) is located on the front side of the first chip (210), and the second contact pad (221) is located on the second chip (220). ) of the front.
The package structure of claim 1, wherein the first contact pad (212) is on the back side of the first chip (210), and the second contact pad (221) is on the back side of the second chip (220).
The packaging structure of claim 1, wherein the first contact pad (212) is located on the back side of the first chip (210), and the second contact pad (221) is located on the front side of the second chip (220).
The packaging structure of claim 1, wherein the first contact pad (212) is located on the front side of the first chip (210), and the second contact pad (221) is located on the back side of the second chip (220).
The packaging structure according to any one of claims 1 to 5, wherein the first chip pad (211) covers the first through hole (210a).
The packaging structure according to any one of claims 1-6, wherein,

The first chip (210) also includes a first dielectric layer (214), the first dielectric layer (214) and the first contact pad (212) are located on the same surface of the first chip (210),

The second chip (220) also includes a second dielectric layer (222), the first dielectric layer (214) and the second contact pad (221) are located on the same surface of the second chip (220);

While the first contact pad (212) and the second contact pad (221) are bonded, the first dielectric layer (214) and the second dielectric layer (222) are bonded.
The packaging structure according to any one of claims 1 to 7, wherein the packaging substrate (100) is also provided with wiring holes (100b) inside, and the wiring holes (100b) are located in the groove (100a). ) below, and communicates with the groove (100a).
The packaging structure according to claim 8, wherein:

The stacked chip set (200) includes a first stacked set (200a) and a second stacked set (200b), and the second chip (220) of the first stacked set (200a) with the second laminate group (200b) The chips (220) are connected, and the first chip (210) of the second laminate group (200b) is bonded to the bottom of the groove (100a);

The first substrate pad (110) includes a first pad (111) and a second pad (112). The first pad (111) is located on the front side of the package substrate (100). Two pads (112) are located on the back side of the packaging substrate (100);

The lead wire (300) includes a first lead wire (310) and a second lead wire (320). The first lead wire (310) connects the first bonding pad (111) and the first stacked group (200a). ) of the first chip pad (211), the second lead (320) passes through the wiring hole (100b) to connect the second pad (112) and the second stacked group (200b) ) of the first chip pad (211).
The packaging structure according to claim 9, wherein the packaging structure includes an adhesive layer (400), and the second chip (220) of the first stacked group (200a) is located on the adhesive layer (400). 400), the second chip (220) of the second laminate group (200b) is located on the other side of the adhesive layer (400).
The packaging structure according to claim 9 or 10, wherein the packaging substrate (100) further includes a second substrate pad (120) and a substrate through hole (100c), the second substrate pad (120) is located The back side of the package substrate (100) is connected to the first pad (111) through the substrate through hole (100c).
The package structure according to claim 11, wherein the length of the second lead (320) is greater than the length of the first lead (310).
The packaging structure according to claim 9, wherein:

A conductive layer (160) is provided inside the packaging substrate (100). The conductive layer (160) includes a first conductive part (161) and a second conductive part (162). The first conductive part (161) passes through The interconnection hole located above it is connected to the first pad (111), and the second conductive portion (162) is connected to the second pad (112) through the interconnection hole located below it.
The packaging structure according to claim 13, wherein the distance between the first conductive part (161) and the front surface of the packaging substrate (100) is a first distance, and the distance between the second conductive part (162) and the package substrate is a first distance. The distance between the back surface of the substrate (100) is a second distance, and the first distance is equal to the second distance.
The package structure of claim 14, wherein the length of the second lead (320) is equal to the length of the first lead (310).
The packaging structure according to any one of claims 1-15, wherein,

The stacked chip set (200) includes a first stacked set (200a) and a third stacked set (200c), and the first chip pad (200a) of the first stacked set (200a) 211) is bonded to the first chip pad (211) of the third stack group (200c), and the lead wire (300) connects the first substrate pad (110) and the first The first chip pad (211) of the stack stack (200a).
The packaging structure according to claim 16, wherein:

In the third laminated group (200c) and the first laminated group (200a), the first chip (210) is also provided with a third chip on the side where the first chip pad (211) is provided. Dielectric layer (215), the third dielectric layer (215) of the first stack group (200a) is bonded to the third dielectric layer (215) of the third stack group (200c).
A method for preparing a packaging structure, including:

A first wafer (10), a second wafer (20) and a packaging substrate (100) are provided. The first wafer (10) includes a plurality of first chips (210). One side of the first chip (210) is provided with a third A contact pad (212), the second chip (20) includes a plurality of second chips (220), a second contact pad (221) is provided on one side of the second chip (220), the packaging substrate (100) A groove (100a) is provided inside and includes a first substrate pad (110);

The first wafer (10) and the second wafer (20) are bonded through the first contact pad (212) and the second contact pad (221), and are bonded to the first chip (20). A first through hole (210a) is formed in the first through hole (210a), a first conductive interconnect structure (213) is formed in the first through hole (210a), and a first conductive interconnect structure (213) is formed on the other side of the first chip (210). A chip pad (211), the first through hole (210a) is connected to the first contact pad (212), the first chip pad (211) is electrically connected to the first conductive interconnect structure (213) ;

Cutting the first wafer (10) and the second wafer (20) bonded together to form a stacked chip set (200);

Place the stacked chipset (200) in the groove (100a);

The first substrate pad (110) and the first chip pad (211) are connected through wires (300).
The method of preparing a packaging structure according to claim 18, wherein the packaging substrate (100) is further provided with wiring holes (100b) inside, and the wiring holes (100b) are located below the groove (100a) , and connected with the groove (100a), the laminated chip set (200) includes a first laminated group (200a) and a second laminated group (200b), and the first substrate pad (110) It includes a first bonding pad (111) and a second bonding pad (112), and the lead wire (300) includes a first lead wire (310) and a second lead wire (320);

After cutting the first wafer (10) and the second wafer (20) bonded together, the method further includes:

Connect the second chip (220) of the first stacked group (200a) to the second chip (220) of the second stacked group (200b);

The placing of the stacked chipset (200) in the groove (100a) includes:

Bond the first chip (210) of the second laminate group (200b) to the bottom of the groove (100a);

The connecting of the first substrate pad (110) and the first chip pad (211) by wiring (300) includes:

Connect the first bonding pad (111) and the first chip bonding pad (211) of the first stacked group (200a) through the first lead (310);

The second bonding pad (112) and the first chip bonding pad (211) of the second stacked group (200b) are connected by the second lead (320) passing through the wiring hole (100b). .
The method for manufacturing a packaging structure according to claim 18 or 19, wherein the stacked chip set (200) includes a first stacked set (200a) and a third stacked set (200c),

After cutting the first wafer (10) and the second wafer (20) bonded together, the method further includes:

Bonding the first chip pad (211) of the first stack group (200a) to the first chip pad (211) of the third stack group (200c);

The connecting of the first substrate pad (110) and the first chip pad (211) by wiring (300) includes:

The first substrate pad (110) and the first chip pad (211) of the first stacked group (200a) are connected through a wire (300).