CN111564419B - Chip lamination packaging structure, manufacturing method thereof and electronic equipment - Google Patents
Chip lamination packaging structure, manufacturing method thereof and electronic equipment Download PDFInfo
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- CN111564419B CN111564419B CN202010672631.3A CN202010672631A CN111564419B CN 111564419 B CN111564419 B CN 111564419B CN 202010672631 A CN202010672631 A CN 202010672631A CN 111564419 B CN111564419 B CN 111564419B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The application provides a chip stacked packaging structure, a manufacturing method thereof and electronic equipment, and relates to the technical field of chips. In this application chip stromatolite packaging structure, seted up the mounting groove on the base plate, first chip sets up in the mounting groove, and the pin of first chip passes through the conducting layer and is connected with the pad on the base plate to be connected with the signal line. The second chip is mounted on the first chip, and the pins of the second chip are connected to the conductive layer. The structure avoids the use of a routing mode to connect the first chip, the second chip and the bonding pad of the substrate, and is convenient for realizing shorter signal transmission distance, thereby being beneficial to improving the signal quality. Moreover, the conducting layer is adopted to replace the lead, and the lead of the first chip and the lead of the second chip can be prevented from being crushed or touching to cause short circuit. Due to the fact that the installation groove is formed, the first chip is embedded into the installation groove, the size of the whole packaging structure is smaller, and miniaturization of the whole electronic equipment is facilitated.
Description
Technical Field
The application relates to the technical field of chips, in particular to a chip lamination packaging structure, a manufacturing method thereof and electronic equipment.
Background
With the rapid development of the semiconductor industry, electronic products are miniaturized more and more thinly to meet the requirements of users and product performance and memory are higher and higher, so that a semiconductor packaging structure adopts a multi-chip Stack-Die (Stack-Die) technology or a chip fow (flow over wire) stacking technology to Stack two or more chips in a single packaging structure, thereby realizing the reduction of the packaging volume of the product and the improvement of the product performance. The existing chip laminated packaging structure usually adopts a routing mode to connect pins of a chip with a substrate, so that the signal transmission performance is poor, and the upper layer lead and the lower layer lead are easy to touch and short-circuit.
Disclosure of Invention
The purpose of the present application includes providing a chip stacked package structure and an electronic device, wherein the chip has a better signal transmission performance and the leads are not easily touched to each other to cause short circuit. The application further aims to provide a manufacturing method of the chip stacked package structure.
The embodiment of the application can be realized as follows:
in a first aspect, an embodiment of the present application provides a chip stacked package structure, including:
the signal wire comprises a bonding pad positioned on the surface of the substrate, and the substrate is provided with a mounting groove;
the first chip is fixed in the mounting groove, and a pin of the first chip is positioned at an opening of the mounting groove;
the conducting layer is laid on the surfaces of the substrate and the first chip and is connected with the bonding pad and the pin of the first chip;
and the second chip is arranged on the first chip in a stacking mode, and pins of the second chip are connected with the conductive layer.
In an alternative embodiment, the first chip is connected to the bottom of the mounting slot by a silver paste.
In an alternative embodiment, a gap is eliminated between the first chip and the side wall of the mounting groove by filling the sealant.
In an alternative embodiment, the side of the first chip provided with the pins is flush with the surface of the substrate.
In an optional embodiment, the chip stack package structure further includes a third chip, and the third chip is attached to the second chip and electrically connected to the bonding pad by a wire bonding.
In an alternative embodiment, the surface of the second chip is covered with an adhesive film, and the third chip is mounted on the adhesive film.
In an optional embodiment, the chip-on-chip package structure further includes a package body, and the package body wraps the second chip and covers the bonding pads and the conductive layer on the surface of the substrate.
In a second aspect, an embodiment of the present application provides a method for manufacturing a chip stacked package structure, including:
the surface of the substrate is provided with a mounting groove, the substrate is provided with a signal wire, and the signal wire comprises a bonding pad positioned on the surface of the substrate;
fixing the first chip in the mounting groove, and enabling a pin of the first chip to be located at an opening of the mounting groove;
manufacturing a conducting layer on the surface of the substrate, wherein the conducting layer is connected with the welding pad and a pin of the first chip;
and mounting a second chip on the first chip, and connecting pins of the second chip with the conductive layer.
In an alternative embodiment, before the forming the conductive layer, the forming method further includes:
and filling sealant between the first chip and the side wall of the mounting groove.
In a third aspect, an embodiment of the present application provides an electronic device, including the chip on package structure in any one of the foregoing embodiments, or including the chip on package structure manufactured by the manufacturing method in any one of the foregoing embodiments.
The beneficial effects of the embodiment of the application include:
in the chip lamination packaging structure of the embodiment of the application, the substrate is provided with the mounting groove, the first chip is arranged in the mounting groove, and the pin of the first chip is connected with the bonding pad on the substrate through the conducting layer so as to be connected with the signal line. The second chip is mounted on the first chip, and the pins of the second chip are connected to the conductive layer so as to be connected to the signal lines. Through the structure, the bonding pad of the first chip, the second chip and the substrate is prevented from being connected by using a routing mode, and a conducting layer is adopted, so that a short signal transmission distance is conveniently realized, and the signal quality is favorably improved. Moreover, the conducting layer is adopted to replace the lead, and the lead of the first chip and the lead of the second chip can be prevented from being crushed or touching to cause short circuit. In addition, due to the fact that the installation groove is formed, the first chip is embedded into the installation groove, the size of the whole packaging structure is smaller, and miniaturization of the whole electronic equipment is facilitated. The manufacturing method provided by the embodiment of the application is used for preparing the chip stack packaging structure, and the electronic device provided by the embodiment of the application comprises the chip stack packaging structure or the chip stack packaging structure manufactured by the manufacturing method.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic diagram of a chip on chip package structure according to an embodiment of the present disclosure;
FIG. 2 is a diagram of a chip on package structure according to another embodiment of the present disclosure;
FIG. 3 is a flow chart of a method for fabricating a chip stack package structure according to an embodiment of the present disclosure;
fig. 4 to 8 are diagrams illustrating a form change of a chip stack package structure in a manufacturing process according to an embodiment of the present application.
Icon: 010-chip stack package structure; 100-a substrate; 110-pads; 120-mounting grooves; 130-sealing glue; 140-solder ball; 200-a first chip; 210-a first pin; 300-a conductive layer; 400-a second chip; 410-a second pin; 420-glue film; 500-a third chip; 600-packaging body.
Detailed Description
In order to meet the requirements for product performance, a stacking technology is adopted to stack two or more chips in a single packaging structure, so that the reduction of the packaging volume of the product is realized and the product performance is improved. For example, a memory chip and a logic chip are stacked and packaged together. The existing chip laminated packaging structure usually adopts a routing mode, and a copper wire or an alloy wire is used as a lead to connect each layer of chip and a substrate. The existing chip lamination packaging structure adopts multiple chip mounting and multiple routing to complete the chip mounting and circuit connection, and finally adopts a plastic packaging process to package a plurality of chips. The existing structure is easy to cause the line arc to meet the line, thus causing the short circuit of the product. In addition, the wire bonding arc is too high, which easily causes the collapse of the wire arc when the chips are stacked, and affects the signal transmission. And the wire is used as a lead, so that the signal transmission distance between the chip and the substrate is longer, and the signal transmission loss is larger as the wire arc is longer. In summary, the conventional stacked package structure is prone to have problems of poor signal transmission performance, short circuit caused by easy touch between the upper and lower leads, and the like.
In order to solve the problems that signal transmission is poor and leads are easy to short circuit in the prior art, the embodiment of the application provides a chip stacked package structure, a manufacturing method thereof and electronic equipment. In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present application, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. are used for indicating the orientation or positional relationship based on the orientation or positional relationship shown in the drawings or the orientation or positional relationship which the present invention product is usually put into use, it is only for convenience of describing the present application and simplifying the description, but it is not intended to indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation and be operated, and thus, should not be construed as limiting the present application.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
It should be noted that the features of the embodiments of the present application may be combined with each other without conflict.
Fig. 1 is a schematic diagram of a chip stack package structure 010 according to an embodiment of the disclosure. Referring to fig. 1, the chip stack package structure 010 of the present embodiment includes a substrate 100, a first chip 200, a second chip 400, a conductive layer 300, and a package 600.
The substrate 100 in the embodiment of the present application is provided with signal lines embedded in the substrate 100 or extending to the surface of the substrate 100 for transmitting signals. In the present embodiment, the signal line includes a pad 110 extending to the surface of the substrate 100 for connecting with the chip, thereby realizing the connection between the chip and the signal line.
In the embodiment of the present application, a mounting groove 120 (see fig. 4) is formed on the substrate 100, the mounting groove 120 is used for disposing the first chip 200, and a back surface (a surface where no chip pin is disposed) of the first chip 200 faces downward and is fixedly connected to a bottom of the mounting groove 120. Specifically, the first chip 200 is fixed to the bottom of the mounting groove 120 by silver paste. The front surface (the surface having the pins) of the first chip 200 is located at the opening of the mounting groove 120. For convenience of description, the pins of the first chip 200 will be hereinafter referred to as first pins 210, and the pins of the second chip 400 will be hereinafter referred to as second pins 410. In order to facilitate connection between the bonding pad 110 and the first pin 210 of the first chip 200, in the present embodiment, the side of the first chip 200 where the first pin 210 is disposed is flush with the surface of the substrate 100. The conductive layer 300 is laid on the surfaces of the substrate 100 and the first chip 200, and connects the pad 110 and the first pin 210. It should be understood that, in order to make the front surface of the first chip 200 flush with the surface of the substrate 100, the depth of the mounting groove 120 should be slightly greater than the thickness of the first chip 200 in consideration of the thickness of the silver paste as the adhesive.
As shown in fig. 1, the conductive layer 300 may cover a portion of the pad 110 and a portion of the first pin 210, thereby connecting them, so that the first chip 200 is interconnected with the signal line. The conductive layer 300 may be made of a metal having a good conductivity, such as copper, aluminum, silver, or gold, or may be made of a conductive adhesive. According to the material selection, the manufacturing process of the conductive layer 300 may adopt a steel mesh printing manner, may also adopt a dispensing manner, and may even directly attach the prefabricated conductive layer 300 at a set position (for example, the position of the conductive layer 300 in fig. 1). In an alternative embodiment, in order to prevent the material of the conductive layer 300 from falling into the gap between the first chip 200 and the mounting groove 120 to cause signal disconnection, the gap between the first chip 200 and the sidewall of the mounting groove 120 is eliminated by filling the sealant 130. Thus, when the conductive layer 300 is formed by printing (or dispensing), the material of the conductive layer 300 is not likely to fall between the first chip 200 and the sidewall of the mounting groove 120.
The second chip 400 is mounted on the first chip 200, and as shown in fig. 1, the second pins 410 of the second chip 400 are pressed downward directly on the surface of the conductive layer 300. In other words, the first pins 210 and the second pins 410 sandwich the conductive layer 300 therebetween. In this manner, the second chip 400 is also electrically connected to the signal line and the first chip 200. The conductive layer 300 is adopted to replace a traditional process in which a wire bonding process is used for manufacturing a lead to connect the chip and the substrate 100, so that the transmission distance between the chip and the signal line of the substrate 100 is shorter, and the signal quality is better. And the structure avoids some defects of the routing process, such as easy collapse and touch of the lead.
In this embodiment, the package body 600 wraps the second chip 400 and covers the pads 110 and the conductive layer 300 on the surface of the substrate 100, thereby protecting the second chip 400. The first chip 200 is embedded in the mounting groove 120 and covered by the second chip 400, and is also protected. And because the first chip 200 is embedded in the substrate 100, the volume of the whole packaging structure is reduced.
Further, solder balls 140 are arranged on a surface of the substrate 100 away from the first chip 200 and the second chip 400 in an array manner.
Fig. 2 is a schematic diagram of a chip stack package structure 010 according to another embodiment of the present disclosure. As shown in fig. 2, in an alternative embodiment, when higher performance and higher functionality are required, the chip-on-chip package structure 010 may further include a third chip 500, where the third chip 500 is attached to the second chip 400 and electrically connected to the pad 110 by a wire bonding. The back of the third chip 500 faces the second chip 400, and the side with pins faces away from the second chip 400 and is connected to the bonding pads 110 by wire bonding. Since the first chip 200 and the second chip 400 are not connected to the bonding pad 110 by wire bonding, the leads of the third chip 500 are not pressed on the leads of other chips. Optionally, the surface of the second chip 400 is covered with an adhesive film 420, and the third chip 500 is mounted on the adhesive film 420. Of course, more chips may be provided according to particular needs. The first chip 200, the second chip 400 and the third chip 500 in the embodiments of fig. 1 and 2 may be memory chips, logic chips, etc.
Fig. 3 is a flowchart of a method for manufacturing a chip stack package structure according to an embodiment of the present disclosure, which can be used to manufacture the chip stack package structure 010 according to the embodiment of the present disclosure. Fig. 4 to 8 are diagrams illustrating a form change of the chip stack package structure 010 during a manufacturing process according to an embodiment of the disclosure. As shown in fig. 3, the manufacturing method includes:
step S100, forming a mounting groove on the surface of a substrate, wherein the substrate is provided with a signal line, and the signal line comprises a bonding pad positioned on the surface of the substrate.
Taking the fabrication of the chip stack package structure 010 provided in the embodiment of the present application as an example, the substrate 100 is fabricated in advance, and a signal line is disposed inside the substrate 100 and includes a pad 110 extending to the surface of the substrate 100. During the grooving, a laser grooving technique may be used to form the mounting groove 120 on the surface of the substrate 100, so as to obtain the structure shown in fig. 4. The depth of the mounting groove 120 should be adapted to the thickness of the first chip 200 to be mounted, considering that the upper surface of the first chip 200 is flush with the surface of the substrate 100 after being mounted in the mounting groove 120, and therefore, the depth of the mounting groove 120 should be identical to the thickness of the first chip 200 or slightly greater than the thickness of the first chip 200 (considering the thickness of the adhesive).
And S200, fixing the first chip in the mounting groove, so that the pin of the first chip is positioned at the opening of the mounting groove.
Taking the chip stack package structure 010 provided by the embodiment of the application as an example, the bottom of the mounting groove 120 is coated with silver paste as an adhesive, the back surface of the first chip 200 (without the first pin 210) is adhered to the bottom of the mounting groove 120 through the silver paste, and then the first chip 200 is fixed by baking. After the first chip 200 is mounted, the side of the first chip 200 having the first pins 210 is flush with the surface of the substrate 100, as shown in fig. 5. After the first chip 200 is mounted, a gap may exist between the first chip 200 and the sidewall of the mounting groove 120, and therefore, the sealant 130 may be filled in a dispensing manner to eliminate the gap, so as to prevent the material of the conductive layer 300 from falling into the gap between the first chip 200 and the mounting groove 120 when the conductive layer 300 is manufactured subsequently.
Step S300, a conductive layer is manufactured on the surface of the substrate, and the conductive layer is connected with the bonding pad and the pin of the first chip.
Taking the chip stack package structure 010 provided in the embodiment of the present application as an example, the conductive layer 300 can be manufactured by using a method of printing a conductive adhesive on a steel mesh, the conductive layer 300 covers a portion of the bonding pad 110 and a portion of the first pin 210, and the sealant 130 also supports the conductive layer 300, as shown in fig. 6. The conductive layer 300 replaces the traditional routing process and uses copper wires/alloy wires as leads, thereby greatly improving the signal transmission quality. In other embodiments of the present application, the conductive layer 300 may also be a metal layer; when the conductive layer 300 is formed, the sheet-like conductive layer 300 may be directly attached to a predetermined position, and the pad 110 and the first pin 210 may be connected.
Step S400, mounting a second chip on the first chip, and connecting the pin of the second chip to the conductive layer.
Taking the fabrication of the chip stacked package structure 010 provided in the embodiment of the present application as an example, one side of the second pin 410 of the second chip 400 faces downward and is attached to the first chip 200, and the second pin 410 is pressed on the conductive layer 300, so that the pin of the second chip 400 is connected to the pad 110 through the conductive layer 300, as shown in fig. 7.
After the second chip 400 is mounted, a third chip 500 (see fig. 2) may be mounted on the second chip 400 as needed, and the third chip 500 is connected to the bonding pad 110 by wire bonding. And after all the chips are mounted, plastic packaging is carried out. Taking the fabrication of the chip stacked package structure 010 in the embodiment of fig. 1 as an example, after the second chip 400 is mounted, the package body 600 is formed by using a plastic package process, the second chip 400 is wrapped, and the package body 600 covers the pad 110 and the conductive layer 300, as shown in fig. 8.
After the plastic package is completed, ball mounting may be performed, and an array of solder balls 140 may be formed on a surface of the substrate 100 away from the chip. When a plurality of chip stacked package structures 010 are formed on a large substrate 100, after the plastic encapsulation and ball placement are completed, the chip stacked package structures 010 shown in fig. 1 may be cut into individual pieces by dicing.
The embodiment of the present application further provides an electronic device, which includes the chip stack package structure 010 provided in the embodiment of the present application or the chip stack package structure 010 manufactured by the manufacturing method provided in the embodiment of the present application.
To sum up, in the chip stacked package structure 010 of the present application, the substrate 100 is provided with a mounting groove 120, the first chip 200 is disposed in the mounting groove 120, and a pin of the first chip 200 is connected to the pad 110 on the substrate 100 through the conductive layer 300, so as to be connected to a signal line. The second chip 400 is mounted on the first chip 200, and pins of the second chip 400 are connected to the conductive layer 300, thereby being connected to signal lines. Through the structure, the first chip 200 and the second chip 400 are prevented from being connected with the bonding pad 110 of the substrate 100 by using a routing mode, and the conducting layer 300 is adopted, so that a short signal transmission distance is conveniently realized, and the signal quality is favorably improved. Moreover, the conductive layer 300 is used to replace the leads, so that the leads of the first chip 200 and the leads of the second chip 400 can be prevented from being crushed or touching to cause short circuit. In addition, because the mounting groove 120 is provided, the first chip 200 is embedded into the mounting groove 120, so that the volume of the whole packaging structure is smaller, and the miniaturization of the whole electronic device is facilitated. The manufacturing method provided by the embodiment of the application is used for manufacturing the chip stack package structure 010, and the electronic device provided by the embodiment of the application includes the chip stack package structure 010 or the chip stack package structure 010 manufactured by the manufacturing method.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (8)
1. A chip stack package structure, comprising:
the signal wire comprises a bonding pad positioned on the surface of the substrate, and the substrate is provided with a mounting groove;
the first chip is fixed in the mounting groove, a pin of the first chip is positioned at an opening of the mounting groove, and a gap is eliminated between the first chip and the side wall of the mounting groove by filling sealant;
the conducting layer is laid on the surfaces of the substrate, the sealant and the first chip and is directly connected with the bonding pad and the pin of the first chip;
a second chip stacked on the first chip, and pins of the second chip are directly connected to the conductive layer.
2. The chip stack package structure according to claim 1, wherein the first chip is connected to the bottom of the mounting groove by a silver paste.
3. The chip stack package structure according to claim 1, wherein a side of the first chip on which the leads are disposed is flush with a surface of the substrate.
4. The chip stacked package structure of claim 1, further comprising a third chip, wherein the third chip is attached to the second chip and electrically connected to the bonding pad by a wire bond.
5. The chip stack package structure according to claim 4, wherein the surface of the second chip is covered with an adhesive film, and the third chip is mounted on the adhesive film.
6. The chip on package structure according to any one of claims 1 to 5, further comprising a package body encapsulating the second chip and covering the bonding pads and the conductive layer on the surface of the substrate.
7. A method for manufacturing a chip stack package structure is characterized by comprising the following steps:
the method comprises the following steps of forming a mounting groove in the surface of a substrate, wherein the substrate is provided with a signal wire, and the signal wire comprises a bonding pad positioned on the surface of the substrate;
fixing a first chip in the mounting groove, and enabling a pin of the first chip to be located at an opening of the mounting groove;
filling a sealant between the first chip and the side wall of the mounting groove;
manufacturing a conducting layer on the surface of the substrate, wherein the conducting layer is laid on the surface of the substrate, the sealant and the first chip and is directly connected with the bonding pad and the pin of the first chip;
and mounting a second chip on the first chip, and directly connecting pins of the second chip with the conductive layer.
8. An electronic device comprising the chip-on-package structure according to any one of claims 1 to 6 or the chip-on-package structure manufactured by the manufacturing method according to claim 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202010672631.3A CN111564419B (en) | 2020-07-14 | 2020-07-14 | Chip lamination packaging structure, manufacturing method thereof and electronic equipment |
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| CN202010672631.3A CN111564419B (en) | 2020-07-14 | 2020-07-14 | Chip lamination packaging structure, manufacturing method thereof and electronic equipment |
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| CN111564419A CN111564419A (en) | 2020-08-21 |
| CN111564419B true CN111564419B (en) | 2021-01-01 |
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| US20190019754A1 (en) * | 2015-12-14 | 2019-01-17 | Invensas Corporation | Embedded vialess bridges |
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| KR100650728B1 (en) * | 2004-12-24 | 2006-11-27 | 주식회사 하이닉스반도체 | stacked package and method for manufacturing the same |
| US20080157316A1 (en) * | 2007-01-03 | 2008-07-03 | Advanced Chip Engineering Technology Inc. | Multi-chips package and method of forming the same |
| US20080197469A1 (en) * | 2007-02-21 | 2008-08-21 | Advanced Chip Engineering Technology Inc. | Multi-chips package with reduced structure and method for forming the same |
| KR20090105570A (en) * | 2008-04-03 | 2009-10-07 | 주식회사 하이닉스반도체 | Stacked semiconductor package |
| US8304888B2 (en) * | 2009-12-22 | 2012-11-06 | Fairchild Semiconductor Corporation | Integrated circuit package with embedded components |
| KR20120126365A (en) * | 2011-05-11 | 2012-11-21 | 에스케이하이닉스 주식회사 | Unit package and stack package having the same |
| KR20170001238A (en) * | 2015-06-26 | 2017-01-04 | 에스케이하이닉스 주식회사 | Semiconductor package including step type substrate |
| CN210516710U (en) * | 2019-07-23 | 2020-05-12 | 中国科学技术大学 | Chip packaging structure and device |
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| US20190019754A1 (en) * | 2015-12-14 | 2019-01-17 | Invensas Corporation | Embedded vialess bridges |
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