CN215988737U - POP packaging structure based on 2.5D structure multilayer interconnection - Google Patents
POP packaging structure based on 2.5D structure multilayer interconnection Download PDFInfo
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- CN215988737U CN215988737U CN202122593487.7U CN202122593487U CN215988737U CN 215988737 U CN215988737 U CN 215988737U CN 202122593487 U CN202122593487 U CN 202122593487U CN 215988737 U CN215988737 U CN 215988737U
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- layer
- adapter plate
- semiconductor device
- insulating medium
- packaging
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The utility model discloses a POP (package on package) structure based on 2.5D (two-dimensional) structure multi-layer interconnection, which comprises an independent packaging structure and a substrate, wherein the independent packaging structure is arranged on the substrate; the independent packaging structure comprises an adapter plate; the first conducting structure is filled in the adapter plate, and a first rewiring layer and a first insulating medium layer are arranged on the front surface of the adapter plate; a second rewiring layer and a second insulating medium layer are arranged on the back surface of the adapter plate; the front surface of the adapter plate is connected with a first semiconductor device; the back of the adapter plate is connected with a second semiconductor device; the back of the adapter plate is also provided with a plastic packaging layer; a second conductive structure is filled in the plastic packaging layer; a third wiring layer and a third insulating medium layer are arranged on the plastic packaging layer; and the conducting opening of the third insulating medium layer is connected with a third semiconductor device. The packaging structure improves the product integration level, realizes the product multifunction, and has the advantages of good heat dissipation, high product reliability, small packaging volume, low production cost and high product yield.
Description
Technical Field
The utility model relates to the technical field of semiconductor chip packaging, in particular to a POP packaging structure based on 2.5D structure multilayer interconnection.
Background
With the increasing requirements of people on the performance of electronic products, the semiconductor package structure is developed in the direction of miniaturization, high density, multiple functions and systematization. However, in the existing packaging structure, the chips are directly and vertically interconnected on the substrate through the adapter plate, which greatly limits the diversification of chip integration and the improvement of integration level, and has great difficulty in integrated packaging of various chips or components, and the reliability and heat dissipation of products need to be improved; in addition, the existing packaging process has the disadvantages of complex process flow and high production cost, and the yield of the obtained product needs to be improved.
SUMMERY OF THE UTILITY MODEL
In order to solve the above technical problems, an object of the present invention is to provide a POP package structure based on 2.5D structure multi-layer interconnection. The packaging structure effectively improves the integration level of the product, realizes the multifunction of the product, and has the advantages of good heat dissipation, high product reliability, small packaging volume, low production cost and high product yield.
In order to achieve the technical purpose and achieve the technical effect, the utility model is realized by the following technical scheme:
a POP packaging structure based on 2.5D structure multilayer interconnection comprises an independent packaging structure and a substrate, wherein the independent packaging structure is arranged on the substrate; the independent packaging structure comprises an adapter plate; the adapter plate is filled with a first conductive structure, the front surface of the adapter plate is respectively provided with at least one first rewiring layer, and each first rewiring layer is respectively covered with a first insulating medium layer with a conduction opening; the back of the adapter plate is respectively provided with at least one second rewiring layer, and each second rewiring layer is respectively covered with a second insulating medium layer with a conduction opening;
the front surface of the adapter plate is connected with a first semiconductor device, and the first semiconductor device is electrically connected with the first conductive structure through a first rewiring layer;
the back of the adapter plate is connected with a second semiconductor device; the semiconductor device is electrically connected with the conductive structure through the second rewiring layer; the back of the adapter plate is also provided with a plastic packaging layer; the plastic packaging layer encapsulates the second semiconductor device; the plastic packaging layer is filled with a second conductive structure electrically connected with the second rewiring layer; the plastic packaging layer is provided with at least one third wiring layer electrically connected with the second conductive structure, and each third wiring layer is covered with a third insulating medium layer with a conduction opening; a third semiconductor device is arranged at the conduction opening of the outermost third insulating medium layer; the third semiconductor device is electrically connected with the third redistribution layer.
Furthermore, the first conductive structure and the second conductive structure are both conductive columns.
Furthermore, a bottom glue is filled between the third insulating medium layer and the third insulating medium layer of the semiconductor device.
Furthermore, an outer conductive structure is arranged at the conduction opening of the outermost first insulating medium layer on the front surface of the adapter plate and connected with the substrate.
The utility model has the beneficial effects that:
according to the utility model, the vertical holes are formed in the adapter plate, the conductive materials are filled in the vertical holes, the redistribution layers are respectively formed on the upper surface and the lower surface of the adapter plate, different semiconductor devices are integrated on the upper surface and the lower surface of the adapter plate, the semiconductor devices on the upper surface and the lower surface of the adapter plate are electrically connected by the conductive materials in the vertical through holes, the through holes are formed in the plastic packaging layer through the plastic packaging layer, the conductive materials are filled in the through holes, the redistribution layers capable of leading out signals are manufactured, and then the semiconductor devices are connected above the plastic packaging layer, so that a three-layer high-density stacking effect is formed, the integration level of a product is effectively improved, and the multi-functionalization of the product is realized.
The whole packaging structure has good heat dissipation, high product reliability and small packaging volume, and all layers are vertically arranged, so that the transmission path between each semiconductor device is shortened, the performance of the product is improved, and the high-density integrated packaging of the product is realized. The independent packaging structure is attached to the substrate, so that rewiring processing of the substrate can be avoided, production cost is saved, and product yield is improved.
Drawings
Fig. 1 is a structural diagram obtained after step S1 in the method for manufacturing a package structure of the present invention.
Fig. 2 is a structural diagram obtained after step S2 in the method for manufacturing a package structure of the present invention.
Fig. 3 is a structural diagram obtained after step S3 in the method for manufacturing a package structure of the present invention.
Fig. 4 is a structural diagram obtained after step S4 in the method for manufacturing a package structure of the present invention.
Fig. 5 is a structural diagram obtained after step S5 in the method for manufacturing a package structure of the present invention.
Fig. 6 is a structural diagram obtained after step S6 in the method for manufacturing a package structure of the present invention.
Fig. 7 is a structural diagram obtained after step S7 in the method for manufacturing a package structure of the present invention.
Fig. 8 is a schematic structural diagram of a POP package structure based on 2.5D structure multi-layer interconnection.
Detailed Description
The following detailed description of the preferred embodiments of the present invention, taken in conjunction with the accompanying drawings, will make the advantages and features of the utility model easier to understand by those skilled in the art, and thus will clearly and clearly define the scope of the utility model.
A preferred embodiment of the method for manufacturing a POP package structure based on 2.5D structure multi-layer interconnection as shown in fig. 1 to 8 includes the following steps:
s1, taking an adapter plate 100, making an opening on the adapter plate 100, filling a conductive material in the opening to form a first conductive structure 101, flattening the front surface of the adapter plate by adopting a chemical mechanical polishing mode, then making at least one first redistribution layer 102 electrically connected with the first conductive structure 101 on the adapter plate 100, and covering a first insulating medium layer 103 with a conducting opening on each first redistribution layer 102;
the material of the interposer 100 is silicon or other semiconductor material; in this embodiment, the interposer is a silicon board; the material of the first conductive structure 101 is a metal material, a conductive polymer material, a conductive ceramic material or other conductive materials; the material of the first redistribution layer 102 is one or a combination of two or more of titanium, copper, aluminum, nickel, tin, gold, and silver; the first insulating medium layer 103 is made of one or a combination of more than two of epoxy resin, polyimide derivatives, silicon oxide, silicon nitride, silicon carbide and metal oxide; in this embodiment, the first conductive structure 101 is made of a metal material, the first redistribution layer 102 is made of copper, and the first insulating dielectric layer 103 is made of epoxy resin; in this embodiment, the number of layers of the first redistribution layer 102 is two;
s2, connecting a first semiconductor device 200 having a conductive structure at some of the conductive openings of the outermost first insulating dielectric layer 103 formed in the step S1, the first semiconductor device 200 being electrically connected to the first redistribution layer 102 exposed through the conductive openings of the first insulating dielectric layer 103; forming an outer conductive structure 104 at other conducting openings of the outermost first insulating medium layer 103 by printing solder paste or ball-planting;
s3, inverting the structure obtained in the step S2, and bonding the front surface of the adapter plate 100 with a carrier plate 106 through a bonding adhesive layer 105; the material of the carrier 106 is one of glass, metal, semiconductor, and polymer; in the embodiment, the material of the carrier 106 is glass; the bonding glue layer 105 comprises a bonding material layer and a photothermal conversion layer, so that the photothermal conversion layer can be irradiated by laser in the subsequent process to strip the carrier plate; the bonding glue layer 105 can also protect the outer conductive structure 104 and the first semiconductor device 200;
s4, thinning the back of the transfer plate 100 to expose the first conductive structure 101; manufacturing at least one second rewiring layer 107 on the back surface of the interposer 100, and covering a second insulating medium layer 108 with a conduction opening on each second rewiring layer 107; flip-chip mounting the second semiconductor device 300 with the conductive structure on the back surface of the interposer 100, and electrically connecting the second semiconductor device 300 with the second redistribution layer 107 exposed through the conduction opening of the second insulating dielectric layer 108;
the material of the second redistribution layer 107 is one or a combination of two or more of titanium, copper, aluminum, nickel, tin, gold and silver; the second insulating medium layer 108 is made of one or a combination of more than two of epoxy resin, polyimide derivatives, silicon oxide, silicon nitride, silicon carbide and metal oxide; in this embodiment, the material of the second redistribution layer 107 is copper, and the material of the second insulating dielectric layer 108 is epoxy resin; in this embodiment, the number of layers of the second redistribution layer 107 is two;
s5, encapsulating the second semiconductor device 300 by using the plastic package layer 109, opening a through hole on the plastic package layer 109, and filling a conductive material in the through hole to form a second conductive structure 110; the material of the plastic sealing layer 109 is epoxy, resin, plastic polymer or other materials; the second conductive structure 110 is made of a metal material, a conductive polymer material, a conductive ceramic material or other conductive materials; in this embodiment, the plastic package layer 109 is made of epoxy, and the second conductive structure 110 is made of metal;
s6, forming at least one third redistribution layer 111 on the plastic package layer 109, and covering a third insulating dielectric layer 112 with a via hole on each third redistribution layer 111; the material of the third wiring layer 111 is one or a combination of two or more of titanium, copper, aluminum, nickel, tin, gold and silver; the third insulating medium layer 112 is made of one or a combination of two or more of epoxy resin, polyimide derivatives, silicon oxide, silicon nitride, silicon carbide and metal oxide; in this embodiment, the third redistribution layer 111 is made of copper, and the third insulating dielectric layer 112 is made of epoxy resin; in this embodiment, the number of layers of the third redistribution layer 111 is two;
s7, connecting the semiconductor device iii 400 above the outermost third insulating dielectric layer 112, the semiconductor device iii 400 being electrically connected to the third redistribution layer 111 exposed through the via opening of the third insulating dielectric layer 112; forming an underfill 113 between the third semiconductor device 400 and the third insulating dielectric layer 112 by a bottom-fill process to wrap the conductive structure at the bottom of the third semiconductor device 400; the material of the primer 113 may be resin, filler, stress release agent, adhesion promoter or other material;
s8, removing the carrier 106 by laser irradiation, cutting the interposer 100 by cutting to obtain a plurality of independent package structures, and attaching the independent package structures to the substrate 500 by picking and placing to obtain the POP package structure shown in fig. 8; the substrate 500 is connected to the outer conductive structure 104 of the independent package structure through a conductive adhesive.
Fig. 8 shows a preferred embodiment of a POP package structure based on 2.5D structure multi-layer interconnection, which includes an independent package structure and a substrate 500, wherein the independent package structure is disposed on the substrate 500; the stand-alone package structure includes an interposer 100; the interposer 100 is filled with a first conductive structure 101, the front surface of the interposer 100 is respectively provided with at least one first redistribution layer 102, and each first redistribution layer 102 is respectively covered with a first insulating medium layer 103 with a conduction opening; at least one second redistribution layer 107 is respectively arranged on the back surface of the interposer 100, and a second insulating medium layer 108 with a conduction opening is respectively covered on each second redistribution layer 107;
the front surface of the interposer 100 is connected with a first semiconductor device 200, and the first semiconductor device 200 is electrically connected with the first conductive structure 101 through the first redistribution layer 102;
the back of the adapter plate 100 is connected with a second semiconductor device 300; the second semiconductor device 300 is electrically connected with the first conductive structure 101 through the second redistribution layer 107; a plastic packaging layer 109 is also arranged on the back surface of the adapter plate 100; the second semiconductor device 300 is encapsulated by the plastic packaging layer 109; the second conductive structure 110 electrically connected to the second redistribution layer 107 is filled in the plastic package layer 109; at least one third wiring layer 111 electrically connected with the second conductive structure 110 is arranged on the plastic package layer 109, and a third insulating medium layer 112 with a conduction opening is covered on each third wiring layer 111; a third semiconductor device 400 is arranged at the conduction opening of the outermost third insulating medium layer 112; the semiconductor device three 400 is electrically connected to the third redistribution layer 111.
The first conductive structure 101 and the second conductive structure 110 are conductive pillars.
Wherein, the underfill 113 is filled between the semiconductor device III 400 and the third insulating medium layer 113.
An outer conductive structure 104 is disposed at a conduction opening of the outermost first insulating medium layer 103 on the front surface of the interposer 100, and the outer conductive structure 104 is connected to the substrate 500.
The packaging structure has the effect of three-layer high-density stacking, effectively improves the integration level of products, and realizes the multi-functionalization of the products; the whole packaging structure has good heat dissipation, high product reliability and small packaging volume, and all layers are vertically arranged, so that the transmission path between each semiconductor device is shortened, the performance of the product is improved, and the high-density integrated packaging of the product is realized. The independent packaging structure is attached to the substrate, so that rewiring processing of the substrate can be avoided, production cost is saved, and product yield is improved.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (4)
1. A POP packaging structure based on 2.5D structure multilayer interconnection is characterized by comprising an independent packaging structure and a substrate, wherein the independent packaging structure is arranged on the substrate; the independent packaging structure comprises an adapter plate; the adapter plate is filled with a first conductive structure, at least one first rewiring layer is arranged on the front surface of the adapter plate, and a first insulating medium layer with a conduction opening is covered on each first rewiring layer; at least one second rewiring layer is arranged on the back surface of the adapter plate, and a second insulating medium layer with a conduction opening is covered on each second rewiring layer;
the front surface of the adapter plate is connected with a first semiconductor device, and the first semiconductor device is electrically connected with the first conductive structure through a first rewiring layer;
the back of the adapter plate is connected with a second semiconductor device; the semiconductor device is electrically connected with the conductive structure through the second rewiring layer; the back of the adapter plate is also provided with a plastic packaging layer; the plastic packaging layer encapsulates the second semiconductor device; the plastic packaging layer is filled with a second conductive structure electrically connected with the second rewiring layer; the plastic packaging layer is provided with at least one third wiring layer electrically connected with the second conductive structure, and each third wiring layer is covered with a third insulating medium layer with a conduction opening; a third semiconductor device is arranged at the conduction opening of the outermost third insulating medium layer; the third semiconductor device is electrically connected with the third redistribution layer.
2. The POP packaging structure based on 2.5D structure multilayer interconnection of claim 1, wherein the first conducting structure and the second conducting structure are both conducting pillars.
3. The POP packaging structure based on 2.5D structure multilayer interconnection of claim 1, wherein an underfill is filled between the third insulating medium layer and the third insulating medium layer of the semiconductor device.
4. The POP packaging structure based on 2.5D structure multilayer interconnection of claim 1, wherein an outer conductive structure is arranged at the conduction opening of the outermost first insulating medium layer on the front surface of the adapter plate, and the outer conductive structure is connected with the substrate.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122593487.7U CN215988737U (en) | 2021-10-27 | 2021-10-27 | POP packaging structure based on 2.5D structure multilayer interconnection |
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| CN202122593487.7U CN215988737U (en) | 2021-10-27 | 2021-10-27 | POP packaging structure based on 2.5D structure multilayer interconnection |
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| CN215988737U true CN215988737U (en) | 2022-03-08 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113823612A (en) * | 2021-10-27 | 2021-12-21 | 华天科技（昆山）电子有限公司 | POP packaging structure based on 2.5D structure multi-layer interconnection and manufacturing method thereof |
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2021
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113823612A (en) * | 2021-10-27 | 2021-12-21 | 华天科技（昆山）电子有限公司 | POP packaging structure based on 2.5D structure multi-layer interconnection and manufacturing method thereof |
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