CN115206945A - Packaging structure and electronic equipment - Google Patents

Packaging structure and electronic equipment Download PDF

Info

Publication number
CN115206945A
CN115206945A CN202110402099.8A CN202110402099A CN115206945A CN 115206945 A CN115206945 A CN 115206945A CN 202110402099 A CN202110402099 A CN 202110402099A CN 115206945 A CN115206945 A CN 115206945A
Authority
CN
China
Prior art keywords
chip
bonding pad
substrate
pad
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110402099.8A
Other languages
Chinese (zh)
Inventor
梁伦鹏
孙顺清
尹秋峰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Amlogic Shanghai Co Ltd
Original Assignee
Amlogic Shanghai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Amlogic Shanghai Co Ltd filed Critical Amlogic Shanghai Co Ltd
Priority to CN202110402099.8A priority Critical patent/CN115206945A/en
Publication of CN115206945A publication Critical patent/CN115206945A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

The invention provides a packaging structure and electronic equipment, wherein a plurality of chips are sequentially stacked on a packaging substrate, and occupy the space in the normal direction of the packaging substrate, so that the plurality of chips do not need to occupy too much plane area of the packaging substrate, the surface area utilization rate of the packaging substrate is improved, the size of the packaging substrate is favorably reduced, the size of the packaging structure is further reduced, and the packaging cost is reduced; the chip stacking structure is connected with the packaging substrate through the first welding wire structure and the second welding wire structure, therefore, the first welding wire structure and the second welding wire structure are distributed in the normal direction of the surface of the packaging substrate, the plane area of the packaging substrate occupied by the corresponding first welding wire structure and the second welding wire structure is smaller, the surface area utilization rate of the packaging substrate is improved, the size of the packaging substrate is favorably reduced, and the size of the packaging structure is further reduced.

Description

Packaging structure and electronic equipment
Technical Field
The embodiment of the invention relates to the technical field of chip packaging, in particular to a packaging structure and electronic equipment.
Background
With the trend of ultra-large scale integrated circuits, the feature size of the integrated circuits is continuously decreasing, and the requirements of people on the packaging technology of the integrated circuits are also increasing correspondingly. Conventional packaging technologies include Ball Grid Array (BGA), chip Scale Package (CSP), wafer Level Package (WLP), three-dimensional Package (3D), system In Package (SiP), and the like.
The System package can combine a plurality of active elements with different functions, passive elements, micro Electro Mechanical Systems (MEMS), optical elements and other elements into a unit to form a System or subsystem which can provide multiple functions, and allow heterogeneous IC integration.
However, with the development of science and technology, electronic products such as mobile phones, tablets, smartwatches, etc. are becoming multifunctional, miniaturized and thinned, and the packaging of the chip inside the product is required to be smaller and thinner, and to store larger data volume. Due to chip fabrication process limitations and the demand for chip size towards miniaturization, the capacity of a single chip is still limited, typically from 4GB to 16GB. If the memory device needs larger capacity, a plurality of chips need to be packaged together, the trend of the semiconductor packaging structure is multi-chip packaging, two or more semiconductor chips are combined in a single packaging structure, the whole circuit volume is reduced, and the memory capacity is improved.
The traditional multi-chip packaging structure adopts a side-by-side multi-chip packaging structure, namely two or more chips are arranged on the same substrate side by side, and the substrate is enlarged along with the increase of the number of the chips, so that the volume of the conventional System In Package (SIP) is large, the internal memory combined packaging capacity is small, the substrate utilization rate is low, the packaging cost is high, and the like.
Disclosure of Invention
Embodiments of the present invention provide a package structure and an electronic device, which are used to improve the area utilization of a package substrate and the memory combined package capacity, reduce the size of the package structure, and reduce the package cost.
To solve the above problem, an embodiment of the present invention provides a package structure, including: a package substrate including a connection terminal; the plurality of chips are sequentially stacked on the packaging substrate to form a chip stacking structure; the chip stacking structure exposes the connecting end, each chip comprises a chip bonding pad, and the chip bonding pad of each chip in the chip stacking structure is exposed; the first bonding wire structure is used for realizing the connection between the chip bonding pad and the connecting end; and the second bonding wire structure is used for realizing the connection between the chip bonding pads.
Optionally, the connecting end includes a substrate pad; the first wire bond structure comprising: a first routing for connecting the substrate bonding pad and the chip bonding pad located in the chip stacking structure and closest to the package substrate; the second wire bond structure comprising: and the second routing wires are respectively used for realizing the electric connection between the chip bonding pads of the adjacent chips in the chip stacking structure.
Optionally, in a direction away from the chip stacking structure, the connecting end includes a plurality of spaced substrate pads; the chip stacking structure comprises a plurality of stacking structures, each stacking structure comprises a plurality of chips, and the types of the chips in the different stacking structures are different; the first wire bond structure comprising: the third routing wires are respectively used for connecting the chip bonding pad closest to the packaging substrate in each stacking structure with the corresponding substrate bonding pad; the second wire bonding structure includes: and the fourth routing wires are respectively used for realizing the connection between the chip bonding pads in the adjacent chips in the stacked structures.
Optionally, the number of the stacked structures is the same as the number of the substrate pads.
Optionally, in a direction away from the chip stacking structure, the substrate pad sequentially includes: a first pad and a second pad; the chip stacking structure comprises a first stacking structure and a second stacking structure positioned on the first stacking structure, the first stacking structure comprises two first type chips, and the second stacking structure comprises two second type chips; the number of the third routing lines is two, one third routing line is used for connecting the chip bonding pad closest to the packaging substrate in the first stacking structure with the first bonding pad, and the other third routing line is used for connecting the chip bonding pad closest to the packaging substrate in the second stacking structure with the second bonding pad; the number of the fourth routing is two, one of the fourth routing is used for realizing the connection between the chip bonding pads in the adjacent first type chip, and the other of the fourth routing is used for realizing the connection between the chip bonding pads in the adjacent second type chip.
Optionally, the chip pad includes: the chip bonding pad comprises a first chip power bonding pad and a second chip power bonding pad which are spaced, wherein in the projection of the chip bonding pad on the packaging substrate, the first chip power bonding pad is closest to the connecting end, and in the projection, the first chip power bonding pads of adjacent chips are adjacent, and the second chip power bonding pads of adjacent chips are adjacent; the chip stacking structure comprises a plurality of stacking structures, each stacking structure comprises a plurality of chips, and the types of the chips in the different stacking structures are different; in the stacked structure, the chip closest to the packaging substrate is a lower chip, and the chip farthest from the packaging substrate is an upper chip; the first wire bond structure comprising: the fifth routing wires are respectively used for connecting the first chip power supply bonding pad of each chip with the connecting end; the second wire bond structure comprising: the sixth routing is used for realizing the connection of the power supply bonding pads of the second chips adjacent to the chips in each stacked structure; and one or more seventh routing wires for connecting and connecting the upper chip of the stacked structure with the first chip power supply bonding pad of the lower chip of the other stacked structure above the stacked structure.
Optionally, the chip stacking structure includes a first stacking structure and a second stacking structure located on the first stacking structure, the first stacking structure includes a first chip and a second chip sequentially far away from the package substrate, and the second stacking structure includes a third chip and a fourth chip sequentially far away from the package substrate; the connection end includes: the first substrate power supply bonding pad, the second substrate power supply bonding pad and the third substrate power supply bonding pad are sequentially arranged at intervals in the direction away from the chip stacking structure; the number of the fifth routing is four, the first substrate power supply bonding pad is connected with the first chip power supply bonding pad of the first chip, the second substrate power supply bonding pad is connected with the first chip power supply bonding pad of the second chip, the second substrate power supply bonding pad is connected with the first chip power supply bonding pad of the third chip, and the third substrate power supply bonding pad is connected with the first chip power supply bonding pad of the fourth chip; the number of the sixth routing is two, the second chip power supply bonding pad of the first chip is connected with the second chip power supply bonding pad of the second chip, and the second chip power supply bonding pad of the third chip is connected with the second chip power supply bonding pad of the fourth chip; and the number of the seventh routing is one, and the first chip power supply bonding pad of the second chip is connected with the first chip power supply bonding pad of the third chip.
Optionally, the chip pad includes: the chip bonding pad comprises a first chip power bonding pad and a second chip power bonding pad which are spaced, wherein in the projection of the chip bonding pad on the packaging substrate, the first chip power bonding pad is closest to the connecting end, and in the projection, the first chip power bonding pads of adjacent chips are adjacent, and the second chip power bonding pads of adjacent chips are adjacent; the chip stacking structure comprises a plurality of stacking structures, each stacking structure comprises a plurality of chips, and the types of the chips in the different stacking structures are different; in the stacked structure, the chip closest to the packaging substrate is a lower chip, and the chip farthest from the packaging substrate is an upper chip; the first wire bond structure comprising: a plurality of eighth routing wires, respectively used for connecting the first chip power supply bonding pad of the chip closest to the packaging substrate and farthest from the packaging substrate with the connecting end; the second wire bond structure comprising: the plurality of ninth routing is used for realizing the connection of the power supply bonding pads of the second chips adjacent to the chips in each stacked structure; and one or more tenth routing wires for connecting and connecting the upper chip of the stacked structure with the first chip power supply bonding pad of the lower chip of the other stacked structure above the stacked structure.
Optionally, the chip stacking structure includes a first stacking structure and a second stacking structure located on the first stacking structure, the first stacking structure includes a first chip and a second chip sequentially far away from the package substrate, and the second stacking structure includes a third chip and a fourth chip sequentially far away from the package substrate; the connection end includes: the fourth substrate power supply bonding pads and the fifth substrate power supply bonding pads are arranged at intervals; the number of the eighth routing is two, the fourth substrate power supply bonding pad is connected with the first chip power supply bonding pad of the first chip, and the fifth substrate power supply bonding pad is connected with the first chip power supply bonding pad of the fourth chip; the number of the ninth routing is two, the second chip power supply bonding pad of the first chip is connected with the second chip power supply bonding pad of the second chip, and the second chip power supply bonding pad of the third chip is connected with the second chip power supply bonding pad of the fourth chip; and the number of the tenth routing is one, and the first chip power supply bonding pad of the second chip is connected with the first chip power supply bonding pad of the third chip.
Optionally, the chip farthest from the package substrate in the chip stacking structure is a top chip; the package structure further includes: the side bonding pad is positioned on the packaging substrate and positioned on one side, away from the connecting end, of the chip stacking structure; the rewiring bonding pad is positioned on the top chip and is close to the side bonding pad relative to the chip bonding pad of the top chip; the rewiring structure is positioned on the top chip and is used for realizing the connection of the rewiring bonding pad and one or two of the first chip power bonding pad or the second chip power bonding pad; the package structure further includes: and a third bonding wire structure for connecting the side pad with the rewiring pad.
Optionally, the package structure further includes: and the control chip is positioned on the packaging substrate, is spaced from the chip stacking structure and is electrically connected with the chip stacking structure.
Optionally, the package substrate includes a circuit layer, and the circuit layer is connected to the connection end; the control chip is electrically connected with the circuit layer in a wire bonding mode or a crystal covering mode.
Optionally, in two adjacent chips in the chip stacking structure, a distance between a chip pad on a chip close to the package substrate and a chip sidewall far away from the package substrate is greater than 200 micrometers and less than 1200 micrometers.
Optionally, the chip pad is located on a surface of the chip facing away from the package substrate.
Optionally, the chip pad is located at one end of the chip close to the connecting end.
Optionally, the package structure includes: and the bonding layers are positioned between the packaging substrate and the chip closest to the packaging substrate and between the adjacent chips.
Optionally, the chip comprises a memory chip.
Correspondingly, the embodiment of the invention also provides electronic equipment comprising the packaging structure.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
an embodiment of the present invention provides a package structure, where the package structure includes: a package substrate including a connection terminal; the plurality of chips are sequentially stacked on the packaging substrate to form a chip stacking structure; the chip stacking structure exposes the connecting ends, each chip comprises a chip bonding pad, and the chip bonding pad of each chip in the chip stacking structure is exposed; the first bonding wire structure is used for realizing connection between the chip bonding pad and the connecting end; and the second bonding wire structure is used for realizing the connection between the chip bonding pads. Compared with the situation that the plurality of chips are located on the packaging substrate side by side, the plurality of chips are sequentially stacked on the packaging substrate and occupy the space in the normal direction of the packaging substrate, so that the plurality of chips do not need to occupy too much plane area of the packaging substrate, the surface area utilization rate and the internal memory combined packaging capacity of the packaging substrate are improved, the size of the packaging substrate is favorably reduced, the size of a packaging structure is further reduced, and the packaging cost is reduced; in the embodiment of the invention, a plurality of chips are stacked on the packaging substrate, and the chip stacking structure is connected with the packaging substrate through the first bonding wire structure and the second bonding wire structure, so that the first bonding wire structure and the second bonding wire structure are distributed in the normal direction of the surface of the packaging substrate, the plane area of the packaging substrate occupied by the corresponding first bonding wire structure and the second bonding wire structure is smaller, the surface area utilization rate of the packaging substrate is improved, the size of the packaging substrate is favorably reduced, and the size of the packaging structure is further reduced.
Drawings
FIG. 1 is a schematic structural diagram of a first embodiment of a package structure of the present invention;
FIG. 2 is a diagram of a second embodiment of a package structure according to the present invention;
FIG. 3 is a top view of a second embodiment of the package structure of FIG. 2;
FIG. 4 is a schematic structural diagram of a third embodiment of a package structure of the present invention;
FIG. 5 is a top view of a third embodiment of the package structure of FIG. 4;
FIG. 6 is a schematic structural diagram of a fourth embodiment of a package structure of the present invention;
fig. 7 is a schematic top view of the package structure of fig. 6.
Detailed Description
As is known in the art, conventional package structures have problems. Specifically, the conventional multi-chip Package structure adopts a side-by-side multi-chip Package structure, that is, two or more chips are mounted on the same substrate side by side, and because the substrate is enlarged with the increase of the number of the chips, the conventional System In a Package (SIP) has a large volume, a small internal memory combined Package capacity, a low substrate utilization rate, a high Package cost and the like.
In order to solve the technical problem, an embodiment of the present invention provides a package structure, including: a package substrate including a connection terminal; the plurality of chips are sequentially stacked on the packaging substrate to form a chip stacking structure; the chip stacking structure exposes the connecting end, each chip comprises a chip bonding pad, and the chip bonding pad of each chip in the chip stacking structure is exposed; the first bonding wire structure is used for realizing connection between the chip bonding pad and the connecting end; and the second bonding wire structure is used for realizing the connection between the chip bonding pads.
Compared with the situation that the plurality of chips are located on the packaging substrate side by side, in the embodiment of the invention, the plurality of chips are sequentially stacked on the packaging substrate, and occupy the space in the normal direction of the packaging substrate, so that the plurality of chips do not need to occupy too much plane area of the packaging substrate, the surface area utilization rate of the packaging substrate is improved, the size of the packaging substrate is favorably reduced, the size of a packaging structure is further reduced, and the packaging cost is reduced; in the embodiment of the invention, a plurality of chips are stacked on the packaging substrate, the chip stacking structure is connected with the packaging substrate through the first welding wire structure and the second welding wire structure, and the plane area of the packaging substrate occupied by the corresponding first welding wire structure and the second welding wire structure is smaller, so that the surface area utilization rate of the packaging substrate is improved, the size of the packaging substrate is favorably reduced, and the size of the packaging structure is further reduced.
Fig. 1 is a schematic structural diagram of a package structure according to a first embodiment of the invention.
The package structure includes: a package Substrate 10 (Substrate) including a connection terminal 12; a plurality of chips 11 sequentially stacked on the package substrate 10 to form a chip stack structure (not shown); the chip stacking structure exposes the connecting terminals 12, each chip 11 includes a chip pad 13, and the chip pad 13 of each chip 11 in the chip stacking structure is exposed; a first wire bond structure 14 (shown in solid lines in fig. 1) for making the connection of the die pad 13 to the connection terminal 12; a second wire bond structure 15 (shown in dashed lines in fig. 1) is used to make the connection between the die pads 13.
Compared with the case that the plurality of chips 11 are located on the package substrate 10 side by side, in this embodiment, the plurality of chips 11 are sequentially stacked on the package substrate 10, and the plurality of chips 11 occupy a space in a normal direction of the package substrate 10, so that the plurality of chips 11 do not need to occupy too much plane area of the package substrate 10, thereby improving the surface area utilization rate of the package substrate 10, facilitating reduction of the size of the package substrate 10, further reducing the volume of the package structure, and reducing the package cost; in this embodiment, a plurality of chips 11 are stacked on the package substrate 10, and the chip stacking structure is connected to the package substrate 10 through the first wire bonding structure 14 and the second wire bonding structure 15, so that the first wire bonding structure 14 and the second wire bonding structure 15 are distributed in a normal direction of a surface of the package substrate, and the first wire bonding structure 14 and the second wire bonding structure 15 occupy a smaller planar area of the package substrate 10, which improves a surface area utilization rate of the package substrate 10, facilitates reducing a size of the package substrate 10, and further reduces a volume of the package structure.
The package substrate 10 provides the chip 11 with electrical connection, protection, support, heat dissipation, and assembly functions, so as to achieve the purposes of multi-pin, package product volume reduction, electrical performance and heat dissipation improvement, and ultrahigh density or multi-chip modularization.
In this embodiment, the package substrate 10 is a Printed Circuit Board (PCB). Accordingly, the package substrate 10 includes a circuit layer (not shown).
In this embodiment, the package substrate 10 is rectangular. In other embodiments, the package substrate may also be a diamond, a triangle, or a pentagon.
As an example, the length of the package substrate 10 is 17.45mm, and the width of the package substrate is 16.8mm. In other embodiments, the package substrate may have other dimensions according to actual package requirements.
In this embodiment, the connecting terminal 12 is electrically connected to the circuit layer in the package substrate 10.
Specifically, the connection terminal 12 includes a substrate pad for electrically connecting a circuit layer of the package substrate 10 to other semiconductor devices, and the chip stacking structure exposes the substrate pad, so that the package substrate 10 is electrically connected to the chip pad 13 of the chip 11, and when the package structure works, the connection terminal is used for transmitting a control signal between the package substrate 10 and the chip stacking structure.
In this embodiment, the substrate Pad is a wire Pad (Bond Pad).
The chip 11 includes at least one of a memory chip, a CMOS image sensor Chip (CIS), a sensor module chip, a MEMS chip, and a filter chip.
In this embodiment, the chip 11 includes a Memory chip, and specifically, the chip 11 is a Fourth-Generation Double-Data-Rate Synchronous Dynamic Random Access Memory (DDR 4 SDRAM), and the DDR4 has higher performance, larger DIMM capacity, stronger Data integrity, and lower energy consumption.
In other embodiments, the sensor module chip comprises at least one of a biosensor chip, a radio frequency sensing module chip, an infrared radiation sensing module chip, a visible light signal sensing module chip, an acoustic wave signal sensing module chip, and an electromagnetic wave signal sensing module chip; the filter chip comprises one or two of a surface acoustic wave resonator and a bulk acoustic wave resonator.
The MEMS chip comprises a thermopile sensor chip, and the thermopile sensor chip and the logic chip are integrated together to realize an infrared sensing function, such as temperature measurement. The MEMS chip also comprises a microphone sensor chip, and the microphone sensor chip and the logic chip are integrated together to realize the sound wave sensing function.
The filter chip includes: one or both of a Surface Acoustic Wave (SAW) resonator and a bulk acoustic wave (bulk acoustic wave) resonator, and in the case of the bulk acoustic wave resonator, may be a reflection array type bulk acoustic wave resonator (BAW-SMR), a diaphragm type thin film bulk acoustic wave (FBAR) resonator, or an air gap type thin film bulk acoustic wave resonator.
The chip stack structure includes a first chip 111, a second chip 112, a third chip 113 and a fourth chip 114 sequentially distant from the package substrate 10.
In this embodiment, according to the functional configuration of the package structure, when the package structure works, the first chip 111 and the third chip 113 are the first channel, the first chip 111 and the third chip 113 work simultaneously, the second chip 112 and the fourth chip 114 are the second channel, and the second chip 112 and the fourth chip 114 work simultaneously. In other embodiments, according to the functional configuration of the package structure, the chip stacking structure may further include a first chip, a second chip, and a third chip that are sequentially away from the package substrate, where the first chip and the third chip are first channels, and the second chip is a second channel.
The die pad 13 is used for electrically connecting the connecting terminal 12 through the first wire bonding structure 14, and electrically connecting the die pad 13 in the adjacent die 11 through the second wire bonding structure 15. The chip pads 13 are used to enable the transfer of control signals between the package substrate 10 and the chip stack structure, and between adjacent chips 11, when the package structure is in operation.
In this embodiment, the die pad 13 includes a wire pad (bond pad).
It should be noted that the chip pad 13 is located on a surface of the chip 11 away from the package substrate 10. The first wire bonding structure 14 is favorable for connecting the packaging substrate 10 with the bottommost chip bonding pad 13, the second wire bonding structure 15 is favorable for connecting the chip bonding pads 13 in the adjacent chips 11, and the arrangement rationality of the first wire bonding structure 14 and the second wire bonding structure 15 is improved.
Chip pad 13 is located the tip of chip 11 is on packaging substrate 10's normal direction, is favorable to making the chip 11 of keeping away from packaging substrate 10 expose and be close to chip pad 13 on packaging substrate 10's the chip, the electric connection between the chip 11 of the bottommost of being convenient for and packaging substrate 10 to and the electric connection between chip 11 and the chip 11, improve the rationality that chip 11 arranged among the packaging structure.
Specifically, the die pad 13 is located at one end of the die 11 close to the connecting terminal 12. The die pad 13 is located at one end of the die 11 close to the connecting end 12, which is beneficial to reducing the lengths of the first wire bonding structure 14 and the second wire bonding structure 15, and is beneficial to reducing the probability of overlapping between the first wire bonding structure 14 and the second wire bonding structure 15.
The package structure further includes: and a bonding layer 16 between the package substrate 10 and the chip 11 closest to the package substrate 10, and between the chip 11 and the chip 11.
The bonding layer 16 is used for bonding the package substrate 10 and the bottommost chip 11 together, and bonding the chip 11 and the chip 11 together.
In this embodiment, the bonding layer 16 is made of Die Attach Film (DAF). In other embodiments, the material of the bonding layer may also be a material that can be photoetched, and may be etched into a desired shape according to process requirements. Specifically, the materials of the lithographically bondable layer include: a film-like dry film or a liquid dry film. The elastic modulus of the dry film material is relatively low, the dry film material is easy to deform and cannot be damaged when being subjected to thermal stress, and the bonding stress between the packaging substrate and the chip and the bonding stress between the chip and the chip can be reduced. In other embodiments, the material of the bonding layer further comprises one or more of glass, a dielectric material, and a polymer material.
The first wire bond structure 14 includes: and the first routing is used for connecting the substrate bonding pad and the chip bonding pad 13 which is positioned in the chip stacking structure and is closest to the packaging substrate 10, and is used for realizing the electrical connection between the bottommost chip 11 and the packaging substrate 10.
The second wire bonding structure 15 includes: and the second routing wires are respectively used for realizing the electric connection between the chip bonding pads 13 of the adjacent chips 11 in the chip stacking structure.
When the packaging structure works, the substrate bonding pads are connected in series with the chip bonding pads 13 through the first bonding wire structure 14 and the second bonding wire structure 15, so as to realize the transmission of control signals between the chips 11 and the packaging substrate 10.
In this embodiment, the material of the bonding wire structure 15 includes: one or more of gold, copper and silver.
It should be noted that, in two adjacent chips 11 in the chip stack structure, a distance L (as shown in fig. 1) between a chip pad 13 on the chip 11 close to the package substrate 10 and a side wall of the chip 11 far from the package substrate 10 is neither too small nor too large. If the distance L is too small, in the process of forming the packaging structure and carrying out routing by adopting a packaging routing machine, the routing machine head is easy to touch the side wall of the chip 11 at the side part of the chip bonding pad 21, so that the normal routing movement of the routing machine head is hindered. If the distance is too large, the center of gravity of the chip 11 far away from the package substrate 10 is not likely to fall on the chip 11 at the bottom, so that the chip stacking structure is likely to collapse. In this embodiment, a distance L between a chip pad 13 on a chip 11 close to the package substrate 10 and a sidewall of the chip 11 far from the package substrate 10 is greater than 200 micrometers and less than 1200 micrometers.
The package structure further includes: and the control chip 1 is positioned on the packaging substrate 10, is spaced from the chip stacking structure and is electrically connected with the chip stacking structure and the control chip.
In this embodiment, the control chip 1 is electrically connected to the circuit layer in the package substrate 10 in a flip chip manner, or the control chip 1 is electrically connected to the circuit layer in the package substrate 10 in a wire bonding manner.
The control chip 1 is electrically connected with the plurality of chips 11 in the chip stacking structure through the circuit layer, the connecting end 12, the first wire bonding structure 14 and the second wire bonding structure 15, so that the plurality of chips 11 are controlled.
In this embodiment, the control chip 1 includes, but is not limited to, a power control chip, a frequency converter control chip, a touch screen control chip, a stepper motor control chip, a charging control chip, or a voltage reduction control chip.
Referring to fig. 2 and fig. 3, schematic structural diagrams of a package structure according to a second embodiment of the present invention are shown, and fig. 3 is a top view of fig. 2.
The same parts of this embodiment as the first embodiment are not described herein again, and the differences between this embodiment and the first embodiment are:
in a direction away from the chip stack, the connection terminals 22 include a plurality of spaced apart substrate pads; the chip stacking structure comprises a plurality of stacking structures, each stacking structure comprises a plurality of chips 21, and the types of the chips 21 in the different stacking structures are different; the first wire bond structure 24 includes: a plurality of third bonding wires 241 (solid lines in fig. 2) for connecting the chip pads 23 closest to the package substrate 20 in each stacked structure with the corresponding substrate pads, respectively; the second wire bonding structure 25 includes: a plurality of fourth bonding wires 251 (dashed lines in fig. 2) are respectively used for realizing the connection between the chip bonding pads 23 in the adjacent chips 21 in the stacked structures.
In this embodiment, a direction away from the chip stacking structure is taken as a first direction (e.g., x in fig. 3), a direction perpendicular to the first direction on the package substrate 20 is taken as a second direction (e.g., y in fig. 3), and in the direction away from the chip stacking structure, specifically, in the first direction, the connection terminal 22 includes a plurality of spaced substrate pads, and compared with a case where the substrate pads of the connection terminal 22 are distributed in the same second direction, the size of the package substrate 20 occupied by the connection terminal 22 in the second direction can be reduced, the surface area utilization rate of the package substrate 20 is improved, and the volume of the package structure is reduced.
In this embodiment, the number of the stacked structures is the same as the number of the substrate pads, that is, the number of the chip types is the same as the number of the substrate pads. One substrate pad is electrically connected to only the die pad 23 of the same type of die 21 through the first wire bonding structure 24 and the second wire bonding structure 25. So set up, be favorable to optimizing the distribution of connecting the first bonding wire structure 24 and the second bonding wire structure 25 of different type chips 21, can avoid connecting the first bonding wire structure 24 and the second bonding wire structure 25 of different type chips 21 and overlap on packaging substrate 20 surface normal, improve packaging substrate layout's rationality.
Specifically, in a direction away from the chip stacking structure, the substrate pad sequentially includes: a first pad 221 and a second pad 222; the chip stacking structure includes a first stacking structure including two first core pieces 211 and a second stacking structure including two second core pieces 212 on the first stacking structure.
The number of the third wire bonds 241 is two, one of the third wire bonds 241 is used for connecting the chip pad 23 closest to the package substrate 20 in the first stacked structure with the first pad 221, and the other of the third wire bonds 241 is used for connecting the chip pad 23 closest to the package substrate 20 in the second stacked structure with the second pad 222.
The number of the fourth routing 251 is two, one fourth routing 251 is used for realizing the connection between the chip bonding pads 23 in the adjacent first type chips, and the other fourth routing 251 is used for realizing the connection between the chip bonding pads 23 in the adjacent second type chips.
In this embodiment, one third wire 241 is used to connect the first pad 221 with the bottommost die pad 23 in the first stacked structure, and the other third wire 241 is used to connect the second pad 222 with the bottommost die pad 23 in the second stacked structure, where the second pad 222 is far away from the die stacked structure compared to the first pad 221, and the second stacked structure is located above the first stacked structure, so that the third wire 241 connected to the die pad 23 in the second stacked structure is located outside the third wire 241 connected to the die pad 23 in the first stacked structure, and the two third wires 241 are not easily overlapped, thereby reducing the risk of short circuit between the two third wires 241; because the second stacked structure is located the top of first stacked structure, consequently, connect the fourth routing 251 of the chip pad 23 of two first type chips, can not appear the overlap with the fourth routing of the chip pad 23 of connecting two second type chips, reduce the risk of short circuit between two fourth routing 251, so set up and to reduce the risk of short circuit between third routing 241 and the fourth routing 251, improve the rationality of bonding wire structure 25 overall arrangement among the packaging structure.
As an example, the package structure is used to transmit Data Signals (DQs). Specifically, the third routing 241 connected to the second pad 222 and the fourth routing 251 inside the second stacked structure enable the second type chip in the second stacked structure to transmit a data signal higher than 16 bit; the third wire 241 connected to the first pad 221 and the fourth wire 251 inside the first stacked structure enable the first chip in the first stacked structure to transmit data signals lower than 16 bit.
When the package structure is used for transmitting data signals, different types of chips are connected in parallel through the arrangement of the first bonding wire structure 24 and the second bonding wire structure 25. For example, different types of chips do not operate simultaneously when the package structure is operating. Specifically, the chip types are two, the first type chip and the second type chip are connected in parallel, when the first type chip works, the second type chip stops working, and when the second type chip works, the first type chip stops working.
Referring to fig. 4 and 5, schematic structural diagrams of a package structure according to a third embodiment of the invention are shown, and fig. 5 is a top view of fig. 4.
The same parts of this embodiment as those of the first embodiment are not described herein again, and the differences between this embodiment and the first embodiment are:
the chip pad 33 includes: a first chip power pad 331 and a second chip power pad 332 spaced apart from each other, in a projection of the chip pad 33 on the package substrate 30, the first chip power pad 331 is closest to the connection terminal 32, and in the projection, the first chip power pad 331 of the adjacent chip 31 is adjacent, and the second chip power pad 332 of the adjacent chip 31 is adjacent; the chip stacking structure comprises a plurality of stacking structures, each stacking structure comprises a plurality of chips 31, and the types of the chips 31 in the different stacking structures are different; in the stacked structure, the chip 31 closest to the package substrate 30 is a lower chip, and the chip farthest from the package substrate 30 is an upper chip; the first wire bond structure 34 includes: a plurality of fifth wire bonds 341, respectively used for connecting the first chip power pads 331 of the chips 31 with the connecting terminals 32; the second wire bonding structure 35 includes: a plurality of sixth bonding wires 351, configured to connect the second chip power pads 332 of the adjacent chips 31 in each stacked structure; and one or more seventh wire bonds 352 for connecting the upper chip of the stacked structure with the first chip power pad 331 of the lower chip of another stacked structure above the stacked structure.
As an example, the first wire bonding structure 34 and the second wire bonding structure 35 serve as paths through which Power (PG) reflow between the package substrate 30 and the chip stacking structure respectively flows.
In the package structure provided in this embodiment, the fifth wire bonding 341, the sixth wire bonding 351, and the seventh wire bonding 352 form respective paths through which power reflows between the package substrate 30 and the chip stacking structure flow.
In this embodiment, a direction away from the chip stacking structure is taken as a first direction (x direction in fig. 5), a direction perpendicular to the first direction on the package substrate 30 is taken as a second direction (y direction in fig. 5), and in the direction away from the chip stacking structure, specifically, the first direction, the connection terminal 32 includes a plurality of spaced substrate pads, and compared with a case where the substrate pads of the connection terminal 32 are distributed in the same second direction, the size of the package substrate 30 occupied by the connection terminal 32 in the second direction can be reduced, the surface area utilization rate of the package substrate 30 is improved, and the volume of the package structure is reduced.
In this embodiment, the chip stacking structure includes a first stacking structure including a first chip 311 and a second chip 312 sequentially distant from the package substrate 30, and a second stacking structure located on the first stacking structure including a third chip 313 and a fourth chip 314 sequentially distant from the package substrate 30.
The connection end 32 includes: and the first substrate power supply pad 321, the second substrate power supply pad 322 and the third substrate power supply pad 323 are sequentially arranged at intervals in the direction away from the chip stacking structure.
The number of the fifth routing 341 is four, and the first substrate power supply pad 321 is connected to the first chip power supply pad 331 of the first chip 311, the second substrate power supply pad 322 is connected to the first chip power supply pad 331 of the second chip 312, the second substrate power supply pad 322 is connected to the first chip power supply pad 331 of the third chip 313, and the third substrate power supply pad 323 is connected to the first chip power supply pad 331 of the fourth chip 314.
It should be noted that the two fifth bonding wires 341 connected to the second substrate power supply pad 322 electrically connect the second chip 312 and the third chip 313 to the package substrate 30, and also electrically connect the second chip 312 and the third chip 313.
The number of the sixth wire bonds 351 is two, and the second chip power pad 332 of the first chip 311 is connected to the second chip power pad 332 of the second chip 312, and the second chip power pad 332 of the third chip 313 is connected to the second chip power pad 332 of the fourth chip 314.
The number of the seventh wire bonds 352 is one, and the first chip power pad 331 of the second chip 312 is connected to the first chip power pad 331 of the third chip 313. The seventh wire bonding 352 increases a communication path between the second chip 312 and the third chip 313, which is beneficial to reducing a voltage drop between the second chip 312 and the third chip 313, so that a resistance between the second chip 312 and the third chip 313 is small.
In this embodiment, the second chip 312 is located on the first chip 311, the third chip 313 is located on the second chip 312, and the fourth chip 314 is located on the third chip 313. Therefore, the fifth wire bonding 341 connected with the second chip 312 is located outside the fifth wire bonding 341 connected with the first chip 311, the fifth wire bonding 341 connected with the third chip 313 is located outside the fifth wire bonding 341 connected with the second chip 312, and the fifth wire bonding 341 connected with the fourth chip 314 is located outside the fifth wire bonding 341 connected with the third chip 313, and the fifth wire bonding 341 are not easily overlapped, so that the risk of short circuit among different fifth wire bonding 341 is reduced, and the reasonability of the layout of the welding wire structure 35 in the packaging structure is improved.
In this embodiment, the sixth wire 351 is used for realizing the connection between the second chip power pads 332 in the same type of chips, so that the sixth wire 351 connecting the first chip 311 and the second chip power pad 332 in the second chip 312 is closer to the package substrate 30 than the fifth wire 341 connecting the second chip 312, and similarly, the sixth wire 351 connecting the third chip 313 and the second chip power pad 332 in the fourth chip 314 is closer to the package substrate 30 than the fifth wire 341 connecting the fourth chip 314, so that the sixth wire 351 is not easily overlapped with the fifth wire 341, the risk of short circuit between the fifth wire 341 and the sixth wire 351 is reduced, and the rationality of the layout of the wire bonding structure 35 in the package structure is improved.
It should be noted that the seventh wire 352 connecting the first chip power pad 331 of the second chip 312 and the first chip power pad 331 of the third chip 313 is located outside the fifth wire 341 connecting the second chip and inside the fifth wire 341 connecting the third chip 313, so that the seventh wire 352 is not easily overlapped with the fifth wire 341 and the sixth wire 351, the risk of short circuit between the seventh wire 352 and the fifth wire 341 and the sixth wire 351 is reduced, and the rationality of the wire structure layout in the package structure is improved.
The chip farthest from the package substrate 30 in the chip stacking structure is the top chip; the package structure further includes: a side pad 37 located on the package substrate 30, wherein the side pad 37 is located on a side of the chip stacking structure facing away from the connecting terminal 32; rewiring pads on the top chip, close to the side pads 37 with respect to the chip pads of the top chip; a rewiring structure on the top chip for connecting the rewiring pad to one or both of the first chip power pad 331 or the second chip power pad 332; the package structure further includes: a third wire bonding structure 353 for connecting the side pad 37 and the rewiring pad.
Rewiring structure with one or two among first chip power pad 331 and the second chip power pad 332 are connected, rewiring structure with rewiring pad 36 is connected, because rewiring pad 36 is located the top of top chip, side pad 37 is located the chip stack structure deviates from one side of link 32, thereby third bonding wire structure 353 and first bonding wire structure 34 and second bonding wire structure 35 are located respectively the both sides of chip stack structure have avoided third bonding wire structure 353 and first bonding wire structure 34 and second bonding wire structure 35 overlap, have reduced the risk of third bonding wire structure 353 and first bonding wire structure 34 and second bonding wire structure 35 short circuit, improve the rationality of bonding wire structure overall arrangement among the packaging structure.
Referring to fig. 6 and 7, a structure of a package structure according to a fourth embodiment of the invention is shown, and fig. 7 is a top view of fig. 6.
The same parts of this embodiment as the first embodiment are not described herein again, and the differences between this embodiment and the first embodiment are:
the chip pad 43 includes: a first chip power pad 431 and a second chip power pad 432 which are spaced apart, wherein in the projection of the chip pad 43 on the package substrate 40, the first chip power pad 431 is closest to the connection terminal 42, and in the projection, the first chip power pad 431 of the adjacent chip 41 is adjacent, and the second chip power pad 432 of the adjacent chip 41 is adjacent; the chip stacking structure comprises a plurality of stacking structures, each stacking structure comprises a plurality of chips 41, and the types of the chips 41 in the different stacking structures are different; in the stacked structure, the chip 41 closest to the package substrate 40 is a lower chip, and the chip farthest from the package substrate 40 is an upper chip; the first wire bond structure 44 includes: a plurality of eighth bonding wires 441 respectively used for connecting the connection end 42 closest to the package substrate 40 and the connection end 42 farthest from the package substrate 40; the second wire bonding structure 45 includes: a plurality of ninth wire bonds 451, configured to connect the second chip power pads 432 of the adjacent chips 41 in each of the stacked structures; and one or more tenth wire bonds 452 for connecting the upper chip of the stacked structure with the first chip power pad 431 of the lower chip of another stacked structure above the stacked structure.
As an example, the first wire bond structure 44 and the second wire bond structure 45 serve as respective paths through which Power (PG) reflows between the package substrate 40 and the chip stack structure.
In the package structure provided in this embodiment, the eighth wire bonding 441, the ninth wire bonding 451, and the tenth wire bonding 452 form respective paths through which power supply reflows between the package substrate 40 and the chip stacking structure flow.
The chip stack structure includes a first stack structure including a first chip 411 and a second chip 412 sequentially distant from the package substrate 40, and a second stack structure on the first stack structure including a third chip 413 and a fourth chip 414 sequentially distant from the package substrate 40.
The connection end 42 includes: fourth substrate power supply pads 421 and fifth substrate power supply pads 422 arranged at intervals.
The number of the eighth routing 441 is two, and the fourth substrate power pad 421 is connected to the first chip power pad 431 of the first chip 411, and the fifth substrate power pad 422 is connected to the first chip power pad 431 of the fourth chip 414, respectively.
The number of the ninth wire bonds 451 is two, and the second chip power pad 432 of the first chip 411 is connected to the second chip power pad 432 of the second chip 412, and the second chip power pad 432 of the third chip 413 is connected to the second chip power pad 432 of the fourth chip 414.
The number of the tenth wire bonds 452 is one, and the first chip power supply pad 431 of the second chip 412 is connected to the first chip power supply pad 431 of the third chip 413.
In this embodiment, a second chip 412 is located on the first chip 411, a third chip 413 is located on the second chip 412, and a fourth chip 414 is located on the third chip 413. Therefore, the eighth routing 441 connected with the fourth chip 414 is located outside the eighth routing 441 connected with the first chip 411, and the eighth routing 441 are not easily overlapped, so that the risk of short circuit among different eighth routing 441 is reduced, and the rationality of the layout of the bonding wire structure 45 in the packaging structure is improved.
In this embodiment, the ninth wire 451 is used to realize the connection between the second chip power pads 432 in the same type of chips, so that the ninth wire 451 connecting the second chip power pads 432 in the first chip 411 and the second chip 412 is farther away from the package substrate 40 than the eighth wire 441 connecting the first chip 412, and similarly, the ninth wire 451 connecting the second chip power pads 432 in the third chip 413 and the fourth chip 414 is closer to the package substrate 40 than the eighth wire 441 connecting the fourth chip 414, so that the ninth wire 451 is not easily overlapped with the eighth wire 441, thereby reducing the risk of short circuit between the eighth wire 441 and the ninth wire 451, and improving the rationality of the layout of the wire structure 45 in the package structure.
It should be noted that the tenth wire 452 connecting the first chip power pad 431 of the second chip 412 and the first chip power pad 431 of the third chip 413 is located outside the two eighth wires 441, and the tenth wire 452 is located outside the eighth wire 441 connected to the first chip 412 and inside the eighth wire 441 connected to the fourth chip 414, so that the tenth wire 452 is not easily overlapped with the eighth wire 441 and the ninth wire 451, thereby reducing the risk of short circuit between the tenth wire 452 and the eighth wire 441 and the ninth wire 451, and improving the rationality of the layout of the bonding wire structure in the package structure.
The chip farthest from the package substrate 40 in the chip stacking structure is the top chip; the package structure further includes: side pads 47 on the package substrate 40, wherein the side pads 47 are located on a side of the chip stacking structure facing away from the connecting terminals 42; rewiring pads on the top chip, close to the side pads 47 with respect to the chip pads of the top chip; a rewiring structure on the top chip for connecting the rewiring pad to one or both of the first chip power supply pad 431 or the second chip power supply pad 432; the package structure further includes: and a third wire bonding structure 453 for connecting the side pad 47 with the re-wiring pad.
Rewiring structure with one or two in first chip power pad 431 and second chip power pad 432 are connected, rewiring structure with rewiring pad 46 is connected, because rewiring pad 46 is located the top of top chip, side pad 47 is located the chip stack structure deviates from one side of link 42, thereby third bonding wire structure 453 is located respectively with first bonding wire structure 44 and second bonding wire structure 45 the both sides of chip stack structure, has avoided third bonding wire structure 453 and first bonding wire structure 44 and second bonding wire structure 45 overlap, has reduced the risk of third bonding wire structure 453 with first bonding wire structure 44 and second bonding wire structure 45 short circuit, improves the rationality of bonding wire structure layout in the packaging structure.
Correspondingly, the embodiment of the invention also provides electronic equipment, and the electronic equipment comprises the packaging structure.
The packaging structure has small volume and low packaging manufacturing cost, so that the electronic equipment can meet the miniaturization trend and the cost of the electronic equipment is reduced.
The electronic equipment is a set top box, a television, a projector or a mobile phone.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (18)

1. A package structure, comprising:
a package substrate including a connection terminal;
a plurality of chips stacked on the package substrate in sequence to form a chip stacking structure; the chip stacking structure exposes the connecting end, each chip comprises a chip bonding pad, and the chip bonding pad of each chip in the chip stacking structure is exposed;
the first bonding wire structure is used for realizing the connection between the chip bonding pad and the connecting end;
and the second bonding wire structure is used for realizing the connection between the chip bonding pads.
2. The package structure of claim 1, wherein the tab includes a substrate pad; the first wire bonding structure includes: a first routing for connecting the substrate bonding pad and the chip bonding pad located in the chip stacking structure and closest to the package substrate;
the second wire bonding structure includes: and the second routing wires are respectively used for realizing the electric connection between the chip bonding pads of the adjacent chips in the chip stacking structure.
3. The package structure of claim 1, wherein the terminals comprise a plurality of spaced apart substrate pads in a direction away from the chip stack;
the chip stacking structure comprises a plurality of stacking structures, each stacking structure comprises a plurality of chips, and the types of the chips in different stacking structures are different;
the first wire bonding structure includes: the third routing wires are respectively used for connecting the chip bonding pad closest to the packaging substrate in each stacking structure with the corresponding substrate bonding pad;
the second wire bond structure comprising: and the fourth routing is respectively used for realizing the connection between the chip bonding pads in the adjacent chips in the stacked structures.
4. The package structure of claim 3, wherein a number of the stack structures is the same as a number of the substrate pads.
5. The package structure according to claim 3 or 4, wherein the substrate pads comprise, in order in a direction away from the chip stack structure: a first pad and a second pad;
the chip stacking structure comprises a first stacking structure and a second stacking structure positioned on the first stacking structure, the first stacking structure comprises two first type chips, and the second stacking structure comprises two second type chips;
the number of the third routing is two, one third routing is used for connecting the chip bonding pad closest to the packaging substrate in the first stacking structure with the first bonding pad, and the other third routing is used for connecting the chip bonding pad closest to the packaging substrate in the second stacking structure with the second bonding pad;
the number of the fourth routing is two, one of the fourth routing is used for realizing the connection between the chip bonding pads in the adjacent first type chip, and the other of the fourth routing is used for realizing the connection between the chip bonding pads in the adjacent second type chip.
6. The package structure of claim 1, wherein the die pad comprises: the chip bonding pad comprises a first chip power bonding pad and a second chip power bonding pad which are spaced, wherein in the projection of the chip bonding pad on the packaging substrate, the first chip power bonding pad is closest to the connecting end, and in the projection, the first chip power bonding pads of adjacent chips are adjacent, and the second chip power bonding pads of adjacent chips are adjacent;
the chip stacking structure comprises a plurality of stacking structures, each stacking structure comprises a plurality of chips, and the types of the chips in the different stacking structures are different; in the stacked structure, the chip closest to the packaging substrate is a lower chip, and the chip farthest from the packaging substrate is an upper chip;
the first wire bond structure comprising: the fifth routing wires are respectively used for connecting the first chip power supply bonding pad of each chip with the connecting end;
the second wire bonding structure includes: the sixth routing is used for realizing connection of the second chip power supply bonding pads of the adjacent chips in each stacking structure; and one or more seventh routing wires for connecting and connecting the upper chip of the stacked structure with the first chip power supply bonding pad of the lower chip of the other stacked structure above the stacked structure.
7. The package structure of claim 6, wherein the chip stack structure comprises a first stack structure and a second stack structure on the first stack structure, the first stack structure comprising a first chip and a second chip sequentially distant from the package substrate, the second stack structure comprising a third chip and a fourth chip sequentially distant from the package substrate;
the connection end includes: the first substrate power supply bonding pad, the second substrate power supply bonding pad and the third substrate power supply bonding pad are sequentially arranged at intervals in the direction away from the chip stacking structure;
the number of the fifth routing is four, the first substrate power supply bonding pad is connected with the first chip power supply bonding pad of the first chip, the second substrate power supply bonding pad is connected with the first chip power supply bonding pad of the second chip, the second substrate power supply bonding pad is connected with the first chip power supply bonding pad of the third chip, and the third substrate power supply bonding pad is connected with the first chip power supply bonding pad of the fourth chip;
the number of the sixth routing wires is two, the second chip power supply bonding pad of the first chip is connected with the second chip power supply bonding pad of the second chip, and the second chip power supply bonding pad of the third chip is connected with the second chip power supply bonding pad of the fourth chip;
and the number of the seventh routing is one, and the first chip power supply bonding pad of the second chip is connected with the first chip power supply bonding pad of the third chip.
8. The package structure of claim 1, wherein the die pad comprises: the chip bonding pad comprises a first chip power bonding pad and a second chip power bonding pad which are spaced, wherein in the projection of the chip bonding pad on the packaging substrate, the first chip power bonding pad is closest to the connecting end, and in the projection, the first chip power bonding pads of adjacent chips are adjacent, and the second chip power bonding pads of adjacent chips are adjacent;
the chip stacking structure comprises a plurality of stacking structures, each stacking structure comprises a plurality of chips, and the types of the chips in the different stacking structures are different; in the stacked structure, the chip closest to the packaging substrate is a lower chip, and the chip farthest from the packaging substrate is an upper chip;
the first wire bonding structure includes: a plurality of eighth routing wires, respectively used for connecting the first chip power supply bonding pad of the chip closest to the packaging substrate and farthest from the packaging substrate with the connecting end;
the second wire bonding structure includes: the plurality of ninth routing is used for realizing the connection of the power supply bonding pads of the second chips adjacent to the chips in each stacked structure; and one or more tenth routing wires for connecting and connecting the upper chip of the stacked structure with the first chip power supply bonding pad of the lower chip of the other stacked structure above the stacked structure.
9. The package structure of claim 8, wherein the chip stack structure comprises a first stack structure and a second stack structure on the first stack structure, the first stack structure comprising a first chip and a second chip sequentially distant from the package substrate, the second stack structure comprising a third chip and a fourth chip sequentially distant from the package substrate;
the connection end includes: the fourth substrate power supply bonding pads and the fifth substrate power supply bonding pads are arranged at intervals;
the number of the eighth routing is two, the fourth substrate power supply bonding pad is connected with the first chip power supply bonding pad of the first chip, and the fifth substrate power supply bonding pad is connected with the first chip power supply bonding pad of the fourth chip;
the number of the ninth routing is two, and the second chip power supply bonding pad of the first chip is connected with the second chip power supply bonding pad of the second chip, and the second chip power supply bonding pad of the third chip is connected with the second chip power supply bonding pad of the fourth chip;
and the number of the tenth routing is one, and the first chip power supply bonding pad of the second chip is connected with the first chip power supply bonding pad of the third chip.
10. The package structure of any one of claims 6 to 9, wherein a chip in the chip stack structure farthest from the package substrate is a top chip;
the package structure further includes:
the side bonding pad is positioned on the packaging substrate and positioned on one side, away from the connecting end, of the chip stacking structure;
the rewiring bonding pad is positioned on the top chip and is close to the side bonding pad relative to the chip bonding pad of the top chip;
the rewiring structure is positioned on the top chip and is used for realizing the connection of the rewiring bonding pad and one or two of the first chip power supply bonding pad or the second chip power supply bonding pad;
the package structure further includes: and a third bonding wire structure for connecting the side pad with the rewiring pad.
11. The package structure of claim 1, wherein the package structure further comprises: and the control chip is positioned on the packaging substrate, is spaced from the chip stacking structure and is electrically connected with the chip stacking structure.
12. The package structure according to claim 11, wherein the package substrate includes a wiring layer, the wiring layer being connected to the connection terminals;
the control chip is electrically connected with the circuit layer in a wire bonding mode or a crystal covering mode.
13. The package structure of claim 1, wherein in two adjacent chips in the chip stack structure, a distance between a chip pad on a chip close to the package substrate and a side wall of the chip far from the package substrate is greater than 200 microns and less than 1200 microns.
14. The package structure of claim 1, 2, 3, 6, or 8, wherein the die pad is located on a surface of the die facing away from the package substrate.
15. The package structure of claim 1, 2, 3, 6 or 8, wherein the die pad is located at an end of the die proximate to the connection terminal.
16. The package structure of claim 1, wherein the package structure comprises: and the bonding layers are positioned between the packaging substrate and the chip closest to the packaging substrate and between the adjacent chips.
17. The package structure of claim 1, wherein the chip comprises a memory chip.
18. An electronic device comprising the encapsulation structure according to any one of claims 1 to 17.
CN202110402099.8A 2021-04-14 2021-04-14 Packaging structure and electronic equipment Pending CN115206945A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110402099.8A CN115206945A (en) 2021-04-14 2021-04-14 Packaging structure and electronic equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110402099.8A CN115206945A (en) 2021-04-14 2021-04-14 Packaging structure and electronic equipment

Publications (1)

Publication Number Publication Date
CN115206945A true CN115206945A (en) 2022-10-18

Family

ID=83573731

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110402099.8A Pending CN115206945A (en) 2021-04-14 2021-04-14 Packaging structure and electronic equipment

Country Status (1)

Country Link
CN (1) CN115206945A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116153870A (en) * 2023-04-21 2023-05-23 江苏长晶浦联功率半导体有限公司 Stacked packaging structure and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116153870A (en) * 2023-04-21 2023-05-23 江苏长晶浦联功率半导体有限公司 Stacked packaging structure and manufacturing method thereof

Similar Documents

Publication Publication Date Title
US8664780B2 (en) Semiconductor package having plural semiconductor chips and method of forming the same
US8466564B2 (en) Enhanced stacked microelectronic assemblies with central contacts and improved ground or power distribution
US9412720B2 (en) Semiconductor package having supporting plate and method of forming the same
US6414384B1 (en) Package structure stacking chips on front surface and back surface of substrate
US8049342B2 (en) Semiconductor device and method of fabrication thereof
CN100472782C (en) Semiconductor devices
US20120267798A1 (en) Multiple die face-down stacking for two or more die
US20150221616A1 (en) Semiconductor package
US9013033B2 (en) Multiple die face-down stacking for two or more die
JP2013546197A (en) Improved stacked microelectronic assembly with a central contact
WO2014066153A1 (en) Multiple die stacking for two or more die
TWI734271B (en) Double side mounted large mcm package with memory channel length reduction
US20090200651A1 (en) Multi-chip package
US9691691B2 (en) Semiconductor package with sidewall contacting bonding tape
CN115206945A (en) Packaging structure and electronic equipment
CN111564419B (en) Chip lamination packaging structure, manufacturing method thereof and electronic equipment
KR20200033020A (en) Stack package including partially stacked semiconductor dies
TW202209581A (en) Semiconductor package including vertical interconnector
JP3850712B2 (en) Multilayer semiconductor device
CN221783207U (en) Chip packaging structure and electronic equipment
CN220106512U (en) Novel POP chip packaging structure
EP4362086A1 (en) Chip package structure and electronic apparatus
WO2024168948A1 (en) Semiconductor packaging structure and formation method thereof
WO2012021310A1 (en) Disaggregated semiconductor chip assembly and packaging technique
KR100525450B1 (en) Chip Stack Type Semiconductor Package

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination