CN116153870A - Stacked packaging structure and manufacturing method thereof - Google Patents

Stacked packaging structure and manufacturing method thereof Download PDF

Info

Publication number
CN116153870A
CN116153870A CN202310430691.8A CN202310430691A CN116153870A CN 116153870 A CN116153870 A CN 116153870A CN 202310430691 A CN202310430691 A CN 202310430691A CN 116153870 A CN116153870 A CN 116153870A
Authority
CN
China
Prior art keywords
chip
layer
frame
chips
layer chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310430691.8A
Other languages
Chinese (zh)
Inventor
杨国江
郭智
吴涛
汪阳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangsu Changjing Pulian Power Semiconductor Co ltd
Original Assignee
Jiangsu Changjing Pulian Power Semiconductor Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Changjing Pulian Power Semiconductor Co ltd filed Critical Jiangsu Changjing Pulian Power Semiconductor Co ltd
Priority to CN202310430691.8A priority Critical patent/CN116153870A/en
Publication of CN116153870A publication Critical patent/CN116153870A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames

Abstract

The embodiment of the invention discloses a stacked package structure and a manufacturing method thereof, wherein the stacked package structure comprises: a frame; a multi-layer chip, which is laminated on one side of the frame; the chips comprise an ith chip and a jth chip, and the jth chip is positioned at one side of the ith chip far away from the frame; along the stacking direction of the chips, the j-th layer chip comprises an overlapping part overlapped with the i-th layer chip and a suspending part not overlapped with the i-th layer chip; wherein i and j are positive integers and i is not equal to j; and the support structure is positioned on one side of the jth layer chip, which is close to the frame, and is contacted with the suspension subsection of the jth layer chip, and is used for supporting the suspension subsection of the jth layer chip. According to the technical scheme provided by the embodiment of the invention, the chip can be supported by arranging the supporting structure on the chip suspension part and enabling the supporting structure to be in contact with the chip suspension part, so that the chip is prevented from being damaged.

Description

Stacked packaging structure and manufacturing method thereof
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a stacked package structure and a method for manufacturing the same.
Background
As the demands for miniaturization and multifunction of electronic devices have increased, the demands for miniaturization and high density of semiconductor packages have also increased.
At present, packaging can be achieved through stacking of chips, but suspension occurs in a chip bonding area in the multi-layer chip stacking process. When the wire bonding process is connected to the semiconductor chip through the lead, pressure can be generated in the suspended area of the semiconductor chip due to the gravity of the lead and the wire bonding stress, and then chip cracks can be caused, so that the electrical property of the product is poor.
Disclosure of Invention
The embodiment of the invention provides a stacked packaging structure and a manufacturing method thereof, which are used for supporting a suspended part of a chip and preventing the chip from being damaged.
In a first aspect, an embodiment of the present invention provides a stacked package structure, including:
a frame;
a multi-layer chip, which is laminated on one side of the frame; the chips comprise an ith layer of chips and a jth layer of chips, and the jth layer of chips are positioned on one side of the ith layer of chips far away from the frame; along the stacking direction of the chips, the j-th layer chip comprises an overlapping part overlapped with the i-th layer chip and a suspending part not overlapped with the i-th layer chip; wherein i and j are positive integers and i is not equal to j;
and the support structure is positioned on one side of the jth layer chip, which is close to the frame, and is contacted with the suspension subsection of the jth layer chip, and is used for supporting the suspension subsection of the jth layer chip.
Optionally, the multiple layers of chips include an nth layer chip, the nth layer chip is located at a side of any other chip far away from the frame, and at least the nth layer chip includes the overlapping portion and the suspending portion;
the support structure is in contact with at least the suspended portion of the nth layer chip.
Optionally, the j-th layer chip includes a first connection pad;
the first connection pad is located on one side surface of the j-th layer chip far away from the frame, and the first connection pad is electrically connected with the frame through a connection wire.
Optionally, the suspended portion includes a second connection pad;
the second connection pad is located on one side surface of the suspended part, close to the frame, and is electrically connected with the frame through the supporting structure.
Optionally, the ith layer chip includes a covering portion overlapping the jth layer chip and an exposing portion not overlapping the jth layer chip;
the exposed portion includes a third connection pad;
the third connection pad is positioned on one side surface of the exposed part far away from the frame, and the third connection pad is electrically connected with the frame through a connection wire.
Optionally, the support structure includes a support surface adjacent one side of the frame;
the support surface is in contact with the frame;
or the supporting surface is contacted with an mth layer chip, the mth layer chip is positioned on one side of the ith layer chip, which is close to the frame, and along the stacking direction of a plurality of layers of chips, and the mth layer chip covers the suspended subsection; where m is a positive integer and m+.i, m+.j.
Optionally, the support surface is in contact with the frame;
the frame comprises a heat conducting layer, the heat conducting layer is positioned on one side, close to the chip, of the frame, and the supporting surface is in contact with the heat conducting layer.
Optionally, the dimension of the support structure along the first direction is d, wherein d is greater than or equal to 50 μm; the first direction intersects a stacking direction of the plurality of layers of the chips.
Optionally, the frame includes:
a substrate;
an inner base island positioned at one side of the substrate and close to the central area of the substrate; the chip lamination layers are arranged on one side of the inner base island;
and the outer base island is positioned on one side of the substrate and is positioned on one side of the inner base island away from the central area of the substrate.
In a second aspect, an embodiment of the present invention further provides a method for manufacturing a stacked package structure, which is applied to the stacked package structure in any one of the first aspect, where the method includes:
providing a frame;
preparing a plurality of layers of chips which are arranged in a laminated manner on one side of the frame; the chips comprise an ith layer of chips and a jth layer of chips, and the jth layer of chips are positioned on one side of the ith layer of chips far away from the frame; along the stacking direction of the chips, the j-th layer chip comprises an overlapping part overlapped with the i-th layer chip and a suspending part not overlapped with the i-th layer chip; wherein i and j are positive integers and i is not equal to j;
and preparing a supporting structure on one side of the j-th layer chip close to the frame, wherein the supporting structure is contacted with the suspended part of the j-th layer chip.
According to the technical scheme provided by the embodiment of the invention, when the multi-layer chips are stacked and arranged on one side of the frame, the jth layer chip comprises an overlapping part overlapped with the ith layer chip and a suspending part not overlapped with the ith layer chip along the stacking direction of the multi-layer chips, and the supporting structure is arranged on one side of the jth layer chip close to the frame and contacted with the suspending part of the jth layer chip, so that the suspending part of the jth layer chip can be supported, the chips are prevented from being damaged, and the normal working performance of the chips is ensured.
Drawings
Fig. 1 is a schematic structural diagram of a stacked package structure according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another stacked package structure according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another stacked package structure according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another stacked package structure according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another stacked package structure according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another stacked package structure according to an embodiment of the present invention;
fig. 7 is a flowchart of a method for manufacturing a stacked package structure according to an embodiment of the present invention.
10, a frame; 20. a chip; 30. a support structure; 40. a first connection pad; 50. connecting wires; 60. a second connection pad; 70. a third connection pad; 80. a heat conducting layer; 90. a substrate; 100. an inner base island; 110. an outer base island; 21. overlapping sections; 22. suspending the branches; 23. covering the subsections; 24. exposing the sections; 203. layer 1 chip; 202. layer 2 chip; 201. layer 3 chip; 301. a support surface.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Fig. 1 is a schematic structural view of a stacked package structure according to an embodiment of the present invention, fig. 2 is a schematic structural view of another stacked package structure according to an embodiment of the present invention, and fig. 3 is a schematic structural view of yet another stacked package structure according to an embodiment of the present invention. As shown in fig. 1-3, the stacked package structure includes; a frame 10; a multi-layered chip 20 stacked on one side of the frame 10; the multi-layer chip 20 includes an ith layer chip and a jth layer chip, the jth layer chip being located on a side of the ith layer chip remote from the frame; along the stacking direction of the multi-layered chip 20 (X direction as shown in fig. 1), the j-th layer chip includes an overlap portion 21 overlapping the i-th layer chip and a flying portion 22 not overlapping the i-th layer chip; wherein i and j are positive integers and i is not equal to j; the support structure 30 is located at one side of the jth layer chip near the frame 10 and contacts with the suspension 22 of the jth layer chip to support the suspension 22 of the jth layer chip.
Specifically, for convenience of description, in the embodiment of the present invention, three layers of chips 20 are stacked on one side of the frame 10. Illustratively, referring to fig. 1, a layer 1 chip 203, a layer 2 chip 202, and a layer 3 chip 201 are sequentially stacked on the frame 10. As a possible embodiment, when i=1, j=2, along the stacking direction X of the multi-layer chip 20, that is, the layer 2 chip 202 includes the suspended portion 22 that does not overlap the layer 1 chip 203 and the overlapped portion 21 that overlaps the layer 1 chip 203, the suspended portion 22 of the layer 2 chip 202 can play a supporting role on the suspended portion 22 of the layer 2 chip 202 by providing the supporting structure 30 on the side of the layer 2 chip 202 near the frame 10, and the supporting structure 30 is in contact with the suspended portion 22 of the layer 2 chip 202. It will be appreciated that, with continued reference to fig. 1, when i=2, j=3, the supporting structure 30 is disposed on the suspended portion 22 of the layer 3 chip 201, and the supporting structure 30 contacts with the suspended portion 22 of the layer 3 chip 201, so as to support the suspended portion 22 of the layer 3 chip 201.
As another possible implementation manner, fig. 4 is a schematic structural diagram of still another stacked package structure provided in this embodiment of the present invention, as shown in fig. 4, when i=2, j=3, that is, when the layer 3 chip 201 includes a suspended portion 22 that does not overlap with the layer 2 chip 202 and an overlapping portion 21 that overlaps with the layer 2 chip 202, the suspended portion 22 of the layer 3 chip 201 can be supported by providing the support structure 30 on the suspended portion of the layer 3 chip 201, and the support structure 30 contacts with the suspended portion 22 of the layer 3 chip 201.
According to the stacked package structure provided by the embodiment of the invention, when the multi-layer chips are stacked on one side of the frame, the jth layer chip comprises an overlapping part overlapped with the ith layer chip and a suspending part not overlapped with the ith layer chip along the stacking direction of the multi-layer chips, and the supporting structure is arranged on one side of the jth layer chip close to the frame and contacted with the suspending part of the jth layer chip, so that the suspending part of the jth layer chip can be supported, the chips are prevented from being damaged, and the normal working performance of the chips is ensured.
Optionally, the multi-layer chip includes an nth layer chip, the nth layer chip is located at a side of any other chip far away from the frame, and at least the nth layer chip includes an overlapping portion and a suspending portion; the support structure is at least in contact with the suspended portion of the nth layer chip.
Specifically, at least the nth layer chip includes overlapping portion and unsettled portion, that is to say, the topmost chip that is located one side of keeping away from the frame includes overlapping portion and unsettled portion, because the topmost chip is influenced by factors such as self gravity or routing stress, unsettled portion appears the phenomenon that the bonding weakens or the chip damage appears easily with the lower floor chip easily, consequently, through making bearing structure at least contact with unsettled portion of topmost chip, can realize the supporting role to the unsettled portion of topmost chip, consequently can avoid the chip damage of topmost chip because of factors such as self gravity or routing stress, and then can guarantee the working property of chip.
For example, with continued reference to fig. 1, 3 and 4, taking n=3, i.e. taking the top-most chip in the stacked package structure as the layer 3 chip 201 as an example, the layer 3 chip 201 includes a suspension 22 and an overlap 21, and the supporting effect of the suspension 22 of the layer 3 chip 201 can be achieved by making the supporting structure 30 contact with at least the suspension of the layer 3 chip 201.
It should be noted that, referring to the stacking manner of the multi-layer chip 20 shown in fig. 1 and 3, since the layer 2 chip 202 includes the suspended portion 22 that does not overlap the layer 1 chip 203 and the overlapped portion 21 that overlaps the layer 1 chip 203, the supporting structure 30 is disposed on the side of the layer 2 chip 202 near the frame 10 and is in contact with the suspended portion 22 of the layer 2 chip 202, and the supporting structure 30 is in contact with the suspended portion 22 of the layer 2 chip 202, so as to support the suspended portion 22 of the layer 2 chip. That is, by arranging the supporting structure 30 at the position where the suspended portion 22 exists, the supporting structure 30 contacts with the suspended portion 22, so that the chip 20 of the whole stacked package structure can be further supported, and further, the working performance of the chip 20 can be further ensured.
Optionally, the j-th layer chip includes a first connection pad; the first connecting pad is positioned on one side surface of the j-th layer chip far away from the frame, and the first connecting pad is electrically connected with the frame through the connecting wire.
Specifically, the jth layer chip includes a first connection pad, and the connection pad can be understood as a bonding structure of bonding wire arranged in the bonding area, that is, the chip and the frame can be electrically connected through connection routing by bonding wire on the first connection pad of the jth layer chip. Further, the first connection pad is located on a surface of the j-th layer chip far away from the frame, i.e. the j-th layer chip is mounted. That is, the bonding area of the j-th layer chip is located on the surface of the side far away from the frame. The first connection pad may be located in the overlapping portion or in the floating portion, and the location of the first connection pad is not specifically limited in the embodiment of the present invention. Fig. 5 is a schematic structural diagram of still another stacked package structure according to an embodiment of the present invention. Fig. 5 shows a technical solution in which the first connection pads are located in the overlapping portion and the suspending portion, as shown in fig. 5, when j=3, the layer 3 chip 201 includes the first connection pads 40, and the first connection pads 40 in the layer 3 chip 201 are electrically connected with the frame 10 through the connection wires 50, so that transmission of electrical signals between the chip 20 and the frame 10 can be achieved.
Optionally, the suspended portion includes a second connection pad; the second connection pad is positioned on one side surface of the suspended part, which is close to the frame, and the second connection pad is electrically connected with the frame through the supporting structure.
Specifically, the suspended part comprises a second connection pad, and the second connection pad is positioned on one side surface of the suspended part, which is close to the frame, namely the chip is flipped. That is, the bonding area of the chip is located near one side surface of the frame. Further, the second connection pad is electrically connected with the frame through the supporting structure, so that on one hand, the process flow can be simplified, namely, the process flow of electrical connection realized by bonding wires on the connection pad and utilizing the connection wires and the frame can be omitted. On the other hand, not only can support unsettled subsection through bearing structure, can also be connected with the frame electricity through bearing structure, realize the transmission of electric signal between chip and the frame.
Illustratively, with continued reference to fig. 1, when j=2, the overhanging portion 22 of the layer 2 chip 202 includes the second connection pad 60, and the second connection pad 60 in the layer 2 chip 202 is electrically connected to the frame 10 through the support structure 30, such that transmission of electrical signals between the chip 20 and the frame 10 can be achieved.
Optionally, the ith layer of chips includes a cover portion overlapping the jth layer of chips and an exposed portion non-overlapping the jth layer of chips; the exposed portion includes a third connection pad; the third connection pad is positioned on one side surface of the exposed part far away from the frame, and the third connection pad is electrically connected with the frame through the connection wire.
Illustratively, with continued reference to fig. 5, when i=2, j=3, the layer 2 chip 202 includes a cover portion 23 overlapping the layer 3 chip 201 and an exposed portion 24 not overlapping the layer 3 chip 201, the exposed portion 24 includes a third connection pad 70, the third connection pad 70 is located on a side surface of the exposed portion 24 away from the frame 10, that is, the layer 2 chip 202 may be mounted forward, that is, the third connection pad 70 is facing upward, and the third connection pad 70 is electrically connected to the frame 10 through the connection trace 50, that is, the transmission of the electrical signal between the layer 2 chip 202 and the frame 10 may be completed.
Optionally, the support structure includes a support surface adjacent one side of the frame; the supporting surface is contacted with the frame; or the supporting surface is contacted with the m-th layer chip, the m-th layer chip is positioned on one side of the i-th layer chip, which is close to the frame, and covers the suspended part along the stacking direction of the multi-layer chip; where m is a positive integer and m+.i, m+.j.
Specifically, as one possible embodiment, with continued reference to FIG. 1, the support structure 30 includes a support surface 301 adjacent one side of the frame 10, with the support surface 301 contacting the frame 10.
As another possible embodiment, with continued reference to fig. 4, when m=1, i=3, the supporting surface 301 is in contact with the tier 1 chip 203, the tier 1 chip 203 is located on a side of the tier 3 chip 201 near the frame 10 and along the stacking direction X of the multiple chips 20, and the tier 1 chip 203 covers the suspended portion 22.
Further, fig. 6 is a schematic structural diagram of still another stacked package structure according to an embodiment of the present invention, as shown in fig. 6, where the supporting surface 301 contacts the frame 10; the frame 10 includes a thermally conductive layer 80, the thermally conductive layer 80 being located on a side of the frame 10 adjacent to the chip 20, and the support surface 301 being in contact with the thermally conductive layer 80.
Specifically, the frame 10 includes a heat conducting layer 80, and the heat conducting layer 80 is located on a side, close to the chip 20, of the frame 10, so that on one hand, heat generated in the operation process of the chip 20 can be transferred to a bonding pad located below the frame 10 through the frame 10 by contacting the supporting surface 301 with the heat conducting layer 80, and further product power consumption is reduced. On the other hand, the routing is facilitated by the heat conductive layer 80, i.e., the connection pads are electrically connected to the outer islands by connection traces.
Illustratively, the thermally conductive layer may be a metal layer of gold, silver, or the like.
Optionally, with continued reference to FIG. 1, the support structure 30 has a dimension d in a first direction (Y direction as shown in FIG. 1), wherein d+.50 μm; the first direction Y intersects the stacking direction X of the multilayer chip.
Specifically, the size of the supporting structure 30 along the first direction Y is d, and d is greater than or equal to 50 μm, so that heat generated in the working process of the chip 20 can be guaranteed to be fully transferred to the bonding pad positioned below the frame 10 through the frame 10, on one hand, the power consumption of the product can be further reduced, and the working performance of the chip is guaranteed. On the other hand, the supporting effect on the suspended subsection can be improved.
Optionally, with continued reference to fig. 6, the frame 10 includes: a substrate 90; an inner island 100 located at one side of the substrate 90 and close to a central region of the substrate 90; the multi-layer chip 20 is stacked on one side of the inner base island 100; an outer island 110 is located on the side of the substrate 90 and on the side of the inner island 100 away from the central region of the substrate 90.
Specifically, the substrate 90 may be a copper substrate, and the inner and outer islands 100 and 110 may be etched from the substrate 90 by an etching process. The inner islands 100 may be used to house a multi-layer chip 20 and the outer islands 110 on either side of the inner islands 100 may be electrically connected to connection pads on the chip 20 by connection traces 50.
According to the technical scheme provided by the embodiment of the invention, the supporting structure is used for supporting the chip, so that the chip is prevented from being damaged due to the factors such as self gravity, lead gravity or wire bonding stress, and the normal working performance of the chip is further ensured. In addition, the supporting structure comprises a supporting surface, and the supporting surface is in contact with the heat conducting layer on the frame or the supporting surface is in contact with the heat conducting layer on the frame, so that heat generated by a chip in operation can be transferred to the bonding pad through the supporting structure, and the power consumption of a product can be further reduced.
In a second aspect, an embodiment of the present invention further provides a method for manufacturing a stacked package structure, which is applied to the stacked package structure in the first aspect, and fig. 7 is a schematic flow chart of the method for manufacturing a stacked package structure, as shown in fig. 7, where the method includes:
s101, providing a frame.
Specifically, with continued reference to FIG. 6, the frame 10 includes a base plate 90, an inner base island 100, and an outer base island 110. Optionally, the frame 10 may also include a thermally conductive layer 80.
S102, preparing a plurality of layers of chips which are arranged in a laminated way on one side of a frame; the multi-layer chip comprises an ith layer chip and a jth layer chip, and the jth layer chip is positioned at one side of the ith layer chip far away from the frame; along the stacking direction of the multi-layer chips, the j-th layer chip comprises an overlapped part overlapped with the i-th layer chip and a suspended part not overlapped with the i-th layer chip.
Wherein i and j are positive integers and i noteq j.
Illustratively, with continued reference to fig. 1, layer 1 chip 203, layer 2 chip 202, and layer 3 chip 201 are stacked in sequence on frame 10. When i=1, j=2, the layer 2 chip 202 includes the flying portion 22 that does not overlap the layer 1 chip 203 and the overlapping portion 21 that overlaps the layer 1 chip 203 along the stacking direction X of the multi-layer chip 20.
S103, preparing a supporting structure on one side of the j-layer chip close to the frame, wherein the supporting structure is in contact with the suspended part of the j-layer chip.
Illustratively, with continued reference to FIG. 1, the suspended portion 22 of the tier 2 chip 202 can be supported by providing a support structure 30 on a side of the tier 2 chip 202 adjacent to the frame 10 and in contact with the suspended portion 22 of the tier 2 chip 202, and the support structure 30 is in contact with the suspended portion 22 of the tier 2 chip 202.
Optionally, the method further comprises attaching a high-temperature adhesive tape to the back of the frame after the frame is provided, so that protection can be performed to prevent subsequent processes from affecting the chip.
Alternatively, a plurality of chips are stacked on the frame, specifically, the chips may be fixed on the frame by mounting with non-conductive adhesive or conductive adhesive, and by brushing the adhesive, mounting the chips, and then curing.
Optionally, the base island and the chip are electrically connected by wire bonding in the subsequent step, and the frame after encapsulation, post-curing and film tearing (in the case of film attachment) is formed by encapsulating the front frame, forming an encapsulation layer on the front surface. Finally, cutting may be performed to form individual products.
According to the manufacturing method of the stacked package structure, the stacked chips are manufactured in the frame, the j-th layer chip comprises an overlapped part overlapped with the i-th layer chip and a suspension part not overlapped with the i-th layer chip along the stacking direction of the multi-layer chip, and the support structure is manufactured on one side, close to the frame, of the j-th layer chip and is in contact with the suspension part of the j-th layer chip, so that the suspension part of the j-th layer chip can be supported, and breakage of the chips is prevented.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements, combinations, and substitutions can be made by those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims (10)

1. A stacked package structure, comprising:
a frame;
a multi-layer chip, which is laminated on one side of the frame; the chips comprise an ith layer of chips and a jth layer of chips, and the jth layer of chips are positioned on one side of the ith layer of chips far away from the frame; along the stacking direction of the chips, the j-th layer chip comprises an overlapping part overlapped with the i-th layer chip and a suspending part not overlapped with the i-th layer chip; wherein i and j are positive integers and i is not equal to j;
and the support structure is positioned on one side of the jth layer chip, which is close to the frame, and is contacted with the suspension subsection of the jth layer chip, and is used for supporting the suspension subsection of the jth layer chip.
2. The package on package structure of claim 1, wherein the plurality of layers of chips comprises an nth layer of chips, the nth layer of chips being located on a side of any other chip away from the frame, at least the nth layer of chips comprising the overlap portion and the overhang portion;
the support structure is in contact with at least the suspended portion of the nth layer chip.
3. The package on package structure of claim 1, wherein the j-th level chip includes a first connection pad;
the first connection pad is located on one side surface of the j-th layer chip far away from the frame, and the first connection pad is electrically connected with the frame through a connection wire.
4. The package on package structure of claim 1, wherein the flying portion comprises a second connection pad;
the second connection pad is located on one side surface of the suspended part, close to the frame, and is electrically connected with the frame through the supporting structure.
5. The package on package structure of claim 1, wherein the ith layer of chips includes a cover portion overlapping the jth layer of chips and an exposed portion non-overlapping the jth layer of chips;
the exposed portion includes a third connection pad;
the third connection pad is positioned on one side surface of the exposed part far away from the frame, and the third connection pad is electrically connected with the frame through a connection wire.
6. The package on package structure of claim 1, wherein the support structure comprises a support surface adjacent one side of the frame;
the support surface is in contact with the frame;
or the supporting surface is contacted with an mth layer chip, the mth layer chip is positioned on one side of the ith layer chip, which is close to the frame, and along the stacking direction of a plurality of layers of chips, and the mth layer chip covers the suspended subsection; where m is a positive integer and m+.i, m+.j.
7. The package on package structure of claim 6, wherein the support surface is in contact with the frame;
the frame comprises a heat conducting layer, the heat conducting layer is positioned on one side, close to the chip, of the frame, and the supporting surface is in contact with the heat conducting layer.
8. The package on package structure of claim 1, wherein the support structure has a dimension d in the first direction, wherein d is greater than or equal to 50 μm; the first direction intersects a stacking direction of the plurality of layers of the chips.
9. The package on package structure of claim 1, wherein the frame comprises:
a substrate;
an inner base island positioned at one side of the substrate and close to the central area of the substrate; the chip lamination layers are arranged on one side of the inner base island;
and the outer base island is positioned on one side of the substrate and is positioned on one side of the inner base island away from the central area of the substrate.
10. A method for manufacturing a stacked package structure, applied to the stacked package structure of any one of claims 1 to 9, characterized in that the manufacturing method comprises:
providing a frame;
preparing a plurality of layers of chips which are arranged in a laminated manner on one side of the frame; the chips comprise an ith layer of chips and a jth layer of chips, and the jth layer of chips are positioned on one side of the ith layer of chips far away from the frame; along the stacking direction of the chips, the j-th layer chip comprises an overlapping part overlapped with the i-th layer chip and a suspending part not overlapped with the i-th layer chip; wherein i and j are positive integers and i is not equal to j;
and preparing a supporting structure on one side of the j-th layer chip close to the frame, wherein the supporting structure is contacted with the suspended part of the j-th layer chip.
CN202310430691.8A 2023-04-21 2023-04-21 Stacked packaging structure and manufacturing method thereof Pending CN116153870A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310430691.8A CN116153870A (en) 2023-04-21 2023-04-21 Stacked packaging structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310430691.8A CN116153870A (en) 2023-04-21 2023-04-21 Stacked packaging structure and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN116153870A true CN116153870A (en) 2023-05-23

Family

ID=86354659

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310430691.8A Pending CN116153870A (en) 2023-04-21 2023-04-21 Stacked packaging structure and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN116153870A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006310649A (en) * 2005-04-28 2006-11-09 Sharp Corp Semiconductor device package and its manufacturing method
CN108292653A (en) * 2015-09-25 2018-07-17 英特尔公司 For the method, apparatus and system for making encapsulation integrated circuit die interconnect
CN112117242A (en) * 2019-06-20 2020-12-22 江苏长电科技股份有限公司 Chip packaging structure and manufacturing method thereof
CN115206945A (en) * 2021-04-14 2022-10-18 晶晨半导体(上海)股份有限公司 Packaging structure and electronic equipment

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006310649A (en) * 2005-04-28 2006-11-09 Sharp Corp Semiconductor device package and its manufacturing method
CN108292653A (en) * 2015-09-25 2018-07-17 英特尔公司 For the method, apparatus and system for making encapsulation integrated circuit die interconnect
CN112117242A (en) * 2019-06-20 2020-12-22 江苏长电科技股份有限公司 Chip packaging structure and manufacturing method thereof
CN115206945A (en) * 2021-04-14 2022-10-18 晶晨半导体(上海)股份有限公司 Packaging structure and electronic equipment

Similar Documents

Publication Publication Date Title
US7638362B2 (en) Memory module with improved mechanical strength of chips
US6388313B1 (en) Multi-chip module
US7705245B2 (en) Electronic device substrate and its fabrication method, and electronic device and its fabrication method
CN101414603B (en) Stacked semiconductor package and method for manufacturing the same
JP4441974B2 (en) Manufacturing method of semiconductor device
US6448659B1 (en) Stacked die design with supporting O-ring
US10651146B2 (en) Chip packaging structure and manufacturing method for the same
US7786571B2 (en) Heat-conductive package structure
JPS6355213B2 (en)
CN103250246A (en) Method and system for thin multi chip stack package with film on wire and copper wire
JP4945682B2 (en) Semiconductor memory device and manufacturing method thereof
JP2008252016A (en) Substrate and manufacturing method therefor, and circuit device and manufacturing method therefor
KR20020068709A (en) Dual die package and manufacturing method thereof
CN101295709A (en) Stack package with releasing layer and method for forming the same
CN116153870A (en) Stacked packaging structure and manufacturing method thereof
US20200027818A1 (en) Semiconductor package
JP2008187076A (en) Circuit device and manufacturing method thereof
KR101458954B1 (en) Semiconductor Package apparatus having redistribution layer
US20120225521A1 (en) Board on chip package substrate and manufacturing method thereof
US20040125574A1 (en) Multi-chip semiconductor package and method for manufacturing the same
JPH10242379A (en) Semiconductor module
CN213752714U (en) Full-flexible display driving module, display module and display terminal
KR20080096442A (en) Semiconductor package
JP4652428B2 (en) Semiconductor device and manufacturing method thereof
KR100256306B1 (en) Stack multi chip module

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20230523

RJ01 Rejection of invention patent application after publication