CN220106512U - Novel POP chip packaging structure - Google Patents

Abstract

The utility model provides a novel POP chip packaging structure, which comprises: a substrate logic chip flip-chip bonded to a front surface of the substrate; a first solder ball layer is arranged around the logic chip, and the first solder ball layer is attached to the substrate; the plastic layer is arranged on the substrate to carry out plastic packaging on the first solder ball layer and the logic chip, and a plurality of through holes communicated with the first solder ball layer are formed above the first solder ball layer; a second solder ball layer connected with the first solder ball layer is arranged in the through holes; the plastic-packaged memory chip is bonded on the second solder ball layer; the third solder ball layer is welded on the back of the substrate, and the passive device is welded on the back of the substrate.

Description

Novel POP chip packaging structure

Technical Field

The present disclosure relates to semiconductor manufacturing, and more particularly, to an electronic package structure.

Background

The recent growth in semiconductor Integrated Circuits (ICs) has shifted from the traditional computer and communications industries to portable mobile devices such as smartphones, tablet computers, and new generation wearable devices. The integrated circuit packaging technology has also seen a new trend to cope with the special requirements of mobile device products, such as increased functional flexibility, improved electrical performance, thinned volume, reduced cost, and rapid advent. Package on package is one of the very popular three-dimensional overlay techniques that have been developed for IC packaging of mobile devices that can be used for system integration. At present, representative POP packages in the market are the InFo-POP of TMSC and the Interposer-POP of AmKor, which are mainly characterized by the use of Interposer (Interposer) and TMV (molded via). These two packaging forms still have room for improvement in terms of the number of integratable chips, and the indirect connection between the top device and the bottom substrate has the disadvantages of high delay and poor signal.

Disclosure of Invention

The utility model provides a novel POP chip packaging structure, which aims to improve the quantity of chips which can be integrated by the packaging structure and the flexibility of interconnection of the packaging structure.

In order to achieve the above object, an embodiment of the present utility model provides a novel POP chip package structure, including:

substrate board

A logic chip flip-chip bonded to the front surface of the substrate; a first solder ball layer is arranged around the logic chip, and the first solder ball layer is attached to the substrate;

the plastic layer is arranged on the substrate to carry out plastic packaging on the first solder ball layer and the logic chip, and a plurality of through holes communicated with the first solder ball layer are formed above the first solder ball layer; a second solder ball layer connected with the first solder ball layer is arranged in the through holes;

the plastic-packaged memory chip is bonded on the second solder ball layer;

and the third solder ball layer is welded on the back surface of the substrate, and the passive device is welded on the back surface of the substrate.

Preferably, the first solder ball layer comprises a double-layer solder ball, the double-layer solder ball is arranged up and down, and the upper solder ball is contacted with the lower solder ball.

Preferably, the height of the first solder ball layer is smaller than the height of the logic chip.

Preferably, the height of the third solder ball layer is greater than the height of the passive device.

Preferably, the second solder ball layer and the third solder ball layer are single-layered solder balls.

The scheme of the utility model has the following beneficial effects:

the utility model can realize the integration of multiple chips and passive devices, and the lower delay and higher signal transmission speed are realized by adopting a direct connection mode between the top and the bottom plate, and simultaneously, the first solder ball layer has higher interconnection flexibility and can be connected with each device.

Additional features and advantages of the utility model will be set forth in the detailed description which follows.

Drawings

FIG. 1 is a schematic diagram of the structure of the present utility model;

fig. 2 is a flow chart of the present utility model.

[ reference numerals description ]

1-base plate, 2-logic chip, 3-first solder ball layer, 4-plastic sealing layer, 5-second solder ball layer, 6-memory chip, 7-third solder ball layer and 8-passive device.

Detailed Description

In order to make the technical problems, technical solutions and advantages to be solved more apparent, the following detailed description will be given with reference to the accompanying drawings and specific embodiments.

Embodiments of the present utility model are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present utility model and are not to be construed as limiting the present utility model.

In the description of the present utility model, it should be understood that references to orientation descriptions such as upper, lower, front, rear, left, right, etc. are based on the orientation or positional relationship shown in the drawings, are merely for convenience of description of the present utility model and to simplify the description, and do not indicate or imply that the apparatus or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present utility model.

In the description of the present utility model, a number means one or more, a number means two or more, and greater than, less than, exceeding, etc. are understood to not include the present number, and above, below, within, etc. are understood to include the present number. The description of the first and second is for the purpose of distinguishing between technical features only and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defining "first" and "second" may explicitly or implicitly include one or more features.

In the description of the present utility model, it should be noted that, unless explicitly specified and limited otherwise, the term "connected" should be construed broadly, and for example, it may be a fixed connection or an active connection, or it may be a detachable connection or a non-detachable connection, or it may be an integral connection; may be mechanically connected, may be electrically connected, or may be in communication with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements, indirect communication or interaction relationship between the two elements.

The following disclosure provides many different embodiments, or examples, for implementing different aspects of the utility model.

As shown in fig. 1, an embodiment of the present utility model provides a novel POP chip package structure, which includes a substrate 1, a logic chip 2 disposed on a front surface of the substrate 1, the logic chip 2 being bonded on the substrate 1 in a flip-chip manner, and a first solder ball layer 3 disposed around the logic chip 2, where the first solder ball layer 3 is attached to the front surface of the substrate 1. A plastic sealing layer 4 is arranged above the first solder ball layer 3, the plastic sealing layer 4 is used for completely plastic sealing the first solder ball layer 3 and the logic chip 2, namely, the thickness of the plastic sealing layer 4 is larger than that of the first solder ball layer 3 and the logic chip 2, a plurality of longitudinal through holes are formed in the plastic sealing layer 4, the through holes are correspondingly positioned above each solder ball of the first solder ball layer 3, a second solder ball layer 5 is further arranged in each through hole, the second solder ball layer 5 is connected with the first solder ball layer 3, a storage chip 6 which is already subjected to diameter plastic sealing is further arranged above the second solder ball layer 5 to form laminated packaging, and the storage chip 6 is in signal connection with the second solder ball layer 5.

A third solder ball layer 7 is also arranged on the back surface of the substrate 1, and the third solder ball layer 7 is attached to the back surface of the substrate 1. A passive device 8 is also soldered to the opposite side of the substrate 1.

Further, the first solder ball layer 3 includes a double layer of solder balls, the double layer of solder balls are arranged up and down, and the upper solder balls are in contact with the lower solder balls.

Further, the height of the first solder ball layer 3 is smaller than the height of the logic chip 2. The second solder ball layer 5 and the third solder ball layer 7 are single-layered solder balls, and the height of the third solder ball layer 7 is greater than the height of the passive device 8.

In the utility model, the POP packaging mode is adopted, various chips and passive devices 8 can be more integrated, meanwhile, the top and the substrate 1 are directly and electrically connected with high density, lower delay and higher signal speed are realized, compared with the traditional TMV interconnection layout, the Copper Core Ball (CCB) or copper column is replaced by adopting the two-layer solder ball stacking mode, higher interconnection flexibility can be realized, and higher productivity can be realized by depending on the existing industrial technology.

Referring to the step schematic of fig. 2, wherein each figure represents a process step, the construction process of the present utility model is as follows:

step one, a logic chip 2 is flipped on the front surface of a substrate 1;

step two, the passive device 8 is attached to the back surface of the substrate 1;

filling gaps between the front surface of the substrate 1 and the logic chip 2;

step four, first solder ball layers 3 are planted on the front surface of the substrate 1, the first solder ball layers 3 are located around the logic chip 2, and the height of the first solder ball layers 3 is ensured to be lower than that of the logic chip 2;

step five, after the ball implantation is finished, the first solder ball layer 3 and the logic chip 2 are subjected to plastic packaging to form a plastic packaging layer 4;

step six, laser perforating is carried out on the front surface of the plastic sealing layer 4 to form a through hole, so that the upper layer solder balls of the first solder ball layer 3 which is subjected to plastic sealing are exposed, a second solder ball layer 5 is planted above the first solder ball layer 3, and the second solder ball layer 5 is kept to be attached to the first solder ball layer 3;

and step seven, bonding the memory chip 6 which is subjected to the diameter plastic package on the second solder ball layer 5 to form a stacked package.

And step eight, a third solder ball layer 7 is planted on the back surface of the substrate 1, and the height of the third solder ball layer 7 is higher than that of the passive device 8.

While the foregoing is directed to the preferred embodiments of the present utility model, it will be appreciated by those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present utility model, and such modifications and adaptations are intended to be comprehended within the scope of the present utility model.

Claims (5)

1. Novel POP chip packaging structure, its characterized in that includes:

substrate (1)

A logic chip (2) flip-chip bonded to the front surface of the substrate (1); a first solder ball layer (3) is arranged around the logic chip (2), and the first solder ball layer (3) is attached to the substrate (1);

the plastic layer (4) is arranged on the substrate (1) to carry out plastic packaging on the first solder ball layer (3) and the logic chip (2), and a plurality of through holes communicated with the first solder ball layer (3) are formed above the first solder ball layer (3) by the plastic layer (4); a second solder ball layer (5) connected with the first solder ball layer (3) is arranged in the through holes;

the plastic-packaged storage chip (6) is bonded on the second solder ball layer (5);

and the third solder ball layer (7) is welded on the back surface of the substrate (1), and a passive device (8) is welded on the back surface of the substrate (1).

2. The novel POP chip package structure of claim 1, wherein: the first solder ball layer (3) comprises a double-layer solder ball, the double-layer solder ball is arranged up and down, and the upper solder ball is contacted with the lower solder ball.

3. The novel POP chip package structure of claim 2, wherein: the height of the first solder ball layer (3) is smaller than the height of the logic chip (2).

4. The novel POP chip package structure of claim 3, wherein: the height of the third solder ball layer (7) is greater than the height of the passive device (8).

5. The novel POP chip package structure of claim 4, wherein: the second solder ball layer (5) and the third solder ball layer (7) are single-layer solder balls.