WO2024040749A1

WO2024040749A1 - Semiconductor structure and method for manufacturing same

Info

Publication number: WO2024040749A1
Application number: PCT/CN2022/130070
Authority: WO
Inventors: 吕开敏
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-08-26
Filing date: 2022-11-04
Publication date: 2024-02-29
Also published as: CN117690884A

Abstract

Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a method for manufacturing same. The semiconductor structure comprises: a bearing structure and multiple layers of chip modules stacked on the bearing structure in a staggered manner. Each chip module comprises an aligned area and a staggered area; the aligned areas of all the chip modules directly face one another, and the staggered areas of two adjacent layers of chip modules are staggered. Each aligned area comprises a first interface and a second interface. Each aligned area has two opposite sides, the first interface is located one of the two opposite sides, and the second interface is located between the two opposite sides. The surface of each aligned area is provided with a wiring layer. The wiring layer is electrically connected to the second interface and extends to the other side of the two opposite sides. The first interface of each chip module is electrically connected to the wiring layer of the neighboring chip module. The first interface and the second interface of the bottom-layer chip module are electrically connected to the bearing structure. The embodiments of the present disclosure can at least improve the heat dissipation degree of a semiconductor structure, thereby improving the performance of the semiconductor structure.

Description

Semiconductor structures and methods of manufacturing semiconductor structures

cross reference

This application refers to Chinese Patent Application No. 202211034123.8 titled "Semiconductor Structure and Manufacturing Method of Semiconductor Structure" submitted on August 26, 2022, which is fully incorporated by reference into this application.

Technical field

Embodiments of the present disclosure belong to the field of semiconductors, and specifically relate to a semiconductor structure and a manufacturing method of the semiconductor structure.

Background technique

Chip stacking technology, represented by High Bandwidth Memory (HBM), extends the original one-dimensional memory layout to three dimensions, that is, stacking many chips together and packaging them, thus greatly increasing the density of the chips and Achieving large capacity and high bandwidth.

However, as the number of stacked layers increases, the heat generated by the chip during operation will accumulate, causing adverse effects on product performance. For example, an increase in temperature will affect the volume of the semiconductor structure, causing mechanical cracks in the material; an increase in temperature will also affect the electrical performance of the chip, making it difficult to achieve expected functions.

Contents of the invention

Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method of the semiconductor structure, which are at least conducive to improving the degree of heat dissipation of the semiconductor structure, thereby improving the performance of the semiconductor structure.

According to some embodiments of the present disclosure, on one hand, embodiments of the present disclosure provide a semiconductor structure, wherein the semiconductor structure includes: a load-bearing structure; multi-layer chip modules staggeredly stacked on the load-bearing structure, the chip modules including at least one chip ; The chip module includes a facing area and a non-facing area; the facing areas of all the chip modules are arranged facing each other, and the non-facing areas of the two adjacent layers of the chip modules are staggered; The facing area has a first interface and a second interface; the facing area has opposite sides, the first interface is located on one of the opposite sides, and the second interface is located between the opposite sides. between; the surface of the facing area has a wiring layer, the wiring layer is electrically connected to the second interface, and extends to the other side of the opposite sides; the first interface of the chip module It is electrically connected to the wiring layer of the adjacent chip module; the first interface and the second interface of the bottom chip module are electrically connected to the carrying structure.

According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure also provide a manufacturing method of a semiconductor structure. The manufacturing method includes: providing a plurality of chip modules, the chip module including at least one chip; the chip module includes: area and a non-facing area; the facing area has a first interface and a second interface; the facing area has opposite sides, the first interface is located on one side of the opposite sides, and the third interface Two interfaces are located between the opposite sides; a wiring layer is formed on the surface of the facing area, and the wiring layer is electrically connected to the second interface and extends to the other side of the opposite sides; Provide a carrying structure, a plurality of the chip modules are staggered and stacked on the carrying structure, and the facing areas of all the chip modules are arranged facing each other; the non-facing areas of the two adjacent layers of the chip modules are arranged facing each other. The areas are staggered; and the first interface of the chip module is electrically connected to the wiring layer of the adjacent chip module; the first interface and the second interface of the bottom chip module are electrically connected to the load-bearing structure.

The technical solution provided by the embodiments of the present disclosure at least has the following advantages: multiple chip modules are staggered and stacked, thereby increasing the distance between non-facing areas, that is, increasing the heat dissipation space; the facing areas of the chip modules have wiring layers, and wiring The layer can increase the heat dissipation speed of the facing area; in addition, the wiring layer can change the layout of the second interface to facilitate signal connections between chips.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.

Figure 1 shows a schematic diagram of an LPDDR product;

Figure 2 shows a schematic diagram of an HBM product;

3-5 respectively show schematic diagrams of different semiconductor structures provided by an embodiment of the present disclosure;

6-7 illustrate top views of different semiconductor structures provided by an embodiment of the present disclosure;

8-9 illustrate schematic diagrams of two chip modules provided by another embodiment of the present disclosure.

Detailed ways

Figure 1 provides an LPDDR product. Referring to Figure 1, chips 100 are bonded to each other through a die attach film (DAF) or a film on wire (FOW). Figure 2 provides an HBM product. Referring to Figure 2, in HBM, the chip 100 is bonded through a non-conductive film (NCF), or the chip 100 is filled with a molded underfill (Mold underfill). Between 100 and 100 chips. However, the heat dissipation capabilities of the above-mentioned colloid and adhesive layers are weak. In addition, as the number of stacked layers increases, the chip 100 becomes thinner and the space between the chips 100 becomes smaller and smaller; the shrinking heat dissipation space will lead to heat accumulation, which will affect the performance of the semiconductor structure. .

Embodiments of the present disclosure provide a semiconductor structure, in which chip modules are staggered and stacked, thereby increasing the heat dissipation space; the area facing the chip module has a wiring layer, and the wiring layer can better conduct heat on the chip surface; in addition, the wiring layer The layout of the second interface can be changed to facilitate electrical connection between the second interface and the first interface of the adjacent chip to achieve signal connection between the chips.

Each embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present disclosure, many technical details are provided to enable readers to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

As shown in Figures 3 to 7, an embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes: a carrying structure 4; multi-layer chip modules 10 staggered and stacked on the carrying structure 4. The chip module 10 includes at least one chip 1 ; The chip module 10 includes a facing area A and a non-facing area B; the facing areas A of all chip modules 10 are arranged facing each other, and the non-facing areas B of two adjacent layers of chip modules 10 are staggered; the facing area A has The first interface 21 and the second interface 22; the facing area A has two opposite sides, the first interface 21 is located on one side of the opposite two sides, and the second interface 22 is located between the opposite two sides; the surface of the facing area A has The wiring layer 3 is electrically connected to the second interface 22 and extends to the other side of the opposite sides; the first interface 21 of the chip module 10 is electrically connected to the wiring layer 3 of the adjacent chip module 10; the bottom layer The first interface 21 and the second interface 22 of the chip module 10 are electrically connected to the carrying structure 4 .

Such a design has at least the following advantages:

First, the orthographic projections of adjacent chip modules 10 on the carrying structure 4 do not completely overlap; the distance between adjacent non-facing areas B is larger, so the heat dissipation space is larger; the adjacent facing areas A The distance between them is small, so the wiring layer 3 is provided on the surface facing area A, so that the heat on the surface facing area A can be better conducted.

Second, the wiring layer 3 is electrically connected to the second interface 22 and extends to the side facing the area A, so that the wiring layer 3 can face the first interface 21 of the adjacent chip 1, thereby facilitating the implementation of the chip. 1, thereby realizing the signal connection between multiple chips 1 and the carrying structure 4.

Third, the first interface 21 is located at the edge facing area A; the wiring layer 3 changes the layout of the second interface 22 and leads it to the edge facing area A. That is, the connection points of the two chips 1 are located at the edge facing the area A. Compared with being located in the middle area facing the area A, the connection points located at the edge can improve the stability of the chip 1 stack and prevent the chip 1 from tipping or collapsing.

The semiconductor structure will be described in detail below with reference to the accompanying drawings.

Referring to FIGS. 3 to 5 , the carrying structure 41 and the chip module 10 can be fixed through the welding portion 5 and achieve signal connection. In some embodiments, the load-bearing structure 41 may be a substrate. The substrate mainly plays the role of protecting the chip 1 and electrically connecting the chip 1 with the peripheral circuit board. The substrate should be made of materials with good heat dissipation properties, such as organic substrates or ceramic substrates. In other embodiments, the chip 1 can be a memory chip, such as a dynamic random access memory (DRAM, Dynamic Random Access Memory), and the chip 21 can also be a logic chip, and the memory chip communicates with the logic chip.

In some embodiments, the chip 21 close to the carrying structure 1 may be a logic chip, and the chip 21 far away from the carrying structure 1 may be a memory chip.

In other embodiments, the carrier structure 41 may be a logic chip.

Referring to FIGS. 3-5 , the semiconductor structure also includes: a filling layer 7 covering the chip module 10 and the carrying structure 4 . The filling layer 7 can protect the chip module 10 from the influence of the external environment, such as resisting external moisture and solvents, and can also resist thermal shock and mechanical vibration when the semiconductor structure is installed. In some embodiments, the material of the filling layer 7 may be epoxy resin material, that is, EMC (Epoxy molding compound).

The alternate arrangement of the chip modules 10 is beneficial to increasing the filling space of the filling layer 7, thereby reducing the difficulty of filling, improving the filling effect, and thereby ensuring the sealing effect. In addition, large particle filling materials can also be used to improve the heat dissipation effect.

The first interface 21 and the second interface 22 will be described in detail below.

Referring to FIGS. 3-5 , for ease of understanding, the opposite sides of the facing area A are defined as the first side L and the second side R, and the first side L of the facing area A of all chip modules 10 is arranged on the same direction, the second side R of all chip modules 10 facing the area A is arranged in the same direction.

Since the chip modules 10 are stacked alternately, for two adjacent chip modules 10, the first interface 21 of one of the chip modules 10 is located on the first side L, and the wiring layer 3 of the chip module 10 is formed between the first side L and the first side L. extends between the two sides R to the second side R; the first interface 21 of another chip module 10 is located on the second side R, and the wiring layer 3 of the chip module 10 extends between the first side L and the second side R. to the first side L.

It should be noted that the first interface 21 is located at the edge of the facing area A, but since the facing area A is also connected to the non-facing area B, the first interface 21 is located in the middle area of the entire chip module 10 . In addition, the second interface 22 is also located in the middle area of the entire chip module 10 instead of at the edge. The middle area here can be understood as the middle position of the top or bottom surface of the chip module 10 .

The reason why the first interface 21 and the second interface 22 are located in the middle area of the chip module 10 is that the chip 1 usually includes an array area and a peripheral area; among them, the peripheral area is equipped with a control circuit, the array area is equipped with memory units, and the peripheral area is The circuit controls the reading and writing process of the memory unit. The peripheral area is located in the middle area of chip 1, and the array area is located in the edge area of chip 1. The first interface 21 and the second interface 22 are electrically connected to the circuits in the peripheral area. Therefore, the first interface 21 and the second interface 22 are usually disposed in the middle area of the chip 1 .

In some embodiments, the first interface 21 and the second interface 22 may be bonding pads 51 formed on the surface of the chip 1 to draw out different signals within the chip 1 . After the circuit in the chip 1 is manufactured, the first interface 21 and the second interface 22 connected to the circuit can be directly formed on the front side of the chip 1 to simplify the production process. In other embodiments, the first interface 21 and the second interface 22 may also be located on the back of the chip 1 .

Each chip 1 may have a plurality of first interfaces 21 and a plurality of second interfaces 22 , thereby providing the chip 1 with a plurality of different electrical signals. In some embodiments, multiple first interfaces 21 of the same chip 1 can be arranged in a straight line, and multiple second interfaces 22 of the same chip 1 can be arranged in a straight line. In this way, the structure is simpler. In other embodiments, the adjacent first interfaces 21 of the same chip 1 may also be slightly misaligned, and the adjacent second interfaces 22 of the same chip 1 may also be slightly misaligned. Therefore, the spatial position of the surface of the chip 1 can be fully utilized to increase the number of first interfaces 21 and second interfaces 22 and increase the spacing between adjacent first interfaces 21 and the spacing between adjacent second interfaces 22, thereby reducing signal interference.

Referring to FIGS. 3 and 4 , in some embodiments, the first interface 21 and the second interface 22 of the top chip module 10 are located on the bottom surface of the chip module 10 . Therefore, there is no need to form the first conductive via hole 610 and the second conductive via hole 620 in the top chip module 10 to lead the first interface 21 and the second interface 22 to the bottom surface of the chip module 10 . That is, production steps can be reduced and production costs can be reduced. In other embodiments, the top chip module 10 may also have a first conductive via 610 and a second conductive via 620, which will be described in detail later.

The first interface 21 and the second interface 22 of the non-top chip module 10 are located on the bottom or top surface of the chip module 10; the non-top chip module 10 has first conductive vias 610 and second conductive vias 620 inside, The first conductive via 610 is electrically connected to the first interface 21 , and the second conductive via 620 is electrically connected to the second interface 22 . That is, the first conductive vias 610 and the second conductive vias 620 serve as signal transmission paths in the up and down direction, so there is no need to electrically connect each chip module 10 to the carrying structure 4 through conductive structures such as leads or lead frames, which is beneficial. Reduce the size of the semiconductor structure and improve the integration of the semiconductor structure.

Specifically, in a direction perpendicular to the upper surface of the load-bearing structure 4 , the first conductive via hole 610 can be directly opposite and connected to the first interface 21 , and the second conductive via hole 620 can be directly opposite to and connected to the second interface 22 , so that It is beneficial to increase the contact area between the first conductive through hole 610 and the first interface 21 and the contact area between the second conductive through hole 620 and the second interface 22 .

Since the first conductive via 610 and the second conductive via 620 penetrate the chip module 10 in a direction perpendicular to the upper surface of the carrying structure 4, and the electrical signal of the first conductive via 610 is the same as the electrical signal of the first interface 21, The electrical signal of the second conductive via 620 is the same as the electrical signal of the second interface 22 . Therefore, it can be understood that the top and bottom surfaces of the non-top chip module 10 both have the first interface 21 and the second interface 22 .

The wiring layer 3 will be described in detail below.

In some embodiments, referring to FIGS. 3 and 5 , the non-top chip module 10 has wiring layers 3 on both the top and bottom surfaces. Specifically, referring to FIG. 3 , one wiring layer 3 is connected to the second interface 22 , and the other wiring layer 3 is connected to an end of the second conductive via 620 away from the second interface 22 . Referring to FIG. 5 , the wiring layers 3 on the top and bottom surfaces of the chip module 10 are both connected to the second interface 22 . As can be seen from the foregoing, under the electrical connection of the second conductive through hole 620, both the top and bottom surfaces of the chip module 10 have the second interface 22; therefore, by providing the wiring layer 3 on both the top and bottom surfaces of the chip module 10, it is possible to By changing the layout of the second interface 22 on the top and bottom surfaces of the chip module 10, multiple chip modules 10 can be conveniently connected for signals.

In other embodiments, referring to FIG. 4 , if the number of chip modules 10 is two, that is, the non-top chip module 10 is the bottom chip module 10 , the wiring layer 3 may not be provided on the bottom surface of the chip module 10 to change the The layout of the second interface 22 is; and the bottom of the second conductive via 620 is directly welded to the load-bearing structure 4 . Since the welding position is located in the central area of the chip module 10, in order to ensure the stability of the structure, the welding portion 5 can also be added at the edge of the chip module 10. The added welding portion 5 also helps guide heat transfer.

Referring to Figures 3-5, there are multiple welding portions 5 between adjacent chip modules 10. The welding portions 5 are located on opposite sides of the facing area A, that is, some of the welding portions 5 are located on the first side L, and some of the welding portions 5 are located on the first side L. Located on 2nd side R. The welding portion 5 is connected to the wiring layer 3 of one chip module 10 and to the first interface 21 or the first conductive via 610 of another chip module 10 . That is, the welding portion 5 can not only fix the two chip modules 10 but also achieve electrical connection between the two chip modules 10 .

That is to say, since the first interface 21 is located at the edge of the facing area A, the second interface 22 is changed in layout by the wiring layer 3 and extends to the other edge of the facing area A. Correspondingly, the welding portion 5 can also be located at the opposite edge. The edge of area A. Compared with being located in the center of the facing area A, the welding portion 5 is located at the edge of the facing area A, which is beneficial to enhancing the connection strength of the adjacent chip modules 10, thereby improving the structural solidity.

For example, the soldering part 5 may include two soldering pads 51 and a soldering bump 52 located between the two soldering pads 51 , wherein the material of the soldering pads 51 may be copper, and the material of the soldering bumps 52 may be tin-silver alloy. .

In some embodiments, the welding portions 5 are symmetrically distributed relative to the center of the facing area A. That is, the uniformity of the distribution of the welding portions 5 is improved to balance the connection force of adjacent chip modules 10 and thereby improve the structural robustness.

It should be noted that the welding portion 5 is protruding on the surface of the chip module 10, so adjacent chip modules 10 can be arranged at intervals, thereby forming a heat dissipation space between adjacent chip modules 10. In addition, the welding part 5 has excellent heat dissipation capability, so part of the heat generated by the chip 1 can be transferred to the welding part 5 and then conducted outward by the welding part 5, thereby improving the heat dissipation effect.

Examples of chip modules 10 with different numbers of chips 1 will be described below.

In some embodiments, referring to FIGS. 3-4 , the chip module 10 includes one chip 1 , that is, adjacent chips 1 can be staggered and stacked. The chip 1 has a first through hole 61 and a second through hole 62 . The first through hole 61 serves as the first conductive through hole 610 and the second through hole 62 serves as the second conductive through hole 620 . For example, the first through hole 61 and the second through hole 62 may be through-silicon vias (TSV). Each non-top-layer chip 1 may have a wiring layer 3 on its top and bottom surfaces, thereby enhancing the heat dissipation effect.

In addition, the chip 1 can be stacked front to front or back to back. The heat generated on the front side is greater than that on the back side, so the front side can also be understood as the heating surface. In other embodiments, the chips 1 may be stacked front to back, so that there is only one front side in the area between adjacent chips 1 . That is, the distribution of the heating surface is more even, which is helpful to avoid heat accumulation.

In other embodiments, referring to FIG. 5 , the chip module 10 includes multiple chips 1 , and the orthographic projections of the multiple chips 1 in the chip module 10 on the carrying structure 4 coincide with each other. The first through holes 61 of the plurality of chips 1 are directly opposite and electrically connected, and form the first conductive through hole 610 ; the second through holes 62 of the plurality of chips 1 are directly opposite and electrically connected, and form the second conductive through hole 620 . It is worth noting that the plurality of first through holes 61 in the chip module 10 are electrically connected together through the bonding portion 23; the plurality of second through holes 62 in the chip module 10 are also electrically connected together through the bonding portion 23.

If the number of chips 1 in the top chip module 10 is multiple, first conductive vias 610 and second conductive vias 620 also need to be formed in the top chip module 10 to realize signal connections of multiple chips 1 . If the top chip module 10 has only one chip 1, the first conductive via 610 and the second conductive via 620 may not be formed.

Continuing to refer to FIG. 5 , in the non-top chip module 10 , the top surface of the uppermost chip 1 may have a wiring layer 3 , and the bottom surface of the lowermost chip 1 may have a wiring layer 3 . The opposite surfaces of the two chips 1 may not Has wiring layer 3. As a result, the production process can be simplified.

It is worth noting that when the number of chips 1 in the chip module 10 is more than two, the wiring layer 3 may not be provided on the surface of the chip module 10 located in the middle. The main reason is that in the chip module 10, interfaces with the same electrical signals can be aligned and arranged, so there is no need to use the wiring layer 3 to change the location of the interfaces. As a result, the number of wiring layers 3 can be reduced, thereby simplifying the production process.

Multiple chips 1 in the chip module 10 can be connected through hybrid bonding. That is, the surface of the chip 1 has a bonding portion 23 and a dielectric layer (not shown in the figure). The upper surface of the bonding portion 23 can be flush with the upper surface of the dielectric layer, or the upper surface of the bonding portion 23 can be relative to the dielectric layer. The upper surface has a slight depression. Under heating conditions, the bonding portions 23 of two adjacent chips 1 will expand slightly and bond together to form an electrical connection; the dielectric layers of two adjacent chips 1 can be connected together through intermolecular forces. The hybrid bonding method is beneficial to improving the reliability of the chip module 10 . In other embodiments, bump welding technology may also be used to pre-bond multiple chips 1 to form the chip module 10 .

In addition, when the chip module 10 includes a plurality of stacked chips 1 , the front surface of the uppermost chip 1 in the chip module 10 can be placed outward, and the front surface of the lowermost chip 1 in the chip module 10 can also be placed outward. That is, the heating surfaces of the chips 1 on the outermost two sides are arranged outward, so that heat can be dissipated in time and heat accumulation can be reduced.

By way of example, the chip module 10 includes two chips 1, and the front surfaces A of the two chips 1 are both facing outward. That is, the two chips 1 are bonded back to back, thereby ensuring that the heat of each chip 1 in the chip module 10 can be dissipated in time.

In some embodiments, the number of chips 1 within the chip module 10 is less than three. It should be noted that if there are too many chips 1 in the chip module 10, the heat of the chip 1 located in the middle of the chip module 10 may not be dissipated in time. Therefore, controlling the number of chips 1 of the chip module 10 to three or less is beneficial to improving the overall heat dissipation effect of the chip module 10 .

In some embodiments, the number of chips 1 in the plurality of chip modules 10 is the same. As a result, the production process is simpler and helps improve the stability of the stack. In other embodiments, the number of chips 1 in the multiple chip modules 10 may also be different. For example, the number of chips 1 in the chip module 10 located on the top and bottom layers is greater, and the number of chips 1 in the chip module 10 located in the middle position is smaller, thereby reducing the heat accumulation degree of the chip module 10 in the middle position.

Referring to FIGS. 3 to 5 , both the first through hole 61 and the second through hole 62 are located in the middle area of the chip 1 . As can be seen from the above, the first interface 21 and the second interface 22 are usually located in the middle area of the chip 1. Since the first through hole 61 is electrically connected to the first interface 21, and the second through hole 62 is electrically connected to the second interface 22, accordingly , the first through hole 61 and the second through hole 62 may also be located in the middle area of the chip 1 .

Since the first through hole 61 and the second through hole 62 have good thermal conductivity, the heat dissipation speed in the central area of the chip 1 is faster than the heat dissipation speed in the edge area of the chip 1 . One edge area of chip 1 is located in the non-facing area B and is exposed in the filling layer 7, which increases the heat dissipation space in the edge area; the other edge area of chip 1 is located in the facing area A, and this edge area is provided with wiring Layer 3, the wiring layer 3 is also connected to the soldering portion 5, that is, the edge area can dissipate heat through the heat dissipation channel composed of the soldering portion 5, the first through hole 61 of the adjacent chip 1, and its own wiring layer 3. It can be seen that the staggered stacking method and the wiring layer 3 cooperate with each other to balance the heat dissipation degree of the central area and the edge area to improve the overall heat dissipation effect of the semiconductor structure.

Referring to Figures 6-7, the positional relationship between the facing area A and the non-facing area B will be described in detail below. Figures 6-7 show top views of different semiconductor structures. To be more intuitive, Figures 6-7 only show the chip module 10 in the semiconductor structure.

Referring to FIG. 6 , in some embodiments, the facing area A and the non-facing area B of the same chip module 10 are arranged in a first direction X, and the first direction X is parallel to the upper surface of the carrying structure 4 . That is, the facing area A and the non-facing area B are arranged side by side. For example, the shapes of the orthographic projections of the facing area A and the non-facing area B on the bearing structure 4 are both rectangular, and one side of the facing area A and the non-facing area B coincides with each other. That is to say, for two adjacent chip modules 10, they are misaligned in the first direction X and aligned in the second direction Y. The second direction Y is parallel to the upper surface of the bearing structure 4 and perpendicular to the first direction X. This dislocation method is relatively simple and helps ensure the stability of the structure.

In other embodiments, the non-facing area B of the same chip module 10 half surrounds the facing area A. For example, the shapes of the orthographic projections of the facing area A and the non-facing area B on the bearing structure 4 are both rectangular, and the two sides of the facing area A and the non-facing area B coincide with each other. That is to say, for two adjacent chip modules 10, both have misalignment in the first direction X and the second direction Y. In this way, the heat dissipation space can be increased simultaneously in the first direction X and the second direction Y to improve the heat dissipation effect.

In some embodiments, referring to FIGS. 3 and 5 , the areas of the orthographic projections of the plurality of facing areas A on the bearing structure 4 are the same; the areas of the orthogonal projections of the plurality of non-facing areas B on the bearing structure 4 are the same. In this way, it is beneficial to balance the heat dissipation degree of multiple chip modules 10 .

In some embodiments, referring to Figures 3 and 5, the orthographic projections of the non-facing areas B of the odd-numbered chip modules 10 on the carrier structure 4 coincide; the non-facing areas B of the even-numbered layers of the chip modules 10 are on the carrier structure. The orthographic projections on 4 coincide. As a result, the center of gravity of the semiconductor structure can be moved closer to the center, thereby improving the stability of the structure. In addition, the shape of the semiconductor structure is also more regular, which helps simplify the packaging process. In addition, it is helpful to unify the positions of the first interface 21 and the second interface 22 of the chip module 10, thereby facilitating welding of two adjacent chip modules 10.

In some embodiments, the ratio of the area of the orthographic projection of the facing area A on the bearing structure 4 to the area of the orthographic projection of the non-facing area B on the bearing structure 4 is 3:1 to 1:1. It can be understood that if the area of the orthographic projection facing the area A is too small, the chip module 10 may collapse or topple over, and the utilization of the space will be low; if the area of the orthographic projection not facing the area B is too small, If it is small, the heat dissipation space of the chip module 10 is smaller. When the area of the orthographic projection of the facing area A and the non-facing area B is within the above range, it is beneficial to improve the stability of the chip module 10, improve space utilization, and effectively reduce the degree of heat accumulation.

To sum up, in the embodiment of the present disclosure, the wiring layer 3 and the welding portion 5 are used to adjust the stacking method of the chip modules 10 to staggered stacking, and the first conductive vias 610 and the second conductive vias 620 can perform upper and lower signal connections. The wiring layer 3, the welding portion 5, and the first and second

conductive vias

610 and 620 are beneficial to improving the heat conduction effect in the facing area A; the non-facing area B has a large heat dissipation space, thereby increasing the heat dissipation speed. Therefore, the heat dissipation degree of the facing area A and the non-facing area B can be enhanced at the same time. In addition, using the first conductive via 610 and the second conductive via 620 can reduce line resistance, thereby reducing heat generation.

As shown in FIGS. 8-9 and 3, another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure provided by an embodiment of the present application will be described in detail below with reference to the accompanying drawings.

Referring to Figures 8-9, multiple chip modules 10 are provided. The chip module 10 includes a facing area A and a non-facing area B; the facing area A has a first interface 21 and a second interface 22; the facing area A has an opposite On both sides, the first interface 21 is located on one side of the opposite sides, and the second interface 22 is located between the opposite sides. A wiring layer 3 is formed on the surface facing the area A. The wiring layer 3 is electrically connected to the second interface 22 and extends to the other of the two opposite sides.

Specifically, referring to FIG. 8 , one chip 1 is provided as the top chip module 10 . Pads are formed on the bottom of the chip 1 to serve as the first interface 21 and the second interface 22. The material of the pads may be aluminum, copper or other metals. Bonding pads 51 and bonding bumps 52 are formed directly below the first interface 21 . A wiring layer 3 connected to the second interface 22 is formed, and a soldering pad 51 and a soldering bump 52 are formed on the side of the wiring layer 3 away from the second interface 22 . There is no need to form penetrating first through holes 61 and second through holes 62 in the chip 1 to simplify the production process.

Referring to FIG. 9 , a plurality of chips 1 are provided as non-top chip modules 10 . Pads are formed on the top surface of the chip 1 to serve as the first interface 21 and the second interface 22 . The bonding pad 51 is formed directly above the first interface 21 to form the wiring layer 3 connected to the second interface 22 , and the bonding pad 51 is formed on the side of the wiring layer 3 away from the second interface 22 . In addition, a first through hole 61 and a second through hole 62 are also formed through the chip 1 . The upper end of the first through hole 61 is connected to the first interface 21 , and the upper end of the second through hole 62 is connected to the second interface 22 . A wiring layer 3 is formed on the bottom surface of the chip 1 , and the wiring layer 3 is connected to the lower end of the second through hole 62 . A bonding pad 51 is formed on the side of the wiring layer 3 away from the second through hole 62 and the lower end of the first through hole 61 .

In other embodiments, the chip module 10 may include multiple chips 1 , the first through holes 61 in the multiple chips 1 are electrically connected to form a first conductive via 610 , and the second through holes 62 in the multiple chips 1 The second conductive via hole 620 is electrically connected.

Based on the steps of FIGS. 8 and 9 , it can be seen that first conductive vias 610 and second conductive vias 620 are formed in the non-top chip module 10 , and the first conductive vias 610 are electrically connected to the first interface 21 . The two conductive vias 620 are electrically connected to the second interface 22 . The first conductive via 610 and the second conductive via 620 enable faster heat dissipation in the middle area of the chip module 10 .

Referring to Figure 3, a load-bearing structure 4 is provided. Multiple chip modules 10 are staggered and stacked on the load-bearing structure 4. The facing areas A of all chip modules 10 are arranged facing each other; the non-facing areas B of two adjacent layers of chip modules 10 are arranged facing each other. staggered arrangement; electrically connect the first interface 21 of the chip module 10 to the wiring layer 3 of the adjacent chip module 10; electrically connect the first interface 21 and the second interface 22 of the bottom chip module 10 to the carrying structure 4.

A molded underfill process is used to form a filling layer 7 covering the chip module 10 and the load-bearing structure 4. The staggered arrangement of the chip modules 10 can increase the filling space. Therefore, large particles of filling material can be selected to improve the heat dissipation effect.

To sum up, in the embodiment of the present disclosure, the soldering pads 51 and the soldering bumps 52 are formed on the lower surface of the first interface 21 of the top chip module 10, and the wiring layer 3 is formed on the lower surface of the second interface 22, so that the The signals of the second interface 22 extend to the edge of the chip 1 , and thereafter, the bonding pads 51 and the bonding bumps 52 are formed on the lower surface of the wiring layer 3 . The non-top chip module 10 uses the wiring layer 3 to extend the signal of the second interface 22 to the edge of the chip 1 . In addition, a first conductive via 610 and a second conductive via 620 are formed in the chip module 10 . Thereafter, the chip module 10 is staggeredly soldered and filled using a molded underfill process. In this way, the degree of heat dissipation of the semiconductor structure can be improved, thereby improving the performance of the semiconductor structure.

In the description of this specification, reference to the terms "some embodiments," "exemplarily," etc. means that a particular feature, structure, material or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present disclosure or in the example. In this specification, the schematic expressions of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and combine different embodiments or examples and features of different embodiments or examples described in this specification unless they are inconsistent with each other.

Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above-mentioned embodiments are illustrative and should not be construed as limitations of the present disclosure. Those of ordinary skill in the art can make modifications to the above-mentioned embodiments within the scope of the present disclosure. The embodiments are subject to changes, modifications, substitutions and modifications, so any changes or modifications made in accordance with the claims and description of the present disclosure shall be within the scope of the patent of the present disclosure.

Claims

A semiconductor structure including:

load-bearing structure;

Multi-layer chip modules are staggered and stacked on the carrier structure. The chip module includes at least one chip. The chip module includes a facing area and a non-facing area. The facing areas of all the chip modules face each other. Set, the non-facing areas of the chip modules on two adjacent layers are staggered;

The facing area has a first interface and a second interface; the facing area has opposite sides, the first interface is located on one of the opposite sides, and the second interface is located on the opposite two sides. between the sides; the surface of the facing area has a wiring layer, the wiring layer is electrically connected to the second interface and extends to the other side of the opposite sides;

The first interface of the chip module is electrically connected to the wiring layer of the adjacent chip module;

The first interface and the second interface of the underlying chip module are electrically connected to the carrying structure.
The semiconductor structure of claim 1, wherein

The first interface and the second interface of the top chip module are located on the bottom surface of the chip module;

The first interface and the second interface of the non-top-layer chip module are located on the bottom or top surface of the chip module; the non-top-layer chip module has first conductive vias and second conductive vias therethrough. Through holes, the first conductive through holes are electrically connected to the first interface, and the second conductive through holes are electrically connected to the second interface.
The semiconductor structure according to claim 2, wherein both the top surface and the bottom surface of the non-top-layer chip module have the wiring layer, and one of the wiring layers is connected to the second interface, and the other wiring layer The layer is connected to an end of the second conductive via hole away from the second interface.
The semiconductor structure of claim 2, wherein

There are a plurality of welding portions between adjacent chip modules, and the welding portions are located on opposite sides of the facing area; the welding portions are connected to the wiring layer of one chip module and to the wiring layer of another chip module. The first interface or the first conductive via of the chip module is connected.
The semiconductor structure of claim 2, wherein the chip has first through holes and second through holes,

The chip module includes one of the chips, the first through hole serves as the first conductive through hole, and the second through hole serves as the second conductive through hole;

Alternatively, the chip module includes a plurality of chips, and the first through holes of the plurality of chips are facing and electrically connected to form the first conductive through hole; the second through holes of the plurality of chips are The through holes are opposite and electrically connected, and constitute the second conductive through hole.
The semiconductor structure of claim 5, wherein the first through hole and the second through hole are located in a middle region of the chip.
The semiconductor structure according to claim 1, wherein the facing areas and the non-facing areas of the same chip module are arranged in a first direction, and the first direction is parallel to the carrier structure. upper surface.
The semiconductor structure of claim 1, wherein the non-facing area of the same chip module half surrounds the facing area.
The semiconductor structure of claim 1, wherein

The areas of the orthographic projections of the plurality of facing areas on the load-bearing structure are the same;

The areas of the orthogonal projections of the plurality of non-facing areas on the bearing structure are the same.
The semiconductor structure of claim 9, wherein

The orthographic projections of the non-facing areas of the chip modules of odd-numbered layers on the load-bearing structure coincide;

The orthographic projections of the non-facing areas of the chip modules of the even-numbered layers on the carrier structure coincide with each other.
The semiconductor structure of claim 1, wherein

The ratio of the area of the orthographic projection of the facing area on the load-bearing structure to the area of the orthographic projection of the non-facing area on the load-bearing structure is 3:1 to 1:1.
The semiconductor structure of claim 1, further comprising:

A filling layer covering the chip module and the carrying structure.
A method of manufacturing a semiconductor structure, including:

A plurality of chip modules are provided, and the chip module includes at least one chip; the chip module includes a facing area and a non-facing area; the facing area has a first interface and a second interface; the facing area has an opposite On both sides, the first interface is located on one of the opposite sides, and the second interface is located between the opposite sides;

A wiring layer is formed on the surface of the facing area, the wiring layer is electrically connected to the second interface, and extends to the other side of the opposite sides;

Provide a carrying structure, a plurality of the chip modules are staggered and stacked on the carrying structure, and the facing areas of all the chip modules are arranged facing each other; the non-facing areas of the two adjacent layers of the chip modules are arranged facing each other. The areas are staggered; and the first interface of the chip module is electrically connected to the wiring layer of the adjacent chip module; the first interface and the second interface of the bottom chip module are electrically connected to the load-bearing structure.
The method of manufacturing a semiconductor structure according to claim 13, further comprising:

A first conductive via hole and a second conductive via hole are formed in the chip module that is not the top layer. The first conductive via hole is electrically connected to the first interface, and the second conductive via hole is electrically connected to the first interface. The second interface is electrically connected.
The method of manufacturing a semiconductor structure according to claim 13, further comprising: using a molding underfill process to form a filling layer covering the chip module and the carrying structure.