KR100525450B1 - Chip Stack Type Semiconductor Package - Google Patents
Chip Stack Type Semiconductor Package Download PDFInfo
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- KR100525450B1 KR100525450B1 KR10-2001-0007285A KR20010007285A KR100525450B1 KR 100525450 B1 KR100525450 B1 KR 100525450B1 KR 20010007285 A KR20010007285 A KR 20010007285A KR 100525450 B1 KR100525450 B1 KR 100525450B1
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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Abstract
본 발명은 리드간 서로 대향하는 선단부의 주위에 단차부를 형성하여 리드의 상면과 하면에 각각 반도체 칩을 부착하되 리드 하면의 반도체 칩은 상기 단차부와 접속되도록 함으로써, 두께와 면적을 최소화하면서 2개 이상의 반도체 칩을 적층하여 그 집적용량을 확대하는 반도체 칩 적층형 반도체 패키지를 제공한다.According to the present invention, a step is formed around lead portions facing each other between leads to attach semiconductor chips to the top and bottom surfaces of the leads, respectively, so that the semiconductor chips on the bottom surface of the leads are connected to the step portions, thereby minimizing thickness and area. Provided is a semiconductor chip stack-type semiconductor package in which the above semiconductor chips are stacked to increase their integrated capacity.
상기 목적을 달성하기 위해, 본 발명의 반도체 칩 적층형 반도체 패키지는,서로 대향하는 선단부에 단차가 발생되도록 일부가 제거된 단차부를 포함하는 리드와, 상기 리드의 하부에 부착되며 중앙부에 전기접속이 가능한 센터패드를 구비하는 제 1 반도체 칩과, 상기 리드의 상부에 부착되는 칩 가장자리에 전기접속이 가능한 사이드패드를 구비하는 제 2 반도체 칩과, 상기 제 1 반도체 칩과 상기 리드의 단차부 및, 제 2 반도체 칩과 상기 리드의 단차부를 제외한 영역을 각각 전기적으로 접속시키는 접속부재와, 상기 각 접속부재와 상기 제 1, 제 2 반도체 칩 중 적어도 어느 하나의 반도체 칩의 상면 또는 하면이 노출되도록 하면서 봉지하는 봉지재와, 상기 리드의 전기 신호를 외부로 인출하는 외부인출단자를 포함하는 것을 특징으로 한다.In order to achieve the above object, the semiconductor chip stacked semiconductor package of the present invention, a lead including a stepped portion is partially removed so that a step is generated in the opposing front end portion, and attached to the lower portion of the lead and electrically connectable to the center A first semiconductor chip having a center pad, a second semiconductor chip having a side pad electrically connected to a chip edge attached to an upper portion of the lead, a stepped portion of the first semiconductor chip and the lead, A connecting member for electrically connecting the semiconductor chip and the region except for the stepped portion of the lead, and the top surface or the bottom surface of each of the connection members and at least one semiconductor chip of the first and second semiconductor chips are exposed. It characterized in that it comprises an encapsulant and an outer lead terminal for drawing the electrical signal of the lead to the outside.
Description
본 발명은 반도체 칩 적층형 반도체 패키지에 관한 것으로서, 보다 상세하게는 적어도 2개 이상의 반도체 칩을 적층하도록 하여 집적 용량을 늘리면서 경박단소한 반도체 칩 적층형 반도체 패키지에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip stack type semiconductor package, and more particularly, to a light and simple semiconductor chip stack type semiconductor package, in which at least two or more semiconductor chips are stacked to increase an integrated capacity.
휴대용 전자제품이 소형화하면서 이에 반도체가 실장될 공간은 더욱 줄어들고 반면에 제품은 더욱 다기능화하고 고성능화되기 때문에 이를 뒷받침해 줄 반도체의 개수는 늘어나는 추세이다. 따라서 단위체적당 실장효율을 높이기 위해서 패키지는 경박단소(輕薄短小)화에 부응할 수밖에 없어서,이러한 요구로 개발되어 상용화된 것이 칩 크기와 거의 같은 크기의 패키지인 CSP(Chip Size Package), 또는 칩 위에 칩을 올려쌓는 SCSP (Stacked CSP)등의 개발이 진척되고 있다.As portable electronic products become smaller, the space for semiconductor mounting is further reduced, while the number of semiconductors to support them is increasing because products are becoming more versatile and higher performance. Therefore, in order to increase the mounting efficiency per unit volume, the package has to meet the thin and small size, and the CSP (Chip Size Package), Or the development of SCSP (Stacked CSP), which stacks chips on top of chips, is progressing.
도 1 에는 종래 반도체 패키지의 개략적인 단면도를 도시하였다. 1 is a schematic cross-sectional view of a conventional semiconductor package.
도면에서 보는 바와 같이 종래의 일반적인 반도체 패키지의 구조는 전자회로가 집적되어 있는 반도체칩(11)과, 상기 반도체칩(11)이 에폭시 접착제(16)에 의해 부착되는 탑재판(15)과, 상기 반도체칩(11)의 신호를 외부로 전달할 수 있는 다수의 리드(12)와, 상기 반도체칩(11)과 리드(12)를 연결시켜 주는 와이어(13)와, 상기 반도체칩(11)과 그 외 주변구성품들을 외부의 산화 및 부식으로부터 보호하기 위하여 그 외부를 감싼 봉지재(14)로 이루어진다.As shown in the drawings, a structure of a conventional semiconductor package includes a semiconductor chip 11 in which an electronic circuit is integrated, a mounting plate 15 to which the semiconductor chip 11 is attached by an epoxy adhesive 16, and A plurality of leads 12 capable of transmitting a signal of the semiconductor chip 11 to the outside, a wire 13 connecting the semiconductor chip 11 and the leads 12, the semiconductor chip 11, and the In order to protect the external peripheral components from external oxidation and corrosion, it is made of an encapsulant 14 wrapped therein.
이러한 구성에 의한 종래의 반도체 패키지는 반도체칩(11)으로부터 출력된 신호와 와이어(13)를 통해 리드(12)로 전달되며, 상기 리드(12)는 마더보드에 연결되어 있어 리드(12)로 전달된 신호가 마더보드(도시 생략함)를 주변소자로 전달된다. 주변소자에서 발생된 신호가 반도체칩(11)으로 전달되는 경우에는 위에서 설명한 경로의 역순으로 신호가 전달되는 것이다.The conventional semiconductor package according to this configuration is transmitted to the lead 12 through the signal and the wire 13 output from the semiconductor chip 11, the lead 12 is connected to the motherboard to the lead 12 The transmitted signal is transferred from the motherboard (not shown) to the peripheral elements. When the signal generated from the peripheral device is transferred to the semiconductor chip 11, the signal is transmitted in the reverse order of the path described above.
상술한 종래 반도체 패키지는 다음과 같은 문제점을 지니고 있다. The conventional semiconductor package described above has the following problems.
상술한 반도체 패키지는 하나의 칩만을 내장하도록 제조되어 있기 때문에 집적용량을 증대하기 위해서는 동일한 패키지가 따로 실장되어야 하거나 또는 반도체 패키지를 적층시켜야 하는 경우가 많아졌다. Since the above-described semiconductor package is manufactured so that only one chip is embedded, the same package must be separately mounted or semiconductor packages must be stacked in order to increase the integrated capacity.
반도체 패키지를 따로 실장할 경우에는 반도체 패키지가 제한된 마더보드의 실장면적을 점유하게 되어 효율적이지 못하고 상기 반도체 패키지를 적층할 경우에는 그 높이가 현저히 증가하여 제품을 경박단소화할 수 없는 문제점이 발생하였다. When the semiconductor package is separately mounted, the semiconductor package occupies a limited mounting area of the motherboard, which is not efficient, and when the semiconductor package is stacked, its height increases significantly, thus making it impossible to reduce the weight and size of the product. .
이에 따라 하나의 반도체 패키지에 2개 이상의 반도체 칩을 내장시킴으로써, 종래 1개의 반도체 칩을 내장한 반도체 패키지와 동일한 공간을 점유하되 그 집적용량을 증가시키는 반도체 칩 적층형 반도체 패키지를 필요로 하게 되었다.Accordingly, by embedding two or more semiconductor chips in one semiconductor package, a semiconductor chip stacked semiconductor package is required, which occupies the same space as a semiconductor package incorporating one semiconductor chip and increases its integration capacity.
본 발명은 상술한 종래 기술의 문제점을 해결하기 위하여 안출된 발명으로서, 동일 사이즈의 반도체 칩을 적층하는 칩 적층형 패키지에 있어서, 리드간 서로 대향하는 선단부의 주위에 단차부를 형성하여 리드의 상면과 하면에 각각 반도체 칩을 부착하되 리드 하면의 반도체 칩은 상기 단차부와 접속되도록 함으로써, 두께와 면적을 최소화하면서 2개 이상의 반도체 칩을 적층하여 그 집적용량을 확대하는 반도체 칩 적층형 반도체 패키지를 제공하는 것을 그 목적으로 한다. SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art. In the chip stack type package in which semiconductor chips of the same size are stacked, a step portion is formed around the front end portions of the leads facing each other to form upper and lower surfaces of the leads. To provide a semiconductor chip stacked semiconductor package for attaching a semiconductor chip to each other, but the semiconductor chip on the lower surface is connected to the stepped portion, thereby stacking two or more semiconductor chips to minimize the thickness and area, thereby expanding the integrated capacity For that purpose.
상기 목적을 달성하기 위하여 본 발명의 반도체 칩 적층형 반도체 패키지는,In order to achieve the above object, the semiconductor chip stacked semiconductor package of the present invention,
서로 대향하는 선단부에 단차가 발생되도록 일부가 제거된 단차부(21)를 포함하는 리드(20)와, A lead 20 including a stepped portion 21 in which portions are removed such that a step is generated at opposite ends thereof;
상기 리드(20)의 하부에 부착되며 표면 중앙에 전기접속되는 센터 패드(22a)를 구비한 제 1 반도체 칩(22)과,A first semiconductor chip 22 attached to the lower part of the lid 20 and having a center pad 22a electrically connected to the center of the surface thereof;
상기 리드(20)의 상부에 설치되며 표면 가장자리에 전기접속되는 사이드 패드(23a)를 구비한 제 2 반도체 칩(23)과, A second semiconductor chip 23 mounted on the lead 20 and having side pads 23a electrically connected to surface edges thereof;
상기 제 1 및 제 2 반도체 칩(22)(23)과 리드(20)를 전기 접속시키는 접속부재(24)와,A connection member 24 for electrically connecting the first and second semiconductor chips 22 and 23 to the lead 20;
상기 각 접속부재(24)와 상기 제 1, 제 2 반도체 칩(22)(23) 중 적어도 어느 하나의 반도체 칩의 상면 또는 하면이 노출되도록 하면서 봉지하는 봉지재(26)와,An encapsulant 26 encapsulating the upper and lower surfaces of at least one of the connection members 24 and the at least one semiconductor chip 22 and 23, respectively, and being encapsulated;
상기 리드(20)의 전기 신호를 외부로 인출하는 외부인출단자(25)를 포함하는 구성으로 이루어진다. It consists of a configuration including an external drawing terminal 25 for drawing the electrical signal of the lead 20 to the outside.
본 발명의 구성에 대하여 첨부한 도면을 참조하면서 보다 상세하게 설명한다. The structure of this invention is demonstrated in detail, referring an accompanying drawing.
도 2 는 본 발명에 의한 반도체 칩 적층형 반도체 패키지의 일실시예를 도시한 단면도이고 도 3 은 상기 실시예의 패키지를 상면에서 투영한 투영도이다. 2 is a cross-sectional view showing an embodiment of a semiconductor chip stacked semiconductor package according to the present invention, and FIG. 3 is a projection view projecting the package of the embodiment from an upper surface thereof.
도 2 와 도 3 을 참조하면, 상기 반도체 칩 적층형 반도체 패키지는 대략 중앙에서 사방으로 대향되어 있으며, 상기 대향된 선단부의 상단 일부가 제거되어 단차를 이루고 있는 단차부(21)가 구비된 리드(20)와, 상기 리드(20) 의 하면에 부착되는 제 1 반도체 칩(22)과, 상기 리드(20)의 상면에 부착되는 제 2 반도체 칩(23)과, 상기 제 1 및 제 2 반도체 칩(22)(23)과 리드(20)를 접속시키는 접속부재(24)와, 상기 제 1 또는 제 2 반도체 칩(23) 및 접속부재(24)와 리드(20)의 일부를 봉지하는 봉지재(26)와, 상기 리드(20)의 전기신호를 외부로 인출하여 입출력이 가능하도록 하는 외부인출단자(25)로 크게 이루어진다. Referring to FIGS. 2 and 3, the semiconductor chip stack-type semiconductor package is substantially opposite from each other in all directions, and a lead 20 having a step portion 21 having a stepped portion formed by removing a portion of an upper end portion of the opposite tip portion is formed. ), A first semiconductor chip 22 attached to a lower surface of the lead 20, a second semiconductor chip 23 attached to an upper surface of the lead 20, and the first and second semiconductor chips ( 22 and 23, a connecting member 24 for connecting the lead 20, and an encapsulant for encapsulating a portion of the first or second semiconductor chip 23 and the connecting member 24 and the lead 20 ( 26) and an external drawing terminal 25 for drawing the electrical signal of the lead 20 to the outside to enable input and output.
이하 상기 본 발명의 일실시예를 보다 상세하게 설명한다. Hereinafter, an embodiment of the present invention will be described in more detail.
상기 구성부품 중 리드(20)는 도전성 금속재로서, 통상의 두께가 대략 8mil 이하로 제조된다. 상기 리드(20)는 도 2 및 도 3에서 보는 바와 같이, QFP인 경우 양측 사방으로 중앙에서 소정 이격되어 위치하고 있으며, 각 방향마다 일렬로 배열되어 있다.Among the components, the lid 20 is a conductive metal material, and is manufactured to a thickness of about 8 mil or less in general. 2 and 3, in the case of the QFP, the leads 20 are spaced apart from each other in the center at both sides, and are arranged in a line in each direction.
상기 리드(20)는 중앙부에 각 리드(20)의 선단부가 서로 마주보고 있는 이격부(27)가 형성되어 있는바, 상기 이격부(27)에서 서로 대향된 리드(20)는 선단부에 단차가 형성된 단차부(21)를 구비하고 있다. 상기 단차부(21)는 반 에칭(half etching)법으로 형성할 수 있으며, 또한 블레이드로 절단내지 스탬핑으로 압착시킬 수도 있다. The lead 20 has a spaced portion 27 in which the tip portions of the leads 20 face each other at a central portion thereof. The formed step part 21 is provided. The step portion 21 may be formed by a half etching method, or may be pressed by cutting or stamping with a blade.
상기 리드(20)의 배면에는 제 1 반도체 칩(22)이 부착되는데, 상기 제 1 반도체 칩(22)과 리드(20)는 접착제를 매개물로 하여 부착된다. 상기 제 1 반도체 칩(22)은 중앙부에 복수의 접속가능한 센터 패드(center pad)를 구비하고 있어 상기 센터 패드(22a)와 리드(20)의 단차부(21) 표면 간에는 접속부재(24)로 통전된다. 상기 접속부재(24)는 금속 세선인 전도성 와이어(242)를 사용하는바, 통상 전도성이 뛰어난 알루미늄, 구리 또는 골드 와이어(242)를 사용한다. The first semiconductor chip 22 is attached to the rear surface of the lead 20, and the first semiconductor chip 22 and the lead 20 are attached using an adhesive as a medium. The first semiconductor chip 22 has a plurality of connectable center pads in a central portion thereof, and is connected to the connection member 24 between the center pad 22a and the surface of the step portion 21 of the lid 20. It is energized. The connection member 24 uses a conductive metal wire 242, which is a fine metal wire, and typically uses aluminum, copper, or gold wire 242 having excellent conductivity.
상기 전도성 와이어(242) 제 2 반도체 칩과 접촉하지 않을 정도로 설치하는 것이 바람직하다. The conductive wire 242 may be disposed so as not to contact the second semiconductor chip.
상기 리드(20)의 상면에는 접착제를 개재하여 제 2 반도체 칩(23)이 부착되는바, 상기 제 2 반도체 칩(23)은 접속패드가 가장자리에 형성된 사이드 패드나 중앙에 형성된 센터 패드 모두 가능하지만 상기 실시예에서는 사이드 패드를 구비한 상태를 도시하였고, 상기 접속패드와 리드(20)의 상면에서 역시 접속부재(24)인 전도성 와이어(242)로 접속된다. The second semiconductor chip 23 is attached to the upper surface of the lead 20 through an adhesive. The second semiconductor chip 23 may be a side pad formed at an edge thereof or a center pad formed at the center thereof. In the above embodiment, the state with the side pads is illustrated, and the connection pads are connected with the conductive wires 242 which are also connection members 24 on the upper surfaces of the leads 20.
상기 전도성 와이어(242)는 극히 미세한 와이어(242)이기 때문에 공기중에 노출되면 쉽게 산화되거나, 적은 충격에도 와이어(242)가 끊어질 수 있다. 이를 방지하기 위해 와이어(242)가 설치된 부분은 외관을 봉지하여 그 안전성을 도모하게 되는바, 통상 EMC(Epoxy Mold Compound)로 몰딩한다. Since the conductive wire 242 is an extremely fine wire 242, it may be easily oxidized when exposed to air, or the wire 242 may be broken even with a small impact. In order to prevent this, the portion in which the wire 242 is installed is encapsulated to promote safety, and is usually molded with an epoxy mold compound (EMC).
상기 리드(20)의 배면 양쪽 단부에는 상기 반도체 패키지를 실장하는 마더 보드와 입출력되는 전기신호를 교환할 수 있도록 외부인출단자(25)가 형성되어 있다. 상기 외부인출단자(25)는 리드(20)를 연장하여 하방으로 절곡 설치할 수 있고, 솔더 범프(25)를 별도로 융착시킬 수도 있다. External lead terminals 25 are formed at both ends of the rear surface of the lid 20 so as to exchange electrical signals to and from the motherboard mounting the semiconductor package. The external lead-out terminal 25 may be installed to bend downward by extending the lead 20, and may separately weld the solder bumps 25.
본 발명에서는 솔더 범프(25)를 채용하여 상기 반도체 패키지를 마더 보드에 바로 실장할 수 있도록 하며 후술되는 패키지의 적층구조에서도 별도의 공정없이 바로 패키지와 패키지가 적층되기 용이하도록 하였다. In the present invention, the solder bumps 25 are used to directly mount the semiconductor package on the mother board, and the package and the package may be easily stacked without a separate process even in a laminate structure of the package described later.
도 3을 다시 참조하면, 상기 도면은 도 2 의 반도체 패키지의 상면에서 투영한 투영도로서, 상기 본 발명에 의한 반도체 칩 적층형 패키지는 제 1 반도체 칩(22)과 제 2 반도체 칩(23)의 리드(20) 접속상태에 따라 구분될 수 있는바, 그 일례를 도시하였다. Referring to FIG. 3 again, the drawing is a projection view projected from the upper surface of the semiconductor package of FIG. 2, wherein the semiconductor chip stack package according to the present invention is a lead of the first semiconductor chip 22 and the second semiconductor chip 23. (20) bar can be classified according to the connection state, an example thereof is shown.
도 2 의 단면도에서 보는 바와 같이 만일 제 1 반도체 칩(22)과 제 2 반도체 칩(23)의 기능이 동일하다면, 예를 들어 메모리 용량의 증가를 위하여 제 2 반도체 칩(23)이 적층되어 있는 경우라면, 하나의 리드(20)에 상기 제 1 반도체 칩(22)과 제 2 반도체 칩(23)이 모두 접속되어도 무방하다. As shown in the cross-sectional view of FIG. 2, if the functions of the first semiconductor chip 22 and the second semiconductor chip 23 are the same, for example, the second semiconductor chip 23 is stacked to increase the memory capacity. In this case, both the first semiconductor chip 22 and the second semiconductor chip 23 may be connected to one lead 20.
그러나 도 3 에 도시한 경우처럼 제 1 반도체 칩(22)과 제 2 반도체 칩(23)이 각각 서로 다른 기능을 하는 경우에는 제 1 반도체 칩(22)이 접속되는 리드(20)와 제 2 반도체 칩(23)이 접속되는 리드(20')가 서로 상이해야한다. However, as shown in FIG. 3, when the first semiconductor chip 22 and the second semiconductor chip 23 have different functions from each other, the leads 20 and the second semiconductor to which the first semiconductor chip 22 is connected are connected. The leads 20 'to which the chips 23 are connected should be different from each other.
도 3 과 같이 구성함으로써 본 발명에 사용되는 제 1 반도체 칩(22)과 제 2 반도체 칩(23)은 서로 동일한 기능의 반도체 칩 뿐 아니라 각각 개별 작용이 가능한 반도체 칩을 적층할 수 있어 멀티 기능을 구비할 수 있다.As shown in FIG. 3, the first semiconductor chip 22 and the second semiconductor chip 23 used in the present invention can stack not only a semiconductor chip having the same function but also a semiconductor chip that can be individually operated. It can be provided.
또한, 상기 제 1 반도체 칩과 제 2 반도체 칩은 서로 동일한 사이즈를 가질 때 뿐 아니라 서로 다른 사이즈라도 본 발명의 목적을 구현하는 데는 무방하다. The first semiconductor chip and the second semiconductor chip may have the same size. Different sizes as well as time may be used to implement the object of the present invention.
도 4 는 본 발명에 의한 반도체 칩 적층형 반도체 패키지의 제 2 실시예를 도시한 단면도이다. 4 is a cross-sectional view showing a second embodiment of a semiconductor chip stacked semiconductor package according to the present invention.
도면을 참조하면, 상기 반도체 패키지는 도 1의 반도체 패키지와 거의 유사한 구조에, 제 2 반도체 칩(23)과 리드(20)와의 접속부재(24)로서 전도성 와이어(242)를 사용하지 않고 솔더 범프(244) 또는 솔더 볼로 직접 리드(20)에 융착접속한 플립 칩 본딩(flip chip bonding)을 채용한 구조를 도시하였다. Referring to the drawings, the semiconductor package has a structure substantially similar to that of the semiconductor package of FIG. 1, and does not use the solder bumps as the connection member 24 between the second semiconductor chip 23 and the lead 20 without using the solder bumps. (244) or a structure employing flip chip bonding in which the solder ball is directly fused and connected to the lead 20 is shown.
상기 플립 칩 본딩은, 반도체 칩이 소형화될수록 더 조밀한 패드에 인터커넥션을 해야하는데 기존의 와이어(242) 본딩 방식으로는 이것을 구현하기 힘들어 이를 대체하는 솔더 범프 (Solder Bumps) 방식이 개발되었고, 상기 솔더 범프 방식은 칩의 패드 위에 솔더 범프(244)를 형성시킨 후 칩을 뒤집어서 PCB나 리드 프레임, 회로 테이프(circuit tape)의 회로 패턴에 직접 붙히는 방법이다. In the flip chip bonding, as semiconductor chips become smaller, interconnections are made to more dense pads. However, solder bumps have been developed to replace them by the conventional wire 242 bonding method. The solder bump method is a method of forming a solder bump 244 on a pad of a chip and then inverting the chip and directly attaching the chip to a circuit pattern of a PCB, a lead frame, and a circuit tape.
도 5 는 본 발명에 의한 반도체 칩 적층형 반도체 패키지의 제 3 실시예로서, 도 2 또는 도 4 의 반도체 패키지보다 그 높이를 축소시킨 반도체 패키지의 단면도이다. FIG. 5 is a cross-sectional view of a semiconductor package having a height smaller than that of FIG. 2 or 4 as a third embodiment of the semiconductor chip stacked semiconductor package according to the present invention.
도면에서 보는 바와 같이, 상기 반도체 패키지는 봉지재(26)의 높이를 제 2 반도체 칩(23)의 높이와 같게 하고, 상기 제 2 반도체 칩(23)의 상면이 외부로 노출되도록 함으로써 제 1 반도체 칩(22)과 마찬가지로 방열성을 향상시킨 구조를 갖는다. As shown in the figure, the semiconductor package has a height of the encapsulant 26 equal to that of the second semiconductor chip 23 and the upper surface of the second semiconductor chip 23 is exposed to the outside to allow the first semiconductor to be exposed. Like the chip 22, it has a structure in which heat dissipation is improved.
도 2 내지 도 5 의 반도체 패키지는 제 1 반도체 칩(22)이 접착제에만 의존하여 리드(20)의 배면에 부착되어 있으므로 이를 보완하기 위하여 도 6에 도시된 제 4 실시예와 같이 제 1 반도체 칩(22)의 측면을 둘러싸면서 봉지재(26)로 몰딩하게 되면, 리드(20)와 제 1 반도체 칩(22)의 결합력을 증대하여 보다 안정적인 반도체 패키지를 구현할 수 있다. In the semiconductor package of FIGS. 2 to 5, since the first semiconductor chip 22 is attached to the rear surface of the lead 20 depending only on the adhesive, the first semiconductor chip as shown in FIG. When molding the encapsulant 26 while surrounding the side surface of the substrate 22, the bonding force between the lead 20 and the first semiconductor chip 22 may be increased to implement a more stable semiconductor package.
아울러 도시하지는 않았으나 도 1에서 제 2 반도체 칩(23)의 상면이 몰딩된바와 같이 제 1 반도체 칩(22)의 전부가 봉지될 수 있는 구조를 채용하여 전체적인 반도체 패키지의 결합력을 증대시킴도 가능하다. Although not shown in FIG. 1, as shown in FIG. 1, the upper surface of the second semiconductor chip 23 may be molded to increase the bonding force of the entire semiconductor package by employing a structure in which the entirety of the first semiconductor chip 22 may be encapsulated. .
도 7 에는 상기 본 발명에 의한 반도체 칩 적층형 반도체 패키지를 적층시킨 상태를 도시하였다. 7 illustrates a state in which the semiconductor chip stacked semiconductor package according to the present invention is stacked.
도면을 참조하면, 상기 반도체 패키지의 리드(20) 단부에 설치된 외부 인출단자(25)는 그 높이가 리드(20)의 상면에 형성된 칩을 포함한 몰딩부와, 리드(20) 하면의 칩 두께를 포함한 높이보다 크도록 하면, 제 1 패키지와 제 2 패키지를 적층하였을 때 제 1 패키지의 상부 칩과 제 2 패키지의 하부 칩이 서로 겹치지 않고 소정의 공간을 사이에 두고 맞닿게 되므로 최소의 공간을 활용하면서 패키지를 적층시킬 수 있게 된다. Referring to the drawings, the external lead terminal 25 provided at the end of the lead 20 of the semiconductor package has a molding portion including a chip formed on an upper surface of the lead 20 and a chip thickness of the lower surface of the lead 20. If the height is greater than the included height, when the first package and the second package are stacked, the upper chip of the first package and the lower chip of the second package do not overlap each other, but contact with each other with a predetermined space therebetween, so that the minimum space is utilized. While stacking the packages can be.
도 8 은 본 발명에 의한 반도체 칩 적층형 반도체 패키지의 다른 실시예로서, 외부인출단자로써 솔더 범프나 솔더 볼과 같은 별도의 단자를 구성하지 않고 리드를 연장시켜 리드의 단부를 하방으로 일부 2중 절곡시켰으며, 또한, 제 2 반도체 칩이 센터 패드를 구비하여 상기 센터 패드와 리드간을 접속시킨 반도체 패키지이다. FIG. 8 illustrates another embodiment of the semiconductor chip stacked semiconductor package according to the present invention, wherein the lead is extended and partially bent downward of an end of the lead without forming a separate terminal such as solder bump or solder ball as an external lead terminal. Moreover, a 2nd semiconductor chip is a semiconductor package provided with the center pad, and connecting the said center pad and a lead.
이와 같이 상기 리드를 연장하여 2중 절곡함으로써 외부인출단자로서 사용이 가능하고, 제 2 반도체 칩은 센터 패드 또는 사이드 패드를 구비하더라도 와이어로 용이하게 접속이 가능하다. As described above, the lead can be extended and bent twice so that the lead can be used as an external lead-out terminal, and the second semiconductor chip can be easily connected with a wire even if it has a center pad or a side pad.
본 발명에 의한 반도체 칩 적층형 반도체 패키지는 두 개의 칩을 적층시키면서도 최소의 높이와 면적을 소모하게 되는 이점과 함께 적정한 크기의 외부인출단자(25)를 구비함으로써 도 7에 도시된 바와 같이 패키지를 적층하게 되면 현저한 용량 증대 및 멀티 기능을 구비할 수 있게 된다. The semiconductor chip stack type semiconductor package according to the present invention stacks the package as shown in FIG. 7 by providing an external lead terminal 25 of an appropriate size with the advantage of consuming the minimum height and area while stacking two chips. This can provide a significant capacity increase and multi-function.
2개 이상의 반도체 칩을 적층할 때 단차부를 갖는 리드를 채용하여 상기 단차부에서 반도체 칩과 리드간을 접속시켜 접속부재가 차지하는 공간을 최소화함으로써 경박단소한 CSP(Chip Size Package)를 구현할 수 있으며, 상기 패키지 위에 같은 방식으로 제조된 패키지를 기타 공정없이 바로 적층시켜 사용할 수 있다. When stacking two or more semiconductor chips, a lead having a stepped portion is employed to connect the semiconductor chip and the lead in the stepped portion to minimize the space occupied by the connection member, thereby implementing a light and simple chip size package (CSP). Packages prepared in the same manner on the package can be directly stacked and used without other processes.
또한, 제조단가가 비교적 저렴한 리드 프레임을 통전부재로 사용하며, 기존의 MLF(micro lead frame)의 구조 및 제조방법이 유사하여 기존 공정시설을 활용할 수 있으므로 생산적용성 측면에서도 유리하다. In addition, a lead frame with a relatively low manufacturing cost is used as the energizing member, and the structure and manufacturing method of the existing MLF (micro lead frame) are similar, so that the existing process facilities can be utilized, which is advantageous in terms of production applicability.
상기에서 본 발명의 특정한 실시 예가 설명 및 도시되었지만 본 발명이 당업자에 의해 다양하게 변형되어 실시될 가능성이 있는 것은 자명한 일이다.Although specific embodiments of the present invention have been described and illustrated above, it is obvious that the present invention may be variously modified and implemented by those skilled in the art.
이와 같이 변형된 실시 예들은 본 발명의 기술적 사상이나 전망으로부터 개별적으로 이해되어져서는 안되며, 이와 같은 변형된 실시 예들은 본 발명에 기술된 특허청구범위 안에 속한다 해야 할 것이다.Such modified embodiments should not be individually understood from the technical spirit or the prospect of the present invention, and such modified embodiments should fall within the claims described in the present invention.
도 1 은 종래 반도체 패키지를 도시한 단면도. 1 is a cross-sectional view showing a conventional semiconductor package.
도 2 는 본 발명에 의한 반도체 칩 적층형 반도체 패키지의 바람직한 일실시예를 도시한 단면도.Figure 2 is a cross-sectional view showing a preferred embodiment of a semiconductor chip stacked semiconductor package according to the present invention.
도 3 은 상기 도 2의 반도체 패키지를 상면에서 투영한 투영도.3 is a projection view of the semiconductor package of FIG. 2 projected from an upper surface thereof;
도 4 는 본 발명에 의한 반도체 칩 적층형 반도체 패키지의 제 2실시예를 도시한 단면도.4 is a cross-sectional view showing a second embodiment of a semiconductor chip stacked semiconductor package according to the present invention;
도 5 는 본 발명의 제 3 실시예를 도시한 단면도.5 is a sectional view showing a third embodiment of the present invention.
도 6 은 본 발명의 제 4 실시예를 도시한 단면도. 6 is a sectional view showing a fourth embodiment of the present invention;
도 7 은 본 발명의 반도체 칩 적층형 반도체 패키지를 적층구성한 단면도.7 is a cross-sectional view of the semiconductor chip stacked semiconductor package of the present invention in a stacked configuration.
도 8 은 본 발명에 관련된 반도체 칩 적층형 반도체 패키지의 다른 실시예를 도시한 도면. 8 is a view showing another embodiment of a semiconductor chip stacked semiconductor package according to the present invention.
** 도면의 주요 부분에 대한 부호의 설명 **** Description of symbols for the main parts of the drawing **
20: 리드 21: 리드의 단차부20: Lead 21: stepped portion of lead
22: 제 1 반도체 칩 23: 제 2 반도체 칩22: first semiconductor chip 23: second semiconductor chip
24: 접속부재 242: 전도성 와이어24: connecting member 242: conductive wire
244: 솔더범프 25: 외부인출단자244: solder bump 25: external drawing terminal
26: 봉지재26: Encapsulant
Claims (12)
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0429363A (en) * | 1990-05-24 | 1992-01-31 | Mitsubishi Electric Corp | Semiconductor device |
| JPH06244360A (en) * | 1993-02-17 | 1994-09-02 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| KR19980054346A (en) * | 1996-12-27 | 1998-09-25 | 문정환 | Semiconductor Device Stacked Semiconductor Package |
| KR20000034120A (en) * | 1998-11-27 | 2000-06-15 | 윤종용 | Multi-chip package of loc type and method for manufacturing multi-chip package |
| KR20010036630A (en) * | 1999-10-11 | 2001-05-07 | 윤종용 | Stack chip package |
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- 2001-02-14 KR KR10-2001-0007285A patent/KR100525450B1/en active IP Right Grant
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0429363A (en) * | 1990-05-24 | 1992-01-31 | Mitsubishi Electric Corp | Semiconductor device |
| JPH06244360A (en) * | 1993-02-17 | 1994-09-02 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| KR19980054346A (en) * | 1996-12-27 | 1998-09-25 | 문정환 | Semiconductor Device Stacked Semiconductor Package |
| KR20000034120A (en) * | 1998-11-27 | 2000-06-15 | 윤종용 | Multi-chip package of loc type and method for manufacturing multi-chip package |
| KR20010036630A (en) * | 1999-10-11 | 2001-05-07 | 윤종용 | Stack chip package |
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