KR19980022344A - Stacked BGA Semiconductor Package - Google Patents
Stacked BGA Semiconductor Package Download PDFInfo
- Publication number
- KR19980022344A KR19980022344A KR1019960041464A KR19960041464A KR19980022344A KR 19980022344 A KR19980022344 A KR 19980022344A KR 1019960041464 A KR1019960041464 A KR 1019960041464A KR 19960041464 A KR19960041464 A KR 19960041464A KR 19980022344 A KR19980022344 A KR 19980022344A
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- South Korea
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- bga
- semiconductor package
- bga semiconductor
- pcb
- printed circuit
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
본 발명은 BGA형 반도체패키지에 대한 것으로, 더욱 상세하게는 BGA형 반도체패키지를 다수개 결합 구성한 적층형 BGA 반도체패키지에 대한 것이다.The present invention relates to a BGA type semiconductor package, and more particularly, to a stacked type BGA semiconductor package in which a plurality of BGA type semiconductor packages are combined.
본 발명에서는 종래 일반 BGA 반도체패키지가 갖는 열방출 문제 및 인쇄회로기판(PCB′)의 크기 제한으로 인한 입출력단자의 설치 제한 문제의 해결을 위하여 사각형태의 인쇄회로기판(PCB) 중앙면에 반도체칩(IC)을 부착하고 콤파운드수지물로 몰드성형하여 하단 BGA 반도체패키지(BGA)를 구성하고, 상기 하단 BGA 반도체패키지(BGA)의 상면에 열방출용 히트싱크(HS)를 구비한 상단 BGA 반도체패키지 (BGA′)를 적층 접합시켜 적층형 BGA 반도체패키지를 구성함으로써, 멀티칩 모듈(MCM)효과와 열방출효과를 갖도록 하여 종래 BGA 반도체패키지에 비해 입출력(I/O)단자수를 배가시킬 수 있도록 한 것이다.In the present invention, in order to solve the problem of heat dissipation of the conventional BGA semiconductor package and the installation limitation of the input and output terminal due to the size limitation of the printed circuit board (PCB '), the semiconductor chip on the center of the rectangular printed circuit board (PCB) (IC) attached and molded into a compound resin to form a lower BGA semiconductor package (BGA), and the upper BGA semiconductor package having a heat dissipation heat sink (HS) on the upper surface of the lower BGA semiconductor package (BGA). By stacking and bonding (BGA ') to form a stacked type BGA semiconductor package, it has a multi-chip module (MCM) effect and a heat dissipation effect to double the number of input / output (I / O) terminals compared to conventional BGA semiconductor packages. will be.
Description
본 발명은 BGA(Ball Grid Array)형 반도체패키지에 대한 것으로, 더욱 상세하게는 BGA형 반도체패키지를 다수개 적층시켜 입출력(I/O수) 단자수를 증가시킴과 동시에 대용랑화 및 처리속도의 극대화를 실현할 수 있는 적층형 BGA 반도체패키지에 관한 것이다.The present invention relates to a BGA (Ball Grid Array) type semiconductor package, and more specifically, to stack a plurality of BGA type semiconductor packages to increase the number of input / output (I / O) terminals and at the same time, maximize the large flux and processing speed. The present invention relates to a stacked BGA semiconductor package capable of realizing the present invention.
일반적으로 실장업계에서는 사방 옆면으로 리드(Lead)를 설치할 수 있는 납작한 형상의 반도체패키지인 QFP(Quad Flat Package) 제조기술이 널리 알려져 있다In general, the manufacturing industry is known for manufacturing a QFP (Quad Flat Package), a flat-shaped semiconductor package capable of installing leads on all sides.
그러나, 최근 전자기기의 소형화, 박형화, 다기능화에 따라 많은 양의 정보를 빠른 시간에 처리할 수 있는 고집적화된 반도체칩이 요구되고 그에 따라 많은 수의 입출력을 갖는 소형의 반도체패키지를 제조하는데 많은 노력을 쏟고 있다. 그렇지만 위의 QFP 기술에 의해서는 반도체패키지의 크기를 증대시키지 않는 한 많은 입출력(I/O수) 단자를 형성하는데에는 무리가 따르지 않을 수 없었다. 그래서, 리드피치(Lead Pitch) 0.3mm 이하의 가공기술을 극복하지 못한 채 연구만을 거듭하던 중 리드 대신 볼(Ball)을 이용하는 BGA 기술이 출현하여 하나의 패키지를 통해 무수히 많은 출력단자를 실장토록 하는데 성공을 거두었다.However, with the recent miniaturization, thinning, and multifunctionalization of electronic devices, a highly integrated semiconductor chip capable of processing a large amount of information in a short time is required, and accordingly, many efforts have been made to manufacture a small semiconductor package having a large number of input and output. Is pouring. However, the above QFP technology has been difficult to form many input / output (I / O) terminals unless the size of the semiconductor package is increased. Therefore, BGA technology, which uses balls instead of leads, has emerged while overcoming the processing technology of lead pitch less than 0.3mm, and mounts numerous output terminals through one package. Successful.
여기서, 수년전부터 반도체 시장에 투입되어 많은 화제를 일으켜 오고 있는 BGA반도체패키지의 기술에 대해 간략히 언급해 보면 우선 BGA 반도체패키지는 크게 2종류로 구분해 볼 수 있는데, 그 하나는 제1도에서 도시한 바와 같은 일반 BGA 반도체패키지(PBGA : 이하, 플라스틱 BGA 반도체패키지라고 함)로써 이 플라스틱 BGA 반도체패키지의 구조를 보면 다수의 회로패턴(CP)이 실장된 인쇄회로기판(PCB) 위에 반도체칩(IC)을 붙이고 이 반도체칩(IC)의 본드 패드와 인쇄회로기판(PCB)의 회로패턴(CP)을 와이어(W)로 본딩한 후, 반도체칩(IC)과 와이어(W)를 콤파운드수지물로 몰드성형하고 인쇄회로기판(PCB) 하면에 볼(BL)을 심어 입출력(I/O) 단자수를 증설할 수 있도록 한 것이며, 또 다른 하나는 제2도의 예시와 같이 반도체칩(IC)으로부터 발생되는 열의 외부 방출효과를 높일 수 있도록 한 것(SBGA : 이하, 슈퍼 BGA 반도체패키지라 함)으로 이 슈퍼 BGA 반도체패키지의 구조를 보면, 방열용 히트싱크(HS)의 일면에 중앙부가 뚫린 인쇄회로기판(PCB′)을 부착하고 상기 히트싱크(HS)의 하면 중앙에 반도체칩(IC′)을 붙이고 와이어(W′) 본딩을 한 다음 수지물로 코팅처리를 하고 인쇄회로기판(PCB′)에 볼(BL′)을 형성한 구조이다.Here, if we briefly talk about the technology of BGA semiconductor package that has been introduced to the semiconductor market for many years, it can be divided into two types of BGA semiconductor packages, one of which is shown in FIG. As a general BGA semiconductor package (PBGA: plastic BGA semiconductor package) as described above, the structure of this plastic BGA semiconductor package shows a semiconductor chip (IC) on a printed circuit board (PCB) on which a plurality of circuit patterns (CP) are mounted. Bonds the bond pad of the semiconductor chip (IC) and the circuit pattern (CP) of the printed circuit board (PCB) with a wire (W), and then molds the semiconductor chip (IC) and the wire (W) with a compound resin. Molding and planting balls BL on the lower surface of the printed circuit board (PCB) to increase the number of input and output (I / O) terminals, the other is generated from the semiconductor chip (IC) as shown in FIG. External heat release effect In order to increase the height (SBGA: hereinafter referred to as the super BGA semiconductor package), the structure of the super BGA semiconductor package includes a printed circuit board (PCB ′) having a central hole formed on one surface of the heat dissipation heat sink (HS). The semiconductor chip IC 'is attached to the center of the lower surface of the heat sink HS, the wire W' is bonded, coated with resin, and the ball BL 'is formed on the printed circuit board PCB'. It is a structure.
그러나, 종래의 플라스틱 BGA 반도체패키지(PBGA)의 경우는 입출력 단자수를 다수 설치할 수 있는 장점이 있지만 입출력수의 증가에 따른 열방출 문제를 해결할 수 없어 200개 이상의 입출력단자를 설치할 수 없는 단점이 있었다. 이에 비하여, 슈퍼 BGA 반도체패키지(SBGA)의 경우는 열방출 문제를 해결할 수 있어 동일 크기의 플라스틱 BGA 반도체패키지(PBGA)에 비해 입출력 단자수를 배가할 수 있는 장점이 있지만 이 슈퍼 BGA 반도체패키지(SBGA)의 경우는 구조상 볼(BL′)을 형성할 수 있는 부위가 한정되어 있어 더 많은 입출력단자를 증설하지 못하는 스페이스(Space)상의 문제가 있었다.However, the conventional plastic BGA semiconductor package (PBGA) has the advantage that the number of input and output terminals can be installed, but the problem of heat dissipation due to the increase in the number of input and output can not solve the problem that can not be installed more than 200 input and output terminals. . On the other hand, the super BGA semiconductor package (SBGA) can solve the heat dissipation problem, which can double the number of input and output terminals compared to the same size plastic BGA semiconductor package (PBGA), but this super BGA semiconductor package (SBGA) In the case of), there is a problem in the space that can not form more input and output terminals because the portion that can form the ball (BL ') is limited.
따라서, 본 발명에서는 상기와 같은 종래의 BGA 반도체패키지의 구조가 갖는 제결함을 감안하여 BGA 반도체패키지를 구성하되 적층형태로 구성함으로써 멀티칩 모듈(MCM)효과(PBGA와 SBGA가 갖는 각각의 기능을 공유할 수 있는 다기능효과)와 열방출효과를 갖도록 하여 입출력 단자수를 극대화하고 대용량화를 이룰 수 있도록 한 것이다.Therefore, in the present invention, in consideration of the defects of the conventional BGA semiconductor package structure as described above, the BGA semiconductor package is configured in a stacked form, so that each function of the multi-chip module (MCM) effect (PBGA and SBGA has a function). It has a multifunction effect that can be shared) and a heat dissipation effect to maximize the number of input / output terminals and achieve a large capacity.
도 1은 종래 일반 BGA 반도체패키지 구성도.1 is a configuration diagram of a conventional general BGA semiconductor package.
도 2는 종래 히트싱크층이 설치된 BGA 반도체패키지(슈퍼 BGA) 구성도.2 is a configuration diagram of a BGA semiconductor package (super BGA) in which a conventional heat sink layer is installed.
도 3은 본 발명을 구성하는 하층부의 상면 구성도.Figure 3 is a top configuration diagram of the lower layer part constituting the present invention.
도 4은 본 발명의 적층형 BGA 반도체패키지 구성도.Figure 4 is a block diagram of a laminated BGA semiconductor package of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
BGA : 하단 BGA 반도체패키지 BGA′: 상단 BGA 반도체패키지BGA: Bottom BGA Semiconductor Package BGA ′: Top BGA Semiconductor Package
IC, IC′: 반도체칩 M : 몰드성형된 부분IC, IC ′: Semiconductor chip M: Molded part
M′: 코팅된 부분 PCB, PCB′: 인쇄회로기판M ′: Coated Part PCB, PCB ′: Printed Circuit Board
W, W′: 와이어 BL, BL′: 볼W, W ′: Wire BL, BL ′: Ball
T : 접속단자 CP : 회로패턴T: Connection terminal CP: Circuit pattern
HS : 히트싱크HS: Heat Sink
상기와 같은 목적을 달성하기 위한 본 발명의 적층형 BGA 반도체패키지는 다음과 같은 특징을 제공한다.Laminated BGA semiconductor package of the present invention for achieving the above object provides the following features.
사각형태의 인쇄회로기판(PCB) 중앙면에 반도체칩(IC)을 부착하고 콤파운드수지물로 몰드성형하여 하단 BGA 반도체패키지(BGA)를 구성하고, 상기 하단 BGA 반도체패키지(PBGA)의 상면에 열방출용 히트싱크(HS)를 구비한 상단 BGA 반도체패키지(BGA′)를 적층 접합시킴으로써 한정된 면적의 인쇄회로기판(PCB)에 입출력 단자수를 극대화할 수 있도록 하여 크기는 소형이면서도 대용량화 및 처리속도의 고속화를 실현할 수 있는 BGA 반도체패키지를 제공하게 되는 것이다.A semiconductor chip (IC) is attached to the center of a rectangular printed circuit board (PCB) and molded into a compound resin to form a lower BGA semiconductor package (BGA), and a column is formed on the upper surface of the lower BGA semiconductor package (PBGA). By stacking and bonding the top BGA semiconductor package (BGA ') with the heat sink (HS) for emission, the number of input and output terminals can be maximized to a limited area printed circuit board (PCB). It is to provide a BGA semiconductor package that can realize high speed.
〈실시예〉<Example>
이하, 본 발명의 적층형 BGA 반도체패키지의 제조방법 및 구조에 대하여 일예시 도면을 통해 상세히 설명하면 다음과 같다.Hereinafter, a method and a structure of a stacked BGA semiconductor package according to the present invention will be described in detail with reference to the following drawings.
도 3은 본 발명의 하층부를 구성하는 하단 BGA 반도체패키지(BGA)의 상면 구성을 나타낸 구성도이고, 도 4는 도 3의 하단 BGA 반도체패키지 위에 열방출용 히트싱크(HS)를 구비한 상단 BGA 반도체패키지(BGA′)를 적층시켜 전기적인 접속이 이루어지도록 한 단면구성도를 나타낸 것이다.Figure 3 is a block diagram showing the top configuration of the lower BGA semiconductor package (BGA) constituting the lower layer of the present invention, Figure 4 is a top BGA having a heat dissipation heat sink (HS) on the lower BGA semiconductor package of Figure 3 Fig. 1 shows a cross-sectional configuration diagram in which a semiconductor package (BGA ') is laminated to allow electrical connection.
본 발명의 하층부를 이루는 하단 BGA 반도체패키지(BGA)는 회로패턴(CP)이 인쇄된 인쇄회로기판(PCB)의 중앙 부분에 반도체칩(IC)이 부착되는데 이 반도체칩(IC)은 와이어(W)에 의해 인쇄회로기판(PCB)에 인쇄된 회로패턴(CP)에 본딩되며, 상기 반도체칩(IC)과 와이어(W)는 콤파운드수지물에 의해 얇은 두께로 몰드성형되는데 이 부분이 몰드성형된 부분(M)이다.The lower BGA semiconductor package BGA constituting the lower layer of the present invention is a semiconductor chip (IC) is attached to the center portion of the printed circuit board (PCB) printed circuit pattern (CP), the semiconductor chip (IC) is a wire (W) Bonded to a circuit pattern CP printed on a printed circuit board (PCB), and the semiconductor chip (IC) and the wire (W) are molded in a thin thickness by a compound resin. Part (M).
그리고, 이 몰드성형된 부분(M)을 제외한 나머지 상면 부분에는 후술하는 상단 BGA 반도체패키지(BGA′)의 볼(BL′)이 접속되는 접속단자(T)가 형성되며, 인쇄회로기판(PCB)의 하면에는 입출력단자를 구성하는 많은 갯수의 솔더볼(BL)이 형성되는 구성을 하고 있다.In addition, a connection terminal T to which the balls BL 'of the upper BGA semiconductor package BGA', which will be described later, are connected, is formed on the remaining upper surface portions except for the molded portion M, and a printed circuit board PCB. In the lower surface, a large number of solder balls BL forming the input / output terminals are formed.
이렇게, 본 발명의 하층부를 이루는 플라스틱 BGA 반도체패키지(BGA)가 완성되면 그 위에 열방출용 히트싱크(HS)를 구비한 상단 BGA 반도체패키지(BGA′)를 적층 접속시키게 되는데, 이때 상단 BGA 반도체패키지(BGA′)의 인쇄회로기판(PCB′)에 형성된 볼(BL′)이 하단 BGA 반도체패키지(BGA)를 구성하는 인쇄회로기판(PCB)의 상면에 형성된 접속단자(T)에 접속되어 전기적으로 도통된 상태를 유지하게 되고, 또한 상단 BGA 반도체패키지(BGA′)의 수지물로 코팅된 부분(M′)과 하단 BGA 반도체패키지(BGA)의 몰드성형된 부분(M)은 열전도성이 우수한 접착물질에 의해 접착된다. 여기서, 상단 BGA 반도체패키지(BGA′)를 구성하는 수지물로 코팅된 부분(M′)을 인쇄회로기판(PCB′)의 하면보다 낮게 형성하게 되면 하단 BGA 반도체패키지(BGA)의 몰드성형된 부분(M)의 돌출높이를 수용할 수 있어 볼(BL′)과 접속단자(T)의 접속성을 좋게 할 수가 있는 것이다.Thus, when the plastic BGA semiconductor package (BGA) forming the lower layer of the present invention is completed, the upper BGA semiconductor package (BGA ′) having a heat dissipation heat sink (HS) is stacked thereon, wherein the upper BGA semiconductor package The ball BL 'formed on the printed circuit board PCB of the BGA' is electrically connected to the connection terminal T formed on the upper surface of the printed circuit board PCB constituting the lower BGA semiconductor package BGA. The conductive state is maintained, and the resin-coated portion M ′ of the upper BGA semiconductor package BGA ′ and the molded portion M of the lower BGA semiconductor package BGA have excellent thermal conductivity. Bonded by the material. Here, when the portion M 'coated with the resin constituting the upper BGA semiconductor package BGA' is lower than the lower surface of the printed circuit board PCB, the molded portion of the lower BGA semiconductor package BGA is formed. The protrusion height of M can be accommodated, and the connection between the ball BL 'and the connection terminal T can be improved.
따라서, 하단 BGA 반도체패키지(BGA)와 상단 BGA 반도체패키지(BGA′)와의 연결 접속이 가능하게 되어 대용량화가 가능하고, 또한 반도체칩(IC)(IC′)에서 발생하는 열을 히트싱크층(HS)을 통해 외부로 쉽게 방출할 수 있어 처리속도의 고속화를 실현할 수 있는 것이다.Therefore, the connection between the lower BGA semiconductor package (BGA) and the upper BGA semiconductor package (BGA ') becomes possible, thereby enabling a large capacity, and heat-sink layer (HS) for heat generated from the semiconductor chip (IC'). It can be easily discharged to the outside through) to realize the high speed of processing.
한편, 본 발명에서는 적층되는 BGA 반도체패키지수를 적절히 조절함으로써 다양한 기능과 용량의 변화를 갖는 BGA형 반도체패키지를 제공하게 되는 것이다.On the other hand, the present invention is to provide a BGA type semiconductor package having a variety of functions and changes in capacity by appropriately adjusting the stacked BGA semiconductor package index.
이와 같이, 본 발명에 의하면 히트싱크(HS)를 구비한 BGA 반도체패키지와 일반 BGA 반도체패키지를 결합 구성시킨 적층형의 새로운 BGA 반도체패키지를 제공하게 됨으로써, 멀티칩 모듈(MCM) 효과와 열방출 효과를 크게 높일 수 있어 종래 BGA 반도체패키지에 비해 입출력(I/O)단자수를 배가시키고, 기능의 다양화 및 용량의 극대화를 실현할 수 있는 효과를 제공하게 되는 것이다.As described above, according to the present invention, a multi-layered BGA semiconductor package including a BGA semiconductor package having a heat sink (HS) and a general BGA semiconductor package is provided to provide a multi-chip module (MCM) effect and heat dissipation effect. It is possible to greatly increase the number of input / output (I / O) terminals compared to the conventional BGA semiconductor package, and to provide the effect of realizing the diversity of functions and the maximization of capacity.
이상에서 설명한 것은 본 발명에 의한 적층형 BGA 반도체패키지를 설명하기 위한 하나의 실시예에 불과한 것이며, 본 발명은 상기한 실시예에 한정되지 않고, 이하의 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능한 것이다.What has been described above is only one embodiment for explaining the stacked type BGA semiconductor package according to the present invention, and the present invention is not limited to the above-described embodiment, and the scope of the present invention as claimed in the following claims Without departing from the art, various modifications can be made by those skilled in the art.
Claims (4)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019960041464A KR100216893B1 (en) | 1996-09-21 | 1996-09-21 | Stacked bga semiconductor package |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019960041464A KR100216893B1 (en) | 1996-09-21 | 1996-09-21 | Stacked bga semiconductor package |
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| Publication Number | Publication Date |
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| KR19980022344A true KR19980022344A (en) | 1998-07-06 |
| KR100216893B1 KR100216893B1 (en) | 1999-09-01 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100460063B1 (en) * | 2002-05-03 | 2004-12-04 | 주식회사 하이닉스반도체 | Stack ball grid arrary package of center pad chips and manufacturing method therefor |
| KR100487135B1 (en) * | 1997-12-31 | 2005-08-10 | 매그나칩 반도체 유한회사 | Ball Grid Array Package |
| KR100575590B1 (en) * | 2003-12-17 | 2006-05-03 | 삼성전자주식회사 | Thermal emission type stack package and modules mounting the same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102105902B1 (en) | 2013-05-20 | 2020-05-04 | 삼성전자주식회사 | Stacked semiconductor package having heat slug |
-
1996
- 1996-09-21 KR KR1019960041464A patent/KR100216893B1/en not_active IP Right Cessation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100487135B1 (en) * | 1997-12-31 | 2005-08-10 | 매그나칩 반도체 유한회사 | Ball Grid Array Package |
| KR100460063B1 (en) * | 2002-05-03 | 2004-12-04 | 주식회사 하이닉스반도체 | Stack ball grid arrary package of center pad chips and manufacturing method therefor |
| KR100575590B1 (en) * | 2003-12-17 | 2006-05-03 | 삼성전자주식회사 | Thermal emission type stack package and modules mounting the same |
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|---|---|
| KR100216893B1 (en) | 1999-09-01 |
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