KR100480908B1 - method for manufacturing stacked chip package - Google Patents
method for manufacturing stacked chip package Download PDFInfo
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- KR100480908B1 KR100480908B1 KR10-2001-0087263A KR20010087263A KR100480908B1 KR 100480908 B1 KR100480908 B1 KR 100480908B1 KR 20010087263 A KR20010087263 A KR 20010087263A KR 100480908 B1 KR100480908 B1 KR 100480908B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
본 발명은 다수의 반도체 칩이 적층된 구조를 가진 적층 칩 패키지의 제조 방법에 관해 개시한다. The present invention relates to a method of manufacturing a stacked chip package having a structure in which a plurality of semiconductor chips are stacked.
개시된 본 발명의 적층 칩 패키지의 제조 방법은 제 1기판 상에 제 1적층 칩을 부착하는 단계와, 제 2기판 상에 제 2적층 칩을 부착하는 단계와, 제 1기판 상의 제 1적층 칩 상에 제 2적층 칩을 포함한 제 2기판을 부착하는 단계와, 제 1기판과 제 2기판을 연결하는 단계를 포함한다.The disclosed method of manufacturing a stacked chip package of the present invention comprises the steps of attaching a first stacked chip on a first substrate, attaching a second stacked chip on a second substrate, and on a first stacked chip on the first substrate. Attaching a second substrate including a second stacked chip to the first substrate; and connecting the first substrate and the second substrate to each other.
Description
본 발명은 반도체 패키지 제조 방법에 관한 것으로, 보다 상세하게는 다수의 반도체 칩이 적층된 구조를 가진 적층 칩 패키지의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor package, and more particularly, to a method for manufacturing a stacked chip package having a structure in which a plurality of semiconductor chips are stacked.
전자기기들의 경박단소화 추세에 따라 그의 핵심 소자인 패키지의 고밀도, 고실장화가 중요한 요인으로 대두되고 있으며, 또한 컴퓨터의 경우 기억 용량의 증가에 따른 대용량의 램(Random Access Memory ; RAM) 및 프레쉬 메모리(Flash Memory)와 같이 칩의 크기는 자연적으로 증대되지만 패키지는 상기의 요건에 따라 소형화되는 경향으로 연구되고 있다.With the trend toward thinner and shorter electronic devices, high-density and high-mounted packages are becoming an important factor.In the case of computers, a large amount of random access memory (RAM) and fresh memory as the storage capacity increases. Like the Flash Memory, the size of the chip grows naturally, but the package is being studied to be smaller in accordance with the above requirements.
여기서, 패키지의 크기를 줄이기 위해서 제안되어 온 여러 가지 방안 예를 들면, 복수개의 칩 또는 패키지를 실장된 적층 칩 패키지(Multi Chip Package ; MCP), 적층 칩 모듈(Multi Chip Module ; MCM) 등이 있으며, 주로 반도체 칩 및 패키지가 기판 상에 평면적인 배열 방법으로 실장되기 때문에 제작에 한계가 있었다.Here, various methods that have been proposed to reduce the size of a package include, for example, a multi chip package (MCP) and a multi chip module (MCM) in which a plurality of chips or packages are mounted. In particular, there are limitations in manufacturing the semiconductor chip and the package because they are mounted in a planar arrangement method on the substrate.
이러한 한계를 극복하기 위해서 동일한 기억 용량의 칩을 일체적으로 복수개 적층한 패키지 기술이 제안된 바 있으며, 이것을 통상 적층 칩 패키지(stacked chip package)라 통칭된다.In order to overcome this limitation, a package technology in which a plurality of chips having the same storage capacity are integrally stacked has been proposed, which is commonly referred to as a stacked chip package.
현재 전술된 적층 칩 패키지의 기술은 단순화된 공정으로 적층 칩 패키지의 제조 단가를 낮출 수 있으며, 또한 대량 생산등의 이점이 있는 반면, 칩의 크기증가에 따른 패키지의 내부 리드를 설계하는데 있어서 공간이 부족한 단점이 있다.At present, the above-described stacked chip package technology can reduce the manufacturing cost of the stacked chip package in a simplified process, and also has advantages such as mass production. There is a shortcoming.
도 1은 종래 기술에 따른 적층 칩 패키지의 제조 방법을 설명하기 위한 단면도이다.1 is a cross-sectional view illustrating a method of manufacturing a stacked chip package according to the prior art.
종래 기술에 따른 적층 칩 패키지(100)는, 도 1에 도시된 바와 같이, 기판(110)을 이용하여 복수개의 반도체 칩(120,130,140)이 평면적으로 실장되어 패키징된 구조를 갖는다.As illustrated in FIG. 1, the stacked chip package 100 according to the related art has a structure in which a plurality of semiconductor chips 120, 130, and 140 are mounted in a planar manner using a substrate 110.
상기 기판(110)의 상부면의 실장 영역에 접착제(114)에 의해 상기 각각의 반도체 칩(120,130,140)이 부착되어 있으며, 기판(110)에 부착된 면에 대하여 반대되는 면에 복수개의 본딩 패드(122,132,142)가 형성된 구조를 갖는다. 이때, 상기 각각의 반도체 칩(120,130,140)을 적층하게 되면 계단 형상으로 배열된다. 또한, 상기 본딩 패드(122,132,142)는 상기 반도체 칩(120,130,140) 상면의 가장자리 부분에 다수개 형성된다.Each of the semiconductor chips 120, 130, and 140 is attached to the mounting area of the upper surface of the substrate 110 by an adhesive 114, and a plurality of bonding pads are formed on a surface opposite to the surface attached to the substrate 110. 122, 132, 142 has a structure formed. In this case, when the semiconductor chips 120, 130, and 140 are stacked, they are arranged in a step shape. In addition, a plurality of bonding pads 122, 132, and 142 may be formed at edge portions of upper surfaces of the semiconductor chips 120, 130, and 140.
상기 본딩 패드(122,132,142)는 기판(110)의 상부면에 형성된 전도성 패턴(112)와 각각 대응되어 본딩 와이어(124,134,144)에 의해 전기적으로 연결된다.The bonding pads 122, 132, and 142 correspond to the conductive patterns 112 formed on the upper surface of the substrate 110, respectively, and are electrically connected by the bonding wires 124, 134, and 144.
그리고, 반도체 칩(120,130,140) 및 기판(110) 상부면에 형성된 전기적 연결 부분을 보호하기 위하여 에폭시 계열의 봉지 수지를 봉지하여 패키지 몸체(150)가 형성된다. In addition, the package body 150 is formed by encapsulating an epoxy-based encapsulating resin in order to protect the electrical connection portions formed on the semiconductor chips 120, 130, 140 and the upper surface of the substrate 110.
상기 기판(110)의 전도성 패턴(112)은 반도체 칩(120,130,140)과 솔더 볼(160)을 전기적으로 연결시키기 위한 배선층이다.The conductive pattern 112 of the substrate 110 is a wiring layer for electrically connecting the semiconductor chips 120, 130, and 140 to the solder balls 160.
반도체 칩(120,130,140)은 기판(110) 상부면에 형성된 회로 패턴에 의해 서로 전기적으로 연결되거나, 전도성 패턴(112)에 반도체 칩의 본딩 패드(12,22,32)가 동시에 본딩 와이어(124,134,144)와 본딩됨으로써 전기적으로 연결될 수도 있다.The semiconductor chips 120, 130, and 140 are electrically connected to each other by a circuit pattern formed on the upper surface of the substrate 110, or the bonding pads 12, 22, and 32 of the semiconductor chip are simultaneously connected to the bonding wires 124, 134, and 144 on the conductive pattern 112. It may be electrically connected by bonding.
그러나, 종래 기술에서는 본딩패드가 가장자리 부분에 위치된 반도체 칩의 경우에만 적용되고 본딩패드가 센터(center) 부분에 위치된 반도체 칩의 경우 적용되지 못하며, 또한 각각의 반도체 칩의 사이즈(size)가 동일한 경우에는 적용할 수 없는 문제점이 있었다.However, in the prior art, the bonding pad is applied only to the semiconductor chip located at the edge portion, the bonding pad is not applied to the semiconductor chip located at the center portion, and the size of each semiconductor chip is In the same case, there was a problem that could not be applied.
이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 센터 부분에 본딩 패드가 각각 형성되고 사이즈가 동일한 반도체 칩들을 다 수개 적층할 수 있는 적층 칩 패키지의 제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a stacked chip package in which a plurality of semiconductor chips having the same size and having bonding pads are formed in a center portion, respectively, and can be stacked. .
상기 목적을 달성하기 위해, 사이즈가 동일하고 각각의 제 1및 제 2센터패드가 구비된 제 1및 제 2적층칩들을 적층시켜 적층칩 패키지를 제조하는 방법에 있어서, 상기 제 1적층칩의 제 1센터패드에 제 1범프를 형성하는 단계와, 센터윈도우가 구비된 제 1기판 상에 접착제를 사용하여 상기 제 1적층칩의 제 1범프가 형성된 면을 부착시키는 단계와, 센터윈도우를 통해 노출된 제 1범프과 상기 제 1기판을 연결시키는 금속와이어를 형성하는 단계와, 제 2적층칩의 제 2센터패드에 제2범프를 형성하는 단계와, 제 2기판 상에 상기 제 2적층칩의 제 2범프가 형성된 면을 부착시키는 단계와, 제 1기판의 상기 제 1적층 칩이 부착된 이면에 상기 제 2기판의 제 2적층 칩이 부착된 이면을 부착시키는 단계와, 상기 결과의 제 1기판 및 제 2기판 사이에 구리패턴 및 도전성 핀 중 어느 하나를 개재시켜 이들을 연결시키는 단계와, 그로부터 얻어지는 결과물을 몰딩하여 몰딩체를 형성하는 단계와, 제 1기판의 제 1적층 칩이 부착된 면에 도전성 볼을 형성하는 단계를 포함한 것을 특징으로 한다. In order to achieve the above object, a method of manufacturing a stacked chip package by stacking first and second stacked chips having the same size and provided with respective first and second center pads, the first stacked chip 1) forming a first bump on the center pad, attaching a surface on which the first bump of the first laminated chip is formed using an adhesive on a first substrate provided with a center window, and exposing through a center window Forming a metal wire connecting the first bump to the first substrate, forming a second bump on a second center pad of the second stacked chip, and forming a second bump on the second substrate. Attaching a surface on which two bumps are formed, attaching a back surface on which a second stacked chip of the second substrate is attached to a back surface on which the first stacked chip of a first substrate is attached, and a first substrate of the result A copper pattern and conductive material between the second substrate Connecting them through any one of the fins, molding the resultant to form a molding, and forming conductive balls on the surface to which the first stacked chip of the first substrate is attached. It is done.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2b는 본 발명의 제 1실시예에 따른 제 1적층 칩의 단면도이고, 도 3은 본 발명의 제 1실시예에 따른 제 2적층 칩의 단면도이다.2A to 2B are cross-sectional views of a first stacked chip according to a first embodiment of the present invention, and FIG. 3 is a cross-sectional view of a second stacked chip according to a first embodiment of the present invention.
도 4a 내지 도 4d는 본 발명의 제 1실시예에 따른 적층 칩 패키지의 제조 방법을 설명하기 위한 단면도이다. 4A to 4D are cross-sectional views illustrating a method of manufacturing a stacked chip package according to a first embodiment of the present invention.
본 발명의 제 1실시예에 따른 적층 칩 패키지의 제조 방법은, 도 2a에 도시된 바와 같이, 먼저 제 1적층 칩(210) 센터 부분의 본딩 패드(미도시)에 제 1범프(212)를 형성한 후, 제 1인쇄회로기판(Printed Circuit Board)(200) 상에 접착제(202)를 사용하여 상기 제 1범프(212)를 포함한 제 1적층 칩(210)을 부착시킨다.In the method of manufacturing a stacked chip package according to the first embodiment of the present invention, as shown in FIG. 2A, first, a first bump 212 is applied to a bonding pad (not shown) of a center portion of a first stacked chip 210. After forming, the first stacked chip 210 including the first bumps 212 is attached to the first printed circuit board 200 using the adhesive 202.
이어서, 도 2b에 도시된 바와 같이, 금속 와이어(214)를 이용하여 상기 제 1적층 칩(210)의 제 1범프(212)를 제 1기판(200)에 본딩시킨다. Subsequently, as illustrated in FIG. 2B, the first bump 212 of the first stacked chip 210 is bonded to the first substrate 200 using the metal wire 214.
그 다음, 도 3에 도시된 바와 같이, 제 2적층 칩(310) 센터 부분의 본딩 패드(미도시)에 제 2범프(312)를 형성한 후, 상기 제 2범프가 형성된 제 2적층 칩(310)을 제 2기판(300) 상에 부착시킨다.Next, as shown in FIG. 3, after the second bumps 312 are formed on the bonding pads (not shown) of the center portion of the second stacked chip 310, the second stacked chips having the second bumps ( 310 is attached on the second substrate 300.
이 후, 도 4a에 도시된 바와 같이, 상기 제 1적층 칩(210)이 부착된 제 1기판(200) 상에 제 2접착제(400)를 이용하여 제 2적층 칩(310)이 부착된 제 2기판(300)을 부착시킨다.Subsequently, as illustrated in FIG. 4A, the second stacked chip 310 is attached to the first substrate 200 to which the first stacked chip 210 is attached using the second adhesive 400. 2 board 300 is attached.
이어서, 도 4b에 도시된 바와 같이, 구리 등의 도전 패턴(404)을 이용하여 제 1기판(200)과 제 2기판(300)을 연결한다.Subsequently, as illustrated in FIG. 4B, the first substrate 200 and the second substrate 300 are connected to each other using a conductive pattern 404 such as copper.
그 다음, 도 4c에 도시된 바와 같이, 상기 결과물을 몰딩하여 몰딩체(404)를 형성하고, 도 4d에 도시된 바와 같이, 제 1기판의 저면에 도전성 볼(406)을 부착한다.Next, as shown in FIG. 4C, the resultant is molded to form a molding 404, and as shown in FIG. 4D, the conductive balls 406 are attached to the bottom of the first substrate.
본 발명의 제 1실시예에서는 두개의 적층 칩을 부착하여 패키징한 것을 예로 하여 설명하였지만 상술한 방법과 동일하게 2개 이상의 적층 칩을 부착하여 패키징 할 수도 있다.In the first embodiment of the present invention, a package in which two stacked chips are attached and described is described as an example. However, two or more stacked chips may be attached and packaged in the same manner as described above.
도 5는 본 발명의 제 2실시예에 따른 적층 칩 패키지의 제조 방법을 설명하기 위한 단면도이다.5 is a cross-sectional view illustrating a method of manufacturing a stacked chip package according to a second embodiment of the present invention.
본 발명의 제 2실시예는, 도5에 도시된 바와 같이, 제 1실시예와 동일하며, 동일한 구조를 가진 제 1및 제 2적층 칩(500)(510) 센터 부분의 본딩 패드(미도시)에 각각 범프(502)(512)를 형성한 후, 패키징 처리한다. As shown in FIG. 5, the second embodiment of the present invention is the same as the first embodiment, and bonding pads (not shown) in the center portions of the first and second stacked chips 500 and 510 having the same structure. Bumps 502 and 512 are respectively formed in the package) and then packaged.
도 6는 본 발명의 제 3실시예에 따른 적층 칩 패키지의 제조 방법을 설명하기 위한 단면도이다.6 is a cross-sectional view for describing a method of manufacturing a stacked chip package according to a third embodiment of the present invention.
본 발명의 제 3실시예는, 도 6에 도시된 바와 같이, 제 1실시예와 동일하되, 도전 패턴 대신에 도전성 핀(612)을 이용하여 제 1기판(600)과 제 2기판(610)을 연결한다.As shown in FIG. 6, the third embodiment of the present invention is the same as the first embodiment, but instead of the conductive pattern, the first substrate 600 and the second substrate 610 using the conductive pins 612. Connect
이상에서 설명한 바와 같이, 본 발명에서는 센터 부분에 본딩 패드가 각각 형성되고 사이즈가 동일한 반도체 칩을 다 수개 적층하여 최소면적에서 메모리 밀도를 확장할 수 있다.As described above, in the present invention, a plurality of semiconductor chips each having bonding pads formed in the center and having the same size may be stacked to expand the memory density at the minimum area.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다. In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
도 1은 종래 기술에 따른 적층 칩 패키지의 제조 방법을 설명하기 위한 단면도.1 is a cross-sectional view for explaining a method for manufacturing a stacked chip package according to the prior art.
도 2a 내지 도 2b는 본 발명의 제 1실시예에 따른 제 1적층 칩의 단면도.2A to 2B are cross-sectional views of a first stacked chip according to a first embodiment of the present invention.
도 3은 본 발명의 제 1실시예에 따른 제 2적층 칩의 단면도.3 is a cross-sectional view of a second stacked chip according to a first embodiment of the present invention.
도 4a 내지 도 4d는 본 발명의 제 1실시예에 따른 적층 칩 패키지의 제조 방법을 설명하기 위한 단면도. 4A to 4D are cross-sectional views illustrating a method of manufacturing a stacked chip package according to a first embodiment of the present invention.
도 5는 본 발명의 제 2실시예에 따른 적층 칩 패키지의 제조 방법을 설명하기 위한 0단면도.5 is a cross-sectional view illustrating a method of manufacturing a stacked chip package according to a second embodiment of the present invention.
도 6는 본 발명의 제 3실시예에 따른 적층 칩 패키지의 제조 방법을 설명하기 위한 단면도.6 is a cross-sectional view illustrating a method of manufacturing a stacked chip package according to a third embodiment of the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
200, 300. 기판 210, 310. 적층 칩200, 300. Substrate 210, 310. Stacked Chip
202, 400. 접착제 212, 312. 범프202, 400.Adhesive 212, 312.Bump
214. 금속와이어 402. 금속 패턴 214. Metal Wires 402. Metal Patterns
404. 몰딩체 406. 도전성 볼404. Molded article 406. Conductive balls
Claims (4)
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11135713A (en) * | 1997-10-29 | 1999-05-21 | Mitsubishi Electric Corp | Semiconductor module |
| JP2000299433A (en) * | 1999-04-06 | 2000-10-24 | Kashin Senshin Denshi Kofun Yugenkoshi | Laminated type package frame |
| KR20010025861A (en) * | 1999-09-01 | 2001-04-06 | 윤종용 | Stack type chip scale semiconductor package |
| KR20010027266A (en) * | 1999-09-13 | 2001-04-06 | 윤종용 | Stack package |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11135713A (en) * | 1997-10-29 | 1999-05-21 | Mitsubishi Electric Corp | Semiconductor module |
| JP2000299433A (en) * | 1999-04-06 | 2000-10-24 | Kashin Senshin Denshi Kofun Yugenkoshi | Laminated type package frame |
| KR20010025861A (en) * | 1999-09-01 | 2001-04-06 | 윤종용 | Stack type chip scale semiconductor package |
| KR20010027266A (en) * | 1999-09-13 | 2001-04-06 | 윤종용 | Stack package |
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