KR20080067891A - Multi chip package - Google Patents

Multi chip package Download PDF

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Publication number
KR20080067891A
KR20080067891A KR1020070005363A KR20070005363A KR20080067891A KR 20080067891 A KR20080067891 A KR 20080067891A KR 1020070005363 A KR1020070005363 A KR 1020070005363A KR 20070005363 A KR20070005363 A KR 20070005363A KR 20080067891 A KR20080067891 A KR 20080067891A
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South Korea
Prior art keywords
semiconductor chip
circuit board
printed circuit
groove
chip
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KR1020070005363A
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Korean (ko)
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김기채
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주식회사 하이닉스반도체
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Priority to KR1020070005363A priority Critical patent/KR20080067891A/en
Publication of KR20080067891A publication Critical patent/KR20080067891A/en

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    • E—FIXED CONSTRUCTIONS
    • E04—BUILDING
    • E04F—FINISHING WORK ON BUILDINGS, e.g. STAIRS, FLOORS
    • E04F11/00—Stairways, ramps, or like structures; Balustrades; Handrails
    • E04F11/02—Stairways; Layouts thereof
    • E04F11/104—Treads
    • E04F11/16—Surfaces thereof; Protecting means for edges or corners thereof
    • E04F11/163—Protecting means for edges or corners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H01L2924/15156—Side view
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15158—Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159—Side view
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

A multi-chip package is provided to reduce a total height of a package by arranging semiconductor chips in grooves on one surface and the other surface of a printed circuit board. A printed circuit board(200) includes a first and second grooves(204,206), a ball land(228), and a first, second, and third electrode terminals(216,218,202). A first semiconductor chip(208) is arranged in the first groove and includes a plurality of first bonding pads connected electrically to at least one or more first electrode terminals. One or more second semiconductor chips(210) are arranged on the first semiconductor chip in a face-up method. A first metal wire(214) is used for connecting a second bonding pad of the semiconductor chip with the third electrode terminal. A controller semiconductor chip(212) is attached in the second groove in the face-up method and includes a plurality of third bonding pads connected electrically to the second electrode terminals of the printed circuit board. A sealant(226) is used for sealing one surface of the printed circuit board including the first metal wire and the first and second semiconductor chips and the other surface of the printed circuit board including the controller semiconductor chip.

Description

멀티 칩 패키지{Multi chip package}Multi chip package

도 1은 종래의 듀얼 다이 패키지를 도시한 단면도.1 is a cross-sectional view of a conventional dual die package.

도 2는 본 발명의 실시예에 따른 멀티 칩 패키지를 도시한 단면도.2 is a cross-sectional view showing a multi-chip package according to an embodiment of the present invention.

도 3은 본 발명의 다른 실시예에 따른 멀티 칩 패키지를 도시한 단면도.3 is a cross-sectional view showing a multi-chip package according to another embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

200, 300 : 인쇄회로기판 202, 302 : 제3전극단자200, 300: printed circuit board 202, 302: third electrode terminal

204, 304 : 제1홈 206, 306 : 제2홈204, 304: First groove 206, 306: Second groove

208, 308 : 제1반도체칩 210, 310 : 제2반도체칩208, 308: first semiconductor chip 210, 310: second semiconductor chip

212, 312 : 컨트롤러 반도체칩 214, 314 : 제1금속와이어212 and 312: controller semiconductor chip 214 and 314: first metal wire

216, 316 : 제1전극단자 218, 318 : 제2전극단자216, 316: first electrode terminal 218, 318: second electrode terminal

220, 320 : 접착제 222, 322 : 솔더범프220, 320 Adhesive 222, 322 Solder bump

224, 324 : 충진재 226, 326 : 봉지제224, 324: filling material 226, 326: sealing agent

228, 328 : 볼랜드 230, 330 : 솔더볼228, 328: Borland 230, 330: solder ball

332 : 제3홈 334 : 제4전극단자332: third groove 334: fourth electrode terminal

336 : 제3반도체칩 338 : 제4반도체칩336: third semiconductor chip 338: fourth semiconductor chip

340 : 제2금속와이어340: second metal wire

본 발명은 멀티 칩 패키지에 관한 것으로, 보다 자세하게는, 인쇄회로기판을 식각하여 서로 다른 이 종간의 반도체칩을 배치시킨 멀티 칩 패키지에 관한 것이다.The present invention relates to a multi-chip package, and more particularly, to a multi-chip package in which semiconductor chips of different types are arranged by etching a printed circuit board.

기존의 반도체 패키징 공정에서는 설계 회로가 인쇄된 칩의 금속 패드와 리드 프레임간의 정보 송수신을 위해 미세한 금속와이어로 본딩하는 작업이 이루어져 왔다.In the conventional semiconductor packaging process, a work of bonding a fine metal wire has been performed to transmit and receive information between a metal pad of a printed chip and a lead frame.

그러나 고성능 칩의 지속적인 발전으로, 패키지 대부분의 반도체 디바이스는 패키지에서 많은 수의 리드를 수용하고자 하였으나, 기존의 와이어 본딩 방식으로는 리드 수를 무한정 늘리는데 기술적인 한계가 야기되었다. 또한 칩 크기 축소, 열 방출 및 전기적 수행 능력 향상, 신뢰성 향상, 그리고, 가격저하 등의 요인들도 기존의 한계를 뛰어넘는 새로운 패키징 기술을 요구해 왔다.However, with the continuous development of high-performance chips, most semiconductor devices have tried to accommodate a large number of leads in a package, but the conventional wire bonding method has caused technical limitations in increasing the number of leads indefinitely. In addition, factors such as chip size reduction, improved heat dissipation and electrical performance, increased reliability, and lower prices have also demanded new packaging technologies that go beyond existing limits.

이에 따라 기존의 기술적 한계를 극복하고, 급변하는 전자 정보 통신 시대의 시장 상황에 부합될 수 있도록 기존의 와이어 본딩 방식은 범핑을 기초로 한 플립 칩 방식에 의해 상당 부분 대체되었다.Accordingly, the wire bonding method has been largely replaced by a flip chip method based on bumping to overcome the existing technical limitations and to meet the rapidly changing market conditions of the electronic information and telecommunications era.

도 1은 종래의 듀얼 다이 패키지를 도시한 단면도이다. 1 is a cross-sectional view of a conventional dual die package.

도시된 바와 같이, 중앙부에 캐버티를 구비한 인쇄회로기판(100) 상에 센터패드형의 제1반도체칩(104)이 접착제(102)를 매개로 페이스-다운 타입으로 부착되고, 상기 제1반도체칩(104)의 하면에는 센터패드형의 제2반도체칩(110)이 접착 제(106)를 매개로 페이스-업 타입으로 부착된다. As shown in the drawing, a center pad-type first semiconductor chip 104 is attached on the printed circuit board 100 having a cavity at the center thereof in a face-down type via the adhesive 102. A center pad type second semiconductor chip 110 is attached to the bottom surface of the semiconductor chip 104 in the face-up type via the adhesive 106.

그리고, 상기 제1반도체칩(104)의 본딩패드(도시안됨)는, 상기 인쇄회로기판(100)의 캐버티를 관통하는 제1금속와이어(108)에 의해 인쇄회로기판(100) 하면의 회로패턴(도시안됨)과 전기적으로 연결되고, 상기 제2반도체칩(110)의 본딩패드(도시안됨)는 제2금속와이어(112)에 의해 인쇄회로기판(100) 상면의 전극단자(118)와 전기적으로 연결된다. The bonding pad (not shown) of the first semiconductor chip 104 may be formed on the bottom surface of the printed circuit board 100 by a first metal wire 108 passing through the cavity of the printed circuit board 100. It is electrically connected to the pattern (not shown), the bonding pad (not shown) of the second semiconductor chip 110 and the electrode terminal 118 of the upper surface of the printed circuit board 100 by the second metal wire 112. Electrically connected.

또한, 상기 제1반도체칩(104)과 제2반도체칩(110) 및 제2금속와이어(112)를 포함한 인쇄회로기판(100) 상면과, 상기 제1금속와이어(108) 및 제1반도체칩(104) 전면부의 일부분을 포함하는 인쇄회로기판(100) 캐버티 부분이 EMC와 같은 봉지제(114)로 밀봉되고, 인쇄회로기판(100) 하면에 구비된 볼랜드(120)에는 실장 수단으로서의 솔더 볼(116)이 부착된 구조를 갖는다.In addition, an upper surface of the printed circuit board 100 including the first semiconductor chip 104, the second semiconductor chip 110, and the second metal wire 112, and the first metal wire 108 and the first semiconductor chip. The cavity portion of the printed circuit board 100 including a portion of the front portion is sealed with an encapsulant 114 such as EMC, and soldered as a mounting means is provided on the ball land 120 provided on the bottom surface of the printed circuit board 100. The ball 116 is attached.

그러나, 전술한 바와 같은 종래의 듀얼 다이 패키지는 전체 두께가 두꺼우므로, 패키지의 효율성을 높이기 위해 구성하는 다이 스택 패키지와 부합되지 못하는 어려움이 있다.However, since the conventional dual die package as described above has a thick overall thickness, there is a difficulty in matching with the die stack package configured to increase the efficiency of the package.

또한, 상부에 배치되는 센터패드형의 반도체칩 본딩패드와 인쇄회로기판 간의 전기적 연결을 위한 와이어 본딩시 상기 반도체칩의 본딩패드와 인쇄회로기판의 전극단자간의 다소 긴 이격 길이로 인하여, 긴(long) 와이어 본딩이 요구되어 패키지 밀도의 효율성 면에서 신뢰성이 떨어지고, 장비의 어려움을 야기시킨다.In addition, when the wire bonding for the electrical connection between the center pad-type semiconductor chip bonding pad disposed on the upper portion and the printed circuit board, due to a rather long separation length between the bonding pad of the semiconductor chip and the electrode terminal of the printed circuit board, ) Wire bonding is required, resulting in less reliability in terms of efficiency of package density and equipment difficulties.

한편, 상기와 같은 듀얼 다이 패키지에 컨트롤러(controller) 반도체칩까지 부착하여 상기 듀얼 다이 패키지와 상기 컨트롤러 반도체칩을 한 패키지내에 구현 하고자 할 경우 상기 듀얼 다이 패키지의 반도체칩과 상기 컨트롤러 반도체칩간을 직접 부착시키지 못하기 때문에 그에 따른 멀티 칩 패키지 구현에 어려움이 있다. On the other hand, if a controller (chip) semiconductor chip is attached to the dual die package as described above, and the dual die package and the controller semiconductor chip are to be implemented in one package, the semiconductor chip of the dual die package and the controller semiconductor chip are directly attached. There is a difficulty in implementing a multi-chip package accordingly.

따라서, 본 발명은 전체 두께를 현저히 감소시킨 멀티 칩 패키지를 제공한다.Thus, the present invention provides a multi-chip package with a significant reduction in overall thickness.

또한, 본 발명은 전기적 연결 길이를 최소화시킨 멀티 칩 패키지를 제공한다.The present invention also provides a multi-chip package with a minimum length of electrical connection.

아울러, 본 발명은 서로 다른 이 종의 반도체칩간을 부착할 수 있는 멀티 칩 패키지를 제공한다. In addition, the present invention provides a multi-chip package capable of attaching different types of semiconductor chips.

일 실시예에 있어서, 멀티 칩 패키지는, 일면 및 타면에 각각 제1홈 및 제2홈이 구비되고, 하면에 볼랜드가 형성되며, 상기 제1홈 및 제2홈의 저면에 각각 적어도 1개 이상의 제1전극단자 및 제2전극단자가 구비되고, 상기 일면에 제3전극단자가 구비된 인쇄회로기판; 상기 제1홈 내에 페이스-다운 타입으로 배치되고, 상기 인쇄회로기판의 적어도 1개 이상의 제1전극단자와 전기적으로 연결되는 다수의 제1본딩패드를 구비한 제1반도체칩; 상기 제1반도체칩 상에 페이스-업 타입으로 배치된 적어도 하나 이상의 제2반도체칩; 상기 제2반도체칩의 제2본딩패드와 인쇄회로기판의 제3전극단자를 상호연결시키는 제1금속와이어; 상기 제2홈 내에 페이스-업 타입으로 부착되고, 상기 인쇄회로기판의 제2전극단자와 전기적으로 연결되는 다수의 제3본딩패드를 구비한 컨트롤러 반도체칩; 및 상기 제1금속와이어와 제1 및 제2 반도체칩을 포함한 인쇄회로기판의 일면과 상기 컨트롤러 반도체칩을 포함한 인쇄회로기판의 타면을 밀봉하는 봉지제;를 포함한다.In one embodiment, the multi-chip package is provided with a first groove and a second groove on one side and the other side, respectively, a borland is formed on the bottom surface, at least one or more on the bottom of the first groove and the second groove, respectively A printed circuit board having a first electrode terminal and a second electrode terminal and having a third electrode terminal on one surface thereof; A first semiconductor chip disposed in the first groove in a face-down type and having a plurality of first bonding pads electrically connected to at least one first electrode terminal of the printed circuit board; At least one second semiconductor chip disposed in a face-up type on the first semiconductor chip; A first metal wire interconnecting the second bonding pad of the second semiconductor chip and the third electrode terminal of the printed circuit board; A controller semiconductor chip attached to the second groove in a face-up type and having a plurality of third bonding pads electrically connected to the second electrode terminals of the printed circuit board; And an encapsulant for sealing one surface of the printed circuit board including the first metal wire and the first and second semiconductor chips and the other surface of the printed circuit board including the controller semiconductor chip.

상기 제1전극단자는, 제1홈의 저면 중앙에 배치된다.The first electrode terminal is disposed at the center of the bottom surface of the first groove.

상기 제2전극단자는, 제2홈의 저면 양측 가장자리에 배치된다.The second electrode terminal is disposed at both edges of the bottom surface of the second groove.

상기 제1반도체칩의 제1본딩패드와 상기 제1홈의 제1전극단자는 적어도 1개 이상의 솔더 범프에 의해 상호 전기적으로 이루어진다.The first bonding pad of the first semiconductor chip and the first electrode terminal of the first groove are electrically connected to each other by at least one solder bump.

상기 인쇄회로기판의 제1홈 저면과 상기 제1반도체칩 사이 공간 및 상기 인쇄회로기판의 제2홈 저면과 상기 컨트롤러 반도체칩 사이 공간에 형성된 충진재(under-fill material)를 더 포함한다.And an under-fill material formed in a space between the bottom of the first groove of the printed circuit board and the first semiconductor chip and in a space between the bottom of the second groove of the printed circuit board and the controller semiconductor chip.

상기 인쇄회로기판은 하면에 다수의 볼랜드를 더 구비한다.The printed circuit board further includes a plurality of ball lands on a lower surface thereof.

상기 볼랜드는 다수의 솔더볼이 부착된다.The borland is attached to a plurality of solder balls.

상기 인쇄회로기판의 일면에 상기 제1 및 제2반도체칩이 배치된 제1홈과 이격하여 구비된 제3홈; 상기 제3홈 내에 페이스-다운 타입으로 배치되며 제4본딩패드를 구비한 제3반도체칩; 상기 제3반도체칩 상에 페이스-업 타입으로 배치되며, 제5본딩패드를 구비한 적어도 하나 이상의 제4반도체칩; 및 상기 제3 및 제4반도체칩과 인쇄회로기판간을 전기적으로 연결시키는 적어도 하나 이상의 제2금속와이어;를 포함한다.A third groove provided on one surface of the printed circuit board to be spaced apart from the first groove on which the first and second semiconductor chips are disposed; A third semiconductor chip disposed in the third groove in a face-down type and having a fourth bonding pad; At least one fourth semiconductor chip disposed on the third semiconductor chip in a face-up type and having a fifth bonding pad; And at least one second metal wire electrically connecting the third and fourth semiconductor chips to the printed circuit board.

상기 제3홈은 저면에 적어도 하나 이상의 제4전극단자가 구비된다.The third groove has at least one fourth electrode terminal at a bottom thereof.

상기 제4전극단자는 제3홈의 저면 양측 가장자리에 배치된다.The fourth electrode terminal is disposed at both edges of the bottom surface of the third groove.

상기 제3반도체칩의 제4본딩패드와 상기 제3홈의 제4전극단자는 적어도 하나 이상의 솔더 범프에 의해 상호 전기적으로 이루어진다.The fourth bonding pad of the third semiconductor chip and the fourth electrode terminal of the third groove are electrically connected to each other by at least one solder bump.

상기 인쇄회로기판의 제3홈 저면과 상기 제3반도체칩 사이 공간에 형성된 충진재(under-fill material)를 더 포함한다.The semiconductor device may further include an under-fill material formed in a space between the bottom of the third groove of the printed circuit board and the third semiconductor chip.

상기 인쇄회로기판은 하면에 다수의 볼랜드를 더 구비한다.The printed circuit board further includes a plurality of ball lands on a lower surface thereof.

상기 볼랜드는 다수의 솔더볼이 부착된다.The borland is attached to a plurality of solder balls.

(실시예)(Example)

이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명은, 인쇄회로기판의 일면 및 타면에 각각 홈을 형성하고, 상기 일면에 형성된 홈 내에 형성시킨 솔더 범프를 이용하여 페이스-다운 타입으로 제1반도체칩을 배치시키고, 상기 제1반도체칩 후면에 페이스-업 타입으로 적어도 하나 이상의 제2반도체칩을 배치시킨 다음, 상기 타면에 형성된 홈 내에 컨트롤러 반도체칩을 배치시켜 멀티 칩 패키지를 구성한다.According to an embodiment of the present invention, grooves are formed on one side and the other side of a printed circuit board, and a first semiconductor chip is disposed in a face-down type by using solder bumps formed in the grooves formed on the one side, and the rear surface of the first semiconductor chip. The at least one second semiconductor chip is disposed in the face-up type, and then the controller semiconductor chip is disposed in the groove formed on the other surface to form a multi-chip package.

이렇게 하면, 상기 인쇄회로기판 일면에 홈을 형성하고 상기 홈 내부에 반도체칩을 스택하여 배치함으로써, 공간활용도 측면에서 우수하며 반도체칩 스택시 발생하는 패키지의 전체 높이를 종래의 그것보다 감소시킬 수가 있다.In this case, by forming a groove on one surface of the printed circuit board and stacking the semiconductor chip inside the groove, the overall height of the package which is excellent in terms of space utilization and occurs when stacking the semiconductor chip can be reduced than that of the conventional one. .

또한, 인쇄회로기판 내에 형성되는 홈의 크기를 변경시킬 수가 있어, 그에 따라 다양한 크기의 반도체칩을 스택하여 반도체 패키지를 구성할 수 있다.In addition, the size of the grooves formed in the printed circuit board can be changed, and accordingly, semiconductor chips of various sizes can be stacked to form a semiconductor package.

게다가, 인쇄회로기판 내의 홈 내에 솔더 범프를 사용하여 전기적으로 연결하여 반도체칩을 배치시킴으로써, 상기 인쇄회로기판과 와이어본딩에 의해 전기적 으로 연결되는 종래의 그것과 달리 전기적 경로가 짧아짐에 따른 보다 높은 전기적 응답성을 가질 수 있다.In addition, by placing the semiconductor chip electrically connected using solder bumps in the grooves in the printed circuit board, unlike the conventional one that is electrically connected by the printed circuit board and wire bonding, a higher electrical path as the electrical path is shortened. It may have responsiveness.

아울러, 인쇄회로기판의 타면에 형성된 홈 내부에 컨트롤러(controller) 반도체칩을 배치하고 상기 컨트롤러 반도체칩과 종류가 상이한 반도체칩들을 상기 인쇄회로기판의 일면에 형성된 홈 내부에 배치하여 스택 패키지를 구성함으로써, 서로 다른 이 종간의 반도체칩의 스택이 가능하여 그에 따른 멀티 칩 패키지로의 구현이 가능하다.In addition, by arranging a controller semiconductor chip in the groove formed on the other surface of the printed circuit board and by placing semiconductor chips different from the controller semiconductor chip in the groove formed on one surface of the printed circuit board to form a stack package In addition, stacks of different semiconductor chips can be implemented in a multi-chip package.

자세하게, 도 2는 본 발명의 실시예에 따른 멀티 칩 패키지를 도시한 단면도로서, 이를 설명하면 다음과 같다.In detail, Figure 2 is a cross-sectional view showing a multi-chip package according to an embodiment of the present invention, as follows.

도시된 바와 같이, 본 발명의 멀티 칩 패키지는 반도체칩이 배치될 수 있도록 내부에 제1홈이 형성된 인쇄회로기판 일면 상에, 두 개의 반도체칩이 스택되고, 상기 인쇄회로기판 타면에 제2홈이 형성되어 상기 제2홈 내에 컨트롤러 반도체칩이 배치되어, 상기 제1 및 제2홈을 포함하는 인쇄회로기판의 일면과 타면이 봉지제로 밀봉되어 있는 구조이다.As shown, in the multi-chip package of the present invention, two semiconductor chips are stacked on one surface of a printed circuit board on which a first groove is formed so that the semiconductor chips may be disposed, and a second groove on the other surface of the printed circuit board. The controller semiconductor chip is formed in the second groove, and one surface and the other surface of the printed circuit board including the first and second grooves are sealed with an encapsulant.

자세하게는, 일면에 회로패턴(도시안됨)이 구비되고, 하면에 다수의 볼랜드(228)를 갖는 인쇄회로기판(200)의 일면 중앙부 상에, 반도체칩이 배치될 수 있도록 내부로 움푹 들어간 형상의 제1홈(204)이 형성된다.In detail, a circuit pattern (not shown) is provided on one surface, and a recessed shape is formed in the center of one surface of the printed circuit board 200 having a plurality of ball lands 228 on the lower surface thereof so that the semiconductor chip can be disposed. The first groove 204 is formed.

또한, 상기 제1홈(204)은 내부에 구비된 적어도 하나 이상의 제1전극단자(216) 상에 적어도 하나 이상의 솔더 범프(222)가 구비되어, 상기 센터패드형의 제1반도체칩(208)에 구비된 제1본딩패드(도시안됨) 간이 전기적으로 연결되어 페이 스-다운 타입으로 부착된다.In addition, the first groove 204 is provided with at least one solder bump 222 on the at least one first electrode terminal 216 provided therein, the first semiconductor chip 208 of the center pad type Between the first bonding pads (not shown) provided in the electrical connection is attached to the face-down type.

이때, 바람직하게는, 상기 제1반도체칩(208) 부착시 기울어짐이 생기지 않도록 주의하여야 한다.At this time, preferably, care should be taken not to incline when attaching the first semiconductor chip 208.

그리고, 상기 제1홈(204) 내에 배치된 제1반도체칩(208)의 전면부와 솔더 범프(222)를 포함하는 포함영역이, 충진재(under-fill material ; 224) 물질로 밀폐된다.In addition, an area including the front surface of the first semiconductor chip 208 and the solder bumps 222 disposed in the first groove 204 is sealed with an under-fill material 224 material.

이때, 상기 충진재(224) 물질로 밀폐시, 내부 공극 없이 치밀하게 밀폐되는 것이 바람직하다.In this case, when the sealing material 224 is sealed, it is preferable that the filling material is tightly sealed without internal voids.

그리고, 상기 제1반도체칩(208) 하면에 접착제(220)를 매개로 페이스-업 타입으로 제2반도체칩(210)이 부착되고, 상기 제2반도체칩(210)의 제2본딩패드(도시안됨)와 인쇄회로기판(200)의 제3전극단자(202) 간의 전기적 연결을 위하여 제1금속와이어(214)가 전기적으로 연결된다.In addition, a second semiconductor chip 210 is attached to the lower surface of the first semiconductor chip 208 by an adhesive 220 in a face-up type, and a second bonding pad of the second semiconductor chip 210 is illustrated. No)) and the first metal wire 214 is electrically connected for the electrical connection between the third electrode terminal 202 of the printed circuit board 200.

또한, 상기 인쇄회로기판(200)의 타면 중앙부 상에, 컨트롤러(controller) 반도체칩이 배치될 수 있도록 내부로 움푹 들어간 형상의 제2홈(206)이 형성되고, 상기 제2홈(206)의 저면 양측 가장자리에 각각 구비된 제2전극단자(218) 상에 솔더 범프(222)가 구비되어, 상기 컨트롤러 반도체칩(212)에 구비된 제3본딩패드(도시안됨) 간이 전기적으로 연결되어 페이스-다운 타입으로 부착된다.In addition, a second groove 206 having a recessed shape is formed on the center of the other surface of the printed circuit board 200 so that a controller semiconductor chip may be disposed. Solder bumps 222 are provided on the second electrode terminals 218 on both side edges of the bottom, and the third bonding pads (not shown) provided on the controller semiconductor chip 212 are electrically connected to each other. Attached down type.

이 경우에도, 상기 컨트롤러 반도체칩(212) 부착시 기울어짐이 생기지 않도록 주의하여야 한다.Even in this case, care must be taken not to incline the attachment of the controller semiconductor chip 212.

그리고, 상기 제2홈(206) 내에 배치된 컨트롤러 반도체칩(212)의 전면부와 솔더 범프(222)를 포함하는 포함영역이, 충진재(under-fill material ; 224) 물질로 밀폐된다.In addition, an area including the front surface of the controller semiconductor chip 212 and the solder bumps 222 disposed in the second groove 206 is sealed with an under-fill material 224 material.

아울러, 상기 제1금속와이어(214)와 제1 및 제2반도체칩(208, 210)을 포함하는 인쇄회로기판(200)의 일면과 컨트롤러 반도체칩(212)을 포함하는 인쇄회로기판(200)의 타면이 외부의 스트레스로부터 보호하기 위해 EMC(Epoxy molding compound)와 같은 봉지제(226)로 밀봉되고, 상기 인쇄회로기판(200)의 타면의 볼랜드(228)에는 실장부재로서 다수의 솔더볼(230)이 부착된다.In addition, the printed circuit board 200 including one surface of the printed circuit board 200 including the first metal wire 214 and the first and second semiconductor chips 208 and 210 and the controller semiconductor chip 212. In order to protect from the external stress of the other side of the sealing is sealed with an encapsulant 226 such as epoxy molding compound (EMC), a plurality of solder balls 230 as a mounting member on the ball land 228 of the other side of the printed circuit board 200 ) Is attached.

도 3은 본 발명의 다른 실시예에 따른 멀티 칩 패키지를 도시한 단면도로서, 이를 설명하면 다음과 같다.3 is a cross-sectional view illustrating a multi-chip package according to another embodiment of the present invention.

도시된 바와 같이, 반도체칩이 배치될 수 있도록 내부에 제1홈 및 상기 제1홈과 이격되게 배치된 제3홈이 형성된 인쇄회로기판 일면 상에, 상기 제1홈 및 제3홈 내에 적어도 네 개 이상의 반도체칩이 스택되고, 상기 인쇄회로기판 타면에는 제2홈이 형성되어 상기 제2홈 내에는 컨트롤러 반도체칩이 배치되며, 상기 제1, 제2 및 제3홈을 포함하는 인쇄회로기판의 일면과 타면이 봉지제로 밀봉되어 있는 구조이다.As shown, at least four in the first groove and the third groove on one surface of a printed circuit board having a first groove and a third groove disposed to be spaced apart from the first groove so that the semiconductor chip can be disposed. A plurality of semiconductor chips are stacked, a second groove is formed on the other surface of the printed circuit board, and a controller semiconductor chip is disposed in the second groove, and the first, second and third grooves of the printed circuit board include: One side and the other side are sealed with an encapsulant.

자세하게는, 일면에 회로패턴(도시안됨)이 구비되고, 하면에 다수의 볼랜드(328)를 갖는 인쇄회로기판(300)의 일면에, 반도체칩이 배치될 수 있도록 내부로 움푹 들어간 형상의 제1홈(304) 및 상기 제1홈(304)과 이격되게 배치된 제3홈(332)이 형성된다.In detail, a first pattern having a recessed shape is formed on one surface of a printed circuit board 300 having a circuit pattern (not shown) on one surface and a plurality of ball lands 328 on a lower surface thereof so that a semiconductor chip can be disposed. A groove 304 and a third groove 332 spaced apart from the first groove 304 are formed.

상기 제1홈(304)은 내부에 구비된 적어도 하나 이상의 제1전극단자(316) 상 에 적어도 하나 이상의 솔더 범프(322)가 구비되어, 제1반도체칩(308)에 구비된 제1본딩패드(도시안됨) 간이 전기적으로 연결되어 페이스-다운 타입으로 부착된다.The first groove 304 is provided with at least one solder bump 322 on the at least one first electrode terminal 316 provided therein, the first bonding pad provided in the first semiconductor chip 308 (Not shown) The liver is electrically connected and attached in a face-down type.

이때, 바람직하게는, 상기 제1반도체칩(308) 부착시 기울어짐이 생기지 않도록 주의하여야 한다.At this time, preferably, care should be taken not to incline when attaching the first semiconductor chip 308.

그리고, 상기 제1홈(304) 내에 배치된 제1반도체칩(308)의 전면부와 상기 솔더 범프(322)를 포함하는 포함영역이, 충진재(under-fill material ; 324) 물질로 밀폐된다.In addition, an area including the front surface of the first semiconductor chip 308 and the solder bumps 322 disposed in the first groove 304 is sealed with an under-fill material 324 material.

여기서, 상기 충진재(324) 물질로 밀폐시, 내부 공극 없이 치밀하게 밀폐되는 것이 바람직하다.Here, when the filler 324 is sealed, it is preferable that the filler 324 is tightly sealed without internal voids.

그리고, 상기 제1반도체칩(308) 하면에 접착제(320)를 매개로 페이스-업 타입으로 적어도 하나 이상의 제2반도체칩(310)이 부착되고, 상기 제2반도체칩(310)의 제2본딩패드(도시안됨)와 인쇄회로기판(300)의 제3전극단자(302) 간의 전기적 연결을 위하여 적어도 하나 이상의 제1금속와이어(314)가 연결된다.In addition, at least one second semiconductor chip 310 is attached to the lower surface of the first semiconductor chip 308 by a face-up type with an adhesive 320, and a second bonding of the second semiconductor chip 310 is performed. At least one first metal wire 314 is connected for electrical connection between the pad (not shown) and the third electrode terminal 302 of the printed circuit board 300.

상기 제1홈(304)과 이격되게 배치된 제3홈(332)은 내부 저면의 양측가장자리에 구비된 적어도 하나 이상의 제4전극단자(334) 상에 적어도 하나 이상의 솔더 범프(322)가 구비되어, 제3반도체칩(336)에 구비된 제4본딩패드(도시안됨) 간이 전기적으로 연결되어 페이스-다운 타입으로 부착된다.The third groove 332 spaced apart from the first groove 304 is provided with at least one solder bump 322 on at least one or more fourth electrode terminals 334 disposed at both side edges of the inner bottom. The fourth bonding pads (not shown) provided in the third semiconductor chip 336 are electrically connected to each other and attached in a face-down type.

이때, 바람직하게는, 상기 제3반도체칩(336) 부착시 기울어짐이 생기지 않도록 주의하여야 한다.At this time, preferably, care should be taken not to incline when attaching the third semiconductor chip 336.

그리고, 상기 제3홈(332) 내에 배치된 제3반도체칩(336)의 전면부와 상기 솔 더 범프(322)를 포함하는 포함영역이, 충진재(324)로 밀폐된다.In addition, an area including the front portion of the third semiconductor chip 336 and the solder bump 322 disposed in the third groove 332 is sealed with the filler 324.

여기서, 상기 충진재(324) 물질로 밀폐시, 내부 공극 없이 치밀하게 밀폐되는 것이 바람직하다.Here, when the filler 324 is sealed, it is preferable that the filler 324 is tightly sealed without internal voids.

그리고, 상기 제3반도체칩(336) 하면에 접착제(320)를 매개로 페이스-업 타입으로 적어도 하나 이상의 제4반도체칩(338)이 부착되고, 상기 제4반도체칩(338)의 제5본딩패드(도시안됨)와 인쇄회로기판(300)의 제3전극단자(302) 간의 전기적 연결을 위하여 적어도 하나 이상의 제2금속와이어(340)가 연결된다.In addition, at least one fourth semiconductor chip 338 is attached to a lower surface of the third semiconductor chip 336 by an adhesive 320 in a face-up type, and a fifth bonding of the fourth semiconductor chip 338 is performed. At least one second metal wire 340 is connected for electrical connection between the pad (not shown) and the third electrode terminal 302 of the printed circuit board 300.

한편, 상기 제1홈(304) 내부에 스택되는 반도체칩들과 상기 제3홈(332) 내부에 스택되는 반도체칩들 간은 서로 다른 이종의 반도체칩들로 구성하여 스택 패키지를 구성할 수 있다.Meanwhile, a stack package may be configured by forming heterogeneous semiconductor chips between semiconductor chips stacked in the first groove 304 and semiconductor chips stacked in the third groove 332. .

그 이외의 나머지 구성요소들은 전술한 본 발명의 실시예의 그것과 동일하며, 여기서는 그 설명을 생략하도록 한다.The other components are the same as those of the above-described embodiment of the present invention, and the description thereof will be omitted.

이 경우, 본 발명은 상기 인쇄회로기판에 형성된 홈 내부에 반도체칩을 배치하여 스택패키지를 구성함으로써, 공간활용도 측면에서 우수하며 반도체칩 스택시 발생하는 패키지의 전체 높이를 종래의 그것보다 감소시킬 수가 있다.In this case, the present invention provides a stack package by arranging a semiconductor chip in a groove formed in the printed circuit board, which is excellent in terms of space utilization and can reduce the overall height of the package generated when stacking the semiconductor chip. have.

또한, 인쇄회로기판 내에 형성되는 홈의 크기를 변경시킬 수가 있어, 그에 따라 다양한 크기의 반도체칩을 스택하여 반도체 패키지를 구성할 수 있다.In addition, the size of the grooves formed in the printed circuit board can be changed, and accordingly, semiconductor chips of various sizes can be stacked to form a semiconductor package.

게다가, 인쇄회로기판 내의 홈 내에 솔더 범프를 사용하여 전기적으로 연결하여 반도체칩을 배치시킴으로써, 상기 인쇄회로기판과 와이어본딩에 의해 전기적으로 연결되는 종래의 그것과 달리 전기적 경로가 짧아짐에 따른 보다 높은 전기적 응답성을 가질 수 있다.In addition, by placing the semiconductor chip electrically connected using solder bumps in the grooves in the printed circuit board, unlike the conventional one that is electrically connected by the printed circuit board and wire bonding, a higher electrical path as the electrical path is shortened. It may have responsiveness.

아울러, 인쇄회로기판의 타면에 형성된 제2홈 내부에 컨트롤러(controller) 반도체칩을 배치하고 상기 컨트롤러 반도체칩과 종류가 상이한 반도체칩들을 상기 인쇄회로기판의 제1홈 및 제3홈 내부에 배치하여 스택 패키지를 구성함으로써, 서로 다른 종류의 반도체칩간들의 스택이 가능하여 그에 따른 멀티 칩 패키지로의 구현이 가능하다.In addition, a controller semiconductor chip is disposed in the second groove formed on the other surface of the printed circuit board, and semiconductor chips different from the controller semiconductor chip are disposed in the first groove and the third groove of the printed circuit board. By constructing a stack package, stacks of different types of semiconductor chips are possible, and thus implementation in a multi-chip package is possible.

이상, 전술한 본 발명의 실시예들에서는 특정 실시예에 관련하고 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.In the above-described embodiments of the present invention, the present invention has been described and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It will be readily apparent to those skilled in the art that the present invention may be variously modified and modified.

이상에서와 같이 본 발명은, 인쇄회로기판의 일면 및 타면에 홈을 형성하여 반도체칩들을 배치함으로써, 공간활용도 측면에서 우수하며 반도체칩 스택시 발생하는 패키지의 전체 높이를 종래의 그것보다 감소시킬 수가 있다.As described above, according to the present invention, by arranging the semiconductor chips by forming grooves on one side and the other side of the printed circuit board, it is excellent in terms of space utilization and can reduce the overall height of the package generated when stacking the semiconductor chips compared with the conventional one. have.

또한, 본 발명은 인쇄회로기판 내에 형성되는 홈의 크기를 변경시킬 수가 있어, 그에 따라 다양한 크기의 반도체칩을 스택하여 반도체 패키지를 구성할 수 있다.In addition, the present invention can change the size of the groove formed in the printed circuit board, it is possible to configure a semiconductor package by stacking semiconductor chips of various sizes accordingly.

게다가, 본 발명은 인쇄회로기판 내의 홈 내에 솔더 범프를 사용하여 전기적으로 연결하여 반도체칩을 배치시킴으로써, 상기 인쇄회로기판과 와이어본딩에 의해 전기적으로 연결되는 종래의 그것과 달리 전기적 경로가 짧아짐에 따른 보다 높 은 전기적 응답성을 가질 수 있다.In addition, the present invention by placing the semiconductor chip by electrically connecting using a solder bump in the groove in the printed circuit board, unlike the conventional electrically connected by the printed circuit board and wire bonding according to the shortened electrical path It can have a higher electrical response.

아울러, 본 발명은 인쇄회로기판의 일면 및 타면에 형성된 홈 내부에 서로 다른 종류의 반도체칩간을 배치하여 스택함으로써, 이 종의 반도체칩들간의 멀티 칩 패키지로의 구현이 가능하다.In addition, the present invention may be implemented by stacking different types of semiconductor chips in grooves formed on one side and the other side of the printed circuit board, thereby enabling a multi-chip package between the semiconductor chips of different types.

Claims (14)

일면 및 타면에 각각 제1홈 및 제2홈이 구비되고, 하면에 볼랜드가 형성되며, 상기 제1홈 및 제2홈의 저면에 각각 적어도 1개 이상의 제1전극단자 및 제2전극단자가 구비되고, 상기 일면에 제3전극단자가 구비된 인쇄회로기판;First and second grooves are provided on one side and the other side, respectively, and a land is formed on the bottom surface, and at least one first electrode terminal and a second electrode terminal are provided on the bottom of the first and second grooves, respectively. A printed circuit board having a third electrode terminal at one surface thereof; 상기 제1홈 내에 페이스-다운 타입으로 배치되고, 상기 인쇄회로기판의 적어도 1개 이상의 제1전극단자와 전기적으로 연결되는 다수의 제1본딩패드를 구비한 제1반도체칩;A first semiconductor chip disposed in the first groove in a face-down type and having a plurality of first bonding pads electrically connected to at least one first electrode terminal of the printed circuit board; 상기 제1반도체칩 상에 페이스-업 타입으로 배치된 적어도 하나 이상의 제2반도체칩;At least one second semiconductor chip disposed in a face-up type on the first semiconductor chip; 상기 제2반도체칩의 제2본딩패드와 인쇄회로기판의 제3전극단자를 상호연결시키는 제1금속와이어;A first metal wire interconnecting the second bonding pad of the second semiconductor chip and the third electrode terminal of the printed circuit board; 상기 제2홈 내에 페이스-업 타입으로 부착되고, 상기 인쇄회로기판의 제2전극단자와 전기적으로 연결되는 다수의 제3본딩패드를 구비한 컨트롤러 반도체칩; 및A controller semiconductor chip attached to the second groove in a face-up type and having a plurality of third bonding pads electrically connected to the second electrode terminals of the printed circuit board; And 상기 제1금속와이어와 제1 및 제2반도체칩을 포함한 인쇄회로기판의 일면과 상기 컨트롤러 반도체칩을 포함한 인쇄회로기판의 타면을 밀봉하는 봉지제;An encapsulant for sealing one surface of the printed circuit board including the first metal wire and the first and second semiconductor chips and the other surface of the printed circuit board including the controller semiconductor chip; 를 포함하는 것을 특징으로 하는 멀티 칩 패키지.Multi-chip package comprising a. 제 1 항에 있어서,The method of claim 1, 상기 제1전극단자는, 제1홈의 저면 중앙에 배치된 것을 특징으로 하는 멀티 칩 패키지.The first electrode terminal, the multi-chip package, characterized in that disposed in the center of the bottom of the first groove. 제 1 항에 있어서,The method of claim 1, 상기 제2전극단자는, 제2홈의 저면 양측 가장자리에 배치된 것을 특징으로 하는 멀티 칩 패키지.The second electrode terminal, the multi-chip package, characterized in that disposed on both edges of the bottom surface of the second groove. 제 1 항에 있어서,The method of claim 1, 상기 제1반도체칩의 제1본딩패드와 상기 제1홈의 제1전극단자는 적어도 1개 이상의 솔더 범프에 의해 상호 전기적으로 이루어진 것을 특징으로 하는 멀티 칩 패키지.And a first bonding pad of the first semiconductor chip and a first electrode terminal of the first groove are electrically connected to each other by at least one solder bump. 제 1 항에 있어서,The method of claim 1, 상기 인쇄회로기판의 제1홈 저면과 상기 제1반도체칩 사이 공간 및 상기 인쇄회로기판의 제2홈 저면과 상기 컨트롤러 반도체칩 사이 공간에 형성된 충진재(under-fill material)를 더 포함하는 것을 특징으로 하는 멀티 칩 패키지.And an under-fill material formed in the space between the bottom of the first groove of the printed circuit board and the first semiconductor chip and the space between the bottom of the second groove of the printed circuit board and the controller semiconductor chip. Multi-chip package. 제 1 항에 있어서,The method of claim 1, 상기 인쇄회로기판은 하면에 다수의 볼랜드를 더 구비하는 것을 특징으로 하는 멀티 칩 패키지. The printed circuit board is a multi-chip package, characterized in that further comprising a plurality of ball land on the lower surface. 제 6 항에 있어서,The method of claim 6, 상기 볼랜드는 다수의 솔더볼이 부착된 것을 특징으로 하는 멀티 칩 패키지.The borland is a multi-chip package, characterized in that a plurality of solder balls are attached. 제 1 항에 있어서,The method of claim 1, 상기 인쇄회로기판의 일면에 상기 제1 및 제2반도체칩이 배치된 제1홈과 이격하여 구비된 제3홈;A third groove provided on one surface of the printed circuit board to be spaced apart from the first groove on which the first and second semiconductor chips are disposed; 상기 제3홈 내에 페이스-다운 타입으로 배치되며 제4본딩패드를 구비한 제3반도체칩; A third semiconductor chip disposed in the third groove in a face-down type and having a fourth bonding pad; 상기 제3반도체칩 상에 페이스-업 타입으로 배치되며, 제5본딩패드를 구비한 적어도 하나 이상의 제4반도체칩; 및At least one fourth semiconductor chip disposed on the third semiconductor chip in a face-up type and having a fifth bonding pad; And 상기 제3 및 제4반도체칩과 인쇄회로기판간을 전기적으로 연결시키는 적어도 하나 이상의 제2금속와이어; At least one second metal wire electrically connecting the third and fourth semiconductor chips to the printed circuit board; 를 포함하는 것을 특징으로 하는 멀티 칩 패키지.Multi-chip package comprising a. 제 8 항에 있어서,The method of claim 8, 상기 제3홈은 저면에 적어도 하나 이상의 제4전극단자가 구비된 것을 특징으로 하는 멀티 칩 패키지. The third groove is a multi-chip package, characterized in that at least one or more fourth electrode terminals are provided on the bottom. 제 9 항에 있어서,The method of claim 9, 상기 제4전극단자는 제3홈의 저면 양측 가장자리에 배치된 것을 특징으로 하는 멀티 칩 패키지. The fourth electrode terminal is a multi-chip package, characterized in that disposed on both edges of the bottom surface of the third groove. 제 8 항 또는 제 9 항에 있어서,The method according to claim 8 or 9, 상기 제3반도체칩의 제4본딩패드와 상기 제3홈의 제4전극단자는 적어도 하나 이상의 솔더 범프에 의해 상호 전기적으로 이루어진 것을 특징으로 하는 멀티 칩 패키지.And a fourth bonding pad of the third semiconductor chip and a fourth electrode terminal of the third groove are electrically connected to each other by at least one solder bump. 제 8 항에 있어서,The method of claim 8, 상기 인쇄회로기판의 제3홈 저면과 상기 제3반도체칩 사이 공간에 형성된 충진재(under-fill material)를 더 포함하는 것을 특징으로 하는 멀티 칩 패키지.The multi-chip package further comprises an under-fill material formed in the space between the bottom of the third groove of the printed circuit board and the third semiconductor chip. 제 8 항에 있어서,The method of claim 8, 상기 인쇄회로기판은 하면에 다수의 볼랜드를 더 구비하는 것을 특징으로 하는 멀티 칩 패키지. The printed circuit board is a multi-chip package, characterized in that further comprising a plurality of ball land on the lower surface. 제 13 항에 있어서,The method of claim 13, 상기 볼랜드는 다수의 솔더볼이 부착된 것을 특징으로 하는 멀티 칩 패키지.The borland is a multi-chip package, characterized in that a plurality of solder balls are attached.
KR1020070005363A 2007-01-17 2007-01-17 Multi chip package KR20080067891A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110066701A (en) * 2009-12-11 2011-06-17 삼성전자주식회사 Package substrate and semiconductor package having the same
US9299685B2 (en) 2013-08-05 2016-03-29 Samsung Electronics Co., Ltd. Multi-chip package having a logic chip disposed in a package substrate opening and connecting to an interposer
US9437586B2 (en) 2013-10-22 2016-09-06 Samsung Electronics Co., Ltd. Semiconductor package and method of fabricating the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110066701A (en) * 2009-12-11 2011-06-17 삼성전자주식회사 Package substrate and semiconductor package having the same
US9299685B2 (en) 2013-08-05 2016-03-29 Samsung Electronics Co., Ltd. Multi-chip package having a logic chip disposed in a package substrate opening and connecting to an interposer
US9437586B2 (en) 2013-10-22 2016-09-06 Samsung Electronics Co., Ltd. Semiconductor package and method of fabricating the same

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