TWI534978B - Chip package structure - Google Patents

Description

Chip package structure

The present invention relates to a package structure, and more particularly to a package structure for a multi-wafer.

With the evolution of semiconductor packaging technology, the miniaturization of electronic products and the increasing demand for high operating speeds, various types of package structures have emerged, such as embedding semiconductor wafers directly in package substrates; or multi-chip modules. The package structure, that is, two or more wafers are combined in a single package structure to reduce the overall volume.

Conventional multi-chip package structures typically employ a parallel architecture that mounts more than two wafers on the same plane. The wafer is typically wire bonded together with the conductors on the substrate. However, the volume of conventional multi-chip package structures will increase as the number of wafers increases, making it impossible to apply to small electronic products; conventional multi-chip package structures cannot integrate wafers with different process variations. Moreover, in the conventional package structure, the wafer and the wafer are usually soldered together by a solder bump, and the tin bumps occupy a large volume, resulting in a further increase in the volume of the chip package structure.

Therefore, there is a need for a chip package structure capable of crystals having different processes. The chip packages are combined to reduce the area of the chip package structure for use in small electronic products.

Therefore, an aspect of the present invention provides a chip package structure capable of packaging a plurality of wafers at a time, in particular, wafers having different processes, and capable of reducing the volume of the entire chip package structure, and being suitable for use on a small electronic device.

According to an embodiment of the invention, a chip package structure includes a first wafer module, a plurality of first gold bumps, a second wafer module, a plurality of second gold bumps, and a non-conductive layer. Non-conductive Paste. The first chip module has a plurality of first bonding pads; the plurality of first gold bumps are located on a portion of the first metal pads; the second chip module is stacked on the first chip module, the first The two wafer module has a plurality of second metal pads. A plurality of second gold bumps are located on the second metal pad, wherein the second gold bumps are docked with the first gold bumps by ultrasonic bonding. A non-conductive adhesive is filled between the first wafer module and the second wafer module to bond the first wafer module and the second wafer module.

In the chip package structure of the above embodiment, a plurality of wafers are packaged by using a three-dimensional structure, and the wafers have different processes, and the gold bumps are connected therebetween, and the distance between the two gold bumps can be shortened, thereby further reducing the overall The size of the package structure is suitable for small electronic products.

100‧‧‧ Chip package structure

101‧‧‧Substrate

103‧‧‧Gold line

105‧‧‧Adhesive layer

107‧‧‧First chip module

109‧‧‧First metal pad

111‧‧‧ third gold bump

113‧‧‧ first gold bump

115‧‧‧second gold bump

117‧‧‧ Non-conductive adhesive

119‧‧‧second chip module

121‧‧‧Second metal pad

125‧‧‧ Third metal pad

200‧‧‧ Chip package structure

201‧‧‧ first gold bump

201a‧‧‧ first block

201b‧‧‧Second block

203‧‧‧Molded adhesive

1 is a schematic cross-sectional view showing a chip package structure according to an embodiment of the present invention.

2 is a schematic cross-sectional view showing a chip package structure according to another embodiment of the present invention.

In the chip package structure of the following embodiments, two or more wafers are combined in a single package structure, in particular, wafers having different processes can be integrated, and paths between the wafers can be shortened to improve electrical functions. The gold bumps are connected to each other, and the distance between the two gold bumps can be shortened, so that the volume of the overall package structure can be further reduced, which is suitable for small electronic products.

1 is a schematic cross-sectional view showing a chip package structure according to an embodiment of the present invention. The chip package structure 100 includes a first wafer module 107, a plurality of first gold bumps (Au Bump) 113, a second wafer module 119, a plurality of second gold bumps 115, and a non-conductive adhesive 117.

The second chip module 119 is stacked on the first chip module 107, and the front surface of the second chip module 119 faces the front surface of the first chip module 107. The two chip modules are stepped in order to facilitate wire bonding. Stacking. The first chip module 107 and the second chip module 119 are two kinds of wafers having different processes. The first chip module 107 can be a logic circuit chip manufactured by a logic process, such as a control chip or a game (Game). The device chip; the second chip module 119 may be a memory circuit chip, such as a flash memory chip or a dynamic random access memory chip. (Dynamic Random Access Memory, DRAM), etc. The positions of the first chip module 107 and the second chip module 119 can be reversed, and the second chip module 119 does not have to be on the first wafer module 107.

The first chip module 107 and the second chip module 119 respectively have a plurality of first bonding pads 109 or a plurality of second metal pads 121, and the metal pads are aluminum (Al) pads. Embedded in the first wafer module 107 or the second wafer module 119. The width of the first metal pad 109 or the second metal pad 121 may be smaller than the width of the first gold bump 113 or the second gold bump 115.

The first gold bump 113 is located on a portion of the first metal pad 109. A plurality of second gold bumps 115 are located on the second metal pad 121. Since the material of the second gold bumps 115 and the first gold bumps 113 is gold (Au; Gold), ultrasonic wave oscillation can be used for docking, and the pitch between the gold bumps can be reduced. Before the two gold bumps are butted, a non-conductive adhesive (Non-Conductive Paste) 117 is filled between the first wafer module 107 and the second wafer module 119 to bond the first wafer module 107. And the second chip module 119, and covering the first gold bump 113 and the second gold bump 115, and then ultrasonic wave oscillation docking. Due to the use of a non-conductive adhesive, there is no need to reserve space between the wafer and the wafer, between the gold bumps and the gold bumps to fill the molding compound, which further reduces the volume of the package structure.

In this embodiment, the width of the first gold bumps 113 is uniform, and the width thereof is equal to the width of the second gold bumps 115. The two gold bumps can be attached to each other without protruding portions. produce. Two first gold bumps The spacing L between 113 is between 10 um and 30 um, and the preferred spacing L is between 18 um and 20 um. Compared to the conventional architecture, the pitch is 40um to 50um, or even 100um, and the pitch of this embodiment of the present invention using gold bumps has been shortened a lot, and the package structure is also reduced in size.

In this embodiment, the chip package structure 100 further includes a substrate 101 and an adhesive layer 105. The adhesive layer 105 adheres the first wafer module 107 to the substrate 101. The material of the adhesive layer 105 can be a thermosetting or thermoplastic adhesive such as epoxy resin or acrylic resin. Add a press to attach. The substrate 101 has a plurality of third bonding pads 125 connected to one end of the Au wire 103; the other end of the gold bonding wires 103 is connected to the third gold bumps 111.

By using the package structure, a plurality of wafers can be packaged at one time, the connection path between the wafers is shortened, the conductive characteristics and the signal transmission efficiency are improved, the spacing between the gold bumps is also shortened, and the volume of the package structure is further reduced. For small electronic devices.

2 is a schematic cross-sectional view showing a chip package structure according to another embodiment of the present invention. In this embodiment, the composition of the package structure 200 is substantially the same as that of the embodiment of FIG. 1, but this embodiment adds a molding compound to cover the gold bumps of different shapes. To connect the chip modules.

The chip package structure 200 includes a substrate 101, a first wafer module 107, a plurality of first gold bumps (Au Bump) 201, a second wafer module 119, and a plurality of second gold bumps 115, and a non-conductive adhesive 117. , gold wire 103, and molding compound 203.

The first gold bump 201 has a first block 201a and a second block 201b, which are fabricated in two stages. The first block 201a is in contact with the first metal pad 109. The cross-sectional area of the first block 201a is larger than the cross-sectional area of the first metal pad 109. The second block 201b is connected to the first block 201a and the second gold bump. Between the blocks 115, the cross-sectional area of the second block 201b is smaller than the cross-sectional area of the first block 201a. The spacing between the two first gold bumps 201 is approximately 10 um to 30 um, and may even be shortened to between 18 um and 20 um.

The molding die 203 covers the first wafer module 107, the second wafer module 119, the gold bonding wire 103, and the non-conductive adhesive 117 for packaging to protect the welded gold wire 103, thereby preventing the gold wire 103 from being broken or It is falling off. The material of the molding compound 203 is mainly epoxy resin (Epoxy) or other thermosetting materials.

In the wafer package structure of the above embodiment, two or more wafers, especially wafers having different processes, are combined in a single package structure, so that the path between the wafers is shortened to enhance electrical functions, and gold between the wafers is used. The bumps are connected by ultrasonic oscillation, and the distance between the two gold bumps can be shortened, thereby further reducing the volume of the overall package structure and being suitable for small electronic products.

101‧‧‧Substrate

103‧‧‧Gold line

105‧‧‧Adhesive layer

107‧‧‧First chip module

109‧‧‧First metal pad

111‧‧‧ third gold bump

115‧‧‧second gold bump

117‧‧‧ Non-conductive adhesive

119‧‧‧second chip module

121‧‧‧Second metal pad

125‧‧‧ Third metal pad

200‧‧‧ Chip package structure

201‧‧‧ first gold bump

201a‧‧‧ first block

201b‧‧‧Second block

203‧‧‧Molded adhesive

Claims (10)

A chip package structure comprising: a first chip module having a plurality of first metal pads; a plurality of first gold bumps on a portion of the first metal pads; a second chip module stacked On the first chip module, the second chip module has a plurality of second metal pads; a plurality of second gold bumps are disposed on the second metal pads, wherein the second gold bumps The block is connected to the first gold bumps by means of ultrasonic oscillation; and a non-conductive adhesive is filled between the first chip module and the second chip module to bond the first chip module And the second wafer module. The chip package structure of claim 1, wherein the distance between the first gold bumps is between 10 um and 30 um. The chip package structure of claim 1, wherein each of the first gold bumps comprises: a first block contacting one of the first metal pads, the cross-sectional area of the first block being greater than a cross-sectional area of the first metal pad; and a second block coupled between the first block and the second gold bumps, the cross-sectional area of the second block being smaller than the first area The cross-sectional area of the block. The chip package structure of claim 1, wherein the front surface of the second chip module faces the front surface of the first wafer module. The chip package structure of claim 1, wherein the first chip module and the second chip module are a logic circuit chip and a memory circuit chip, respectively. The chip package structure of claim 1, wherein the first metal pads and the second metal pads are aluminum pads embedded in the first chip module or the second Wafer module. The chip package structure of claim 1, further comprising: a plurality of third gold bumps disposed on the first metal pads of the first chip module; and a plurality of gold wires, One end of the gold wire is connected to the third gold bumps. The chip package structure of claim 7, further comprising: a substrate having a plurality of third metal pads for connecting the other ends of the gold wires; and an adhesive layer to The wafer module is adhered to the substrate. The chip package structure of claim 8, further comprising: a molding die, covering the first wafer module, the second wafer module, the gold wires, and the non-conductive adhesive, For packaging. The chip package structure according to claim 9, wherein the material of the mold compound is epoxy resin.