KR20080020376A - Stack chip package - Google Patents

Abstract

A stack chip package is provided to reduce the size by electrically connecting chips using solder bumps or solder balls without using bonding wires. A stack chip package includes a substrate(110), first, second, and third semiconductor chips(130,150,170), metal wires, a sealing material(210), and solder balls(220). The substrate includes connection pads at an upper surface and ball lands at a lower surface. The first semiconductor chip includes a redistribution layer having first bonding pads attached on the substrate in face-up, second bonding pad disposed on the first bonding pads, and third bonding pads disposed on the second bonding pads. The second semiconductor chip is bonded with the third bonding pads. The third semiconductor chip is bonded with the second bonding pads on the second semiconductor chip. The metal wires are used for connecting the first bonding pads and connection pads of the substrate. The sealing material is used for sealing an upper surface of the substrate including the first to third semiconductor chips and metal wires. The solder balls are attached to the ball lands.

Description

Multilayer Chip Packages {STACK CHIP PACKAGE}

1 is a cross-sectional view showing a laminated chip package according to the prior art.

2 is a cross-sectional view showing a stacked chip package according to an embodiment of the present invention.

3A to 3D are cross-sectional views illustrating a manufacturing process of a stacked chip package according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

110: substrate 130: first semiconductor chip

140a: first bonding pad 140b: second bonding pad

140c: third bonding pad 150: second semiconductor chip

160: first power supply means 170: third semiconductor chip

180: second conducting means 190: bonding wire

210: sealing portion 220: solder ball

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a multilayer chip package capable of multiple stacking, thin and small, and excellent electrical characteristics regardless of the size of each semiconductor chip.

As electrical and electronic products are getting higher performance and electronic devices are lighter and shorter, the high density and high mounting of packages, which are key components, are becoming an important issue.In the case of computers, as the memory capacity increases, a large amount of RAM (Random Access Memory) As chips have increased capacities, such as flash memory, but packages are being miniaturized, various techniques for mounting a larger number of packages on a limited size substrate have been proposed and studied.

The proposed methods for reducing the size of such a package are to mount a plurality of chips or packages having the same memory capacity, and there is a limitation in manufacturing because the semiconductor chip and the package are mounted in a planar arrangement method on a substrate.

In order to overcome this limitation, a package technology in which a plurality of chips having the same storage capacity are integrally stacked is proposed, which is collectively referred to as a stacked chip package.

The above-described stacked chip package technology can reduce the manufacturing cost of the package by a simplified process, and also has advantages such as mass production, while wiring space for electrical connection inside the package according to the increase in the number and size of stacked chips. There is a drawback to this lack.

1 is a cross-sectional view illustrating a stacked chip package according to the prior art.

As shown, a conventional stacked chip package has a structure in which a plurality of semiconductor chips 20, 30, and 40 are stacked and packaged on a substrate 10, wherein each of the semiconductor chips 20, 30, and 40 is packaged. Surfaces facing each other and surfaces in contact with the substrate 10 are attached to each other with an adhesive 14, and a plurality of bonding pads 18a, 18b, and 18c are formed on the other side of the substrate 10 that is not bonded to the substrate 10.

The bonding pads 18a, 18b, and 18c of the semiconductor chips 20, 30, and 40 are respectively corresponded to the conductive patterns 12 formed on the upper surface of the substrate 10 by the bonding wires 16a, 16b, and 16c. Electrically connected, the electrical connection portion formed on the semiconductor chip 20, 30, 40 and the upper surface of the substrate 10 is encapsulated with an epoxy-based encapsulation resin 22, the ball land formed on the lower portion of the substrate ( The solder ball 24 is attached to the not shown).

However, in the case of the conventional multilayer chip package described above, an electrical short may occur due to the sweep phenomenon of the bonding wire due to the lack of wiring space due to the use of the bonding wire, and the power consumption may be reduced due to the length of the long bonding wire. There is a problem that the electrical properties are increased and worsened.

In addition, when two or more semiconductor chips are used to implement twice or more memory capacities, a wiring design for electrically connecting two or more semiconductor chips may be impossible.

Accordingly, the present invention has been made to solve the above problems, the present invention is to solve the problem of lack of wiring space and to provide packaging in a narrow space and to provide a light and simple laminated chip package.

In order to achieve the above object, the present invention provides a substrate having a connection pad on the upper surface and a ball land on the lower surface; Third bonding pads attached to the substrate in a face-up type and disposed at edges thereof, second bonding pads disposed inside the first bonding pads, and third bonding pads disposed inside the second bonding pads. A first semiconductor chip having a redistribution layer formed of bonding pads; A second semiconductor chip that is flip chip bonded with a third bonding pad on the first semiconductor chip; A third semiconductor chip disposed on the second semiconductor chip, the third semiconductor chip being flip chip bonded to the second bonding pad of the first semiconductor chip; A metal wire connecting the first bonding pad of the first semiconductor chip and the connection pad of the substrate; An encapsulation part sealing an upper surface of the substrate including the first to third semiconductor chips and the metal wire; It includes a solder ball attached to the ball land of the substrate.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view illustrating a stacked chip package according to an exemplary embodiment of the present invention.

As illustrated, the first semiconductor chip 130 having the plurality of bonding pads 140a, 140b, and 140c formed thereon is a circuit pattern therein in a face up type through an adhesive tape (not shown). (Not shown) are formed, and a connection pad (not shown) is attached to the upper surface and a borland (not shown) is provided on the lower surface, respectively. In addition, a first conductive means 160 is formed on a plurality of bonding pads (not shown), and the second semiconductor chip 150 having a size smaller than that of the first semiconductor chip 130 is the first semiconductor chip ( 130 is mounted as a Face Down type. In addition, a second conducting means 180 is formed on a plurality of bonding pads (not shown), and the third semiconductor chip 170 having a size larger than that of the second semiconductor chip 150 is a face down type. The semiconductor device is mounted on the first semiconductor chip 130 while being positioned on the second semiconductor chip 150. Here, on the first bonding pad 140a and the substrate 110 provided in the first semiconductor chip 130 to form an electrical path between the semiconductor chips 130, 150, and 170 and the substrate 110. The provided connection pads (not shown) are connected by bonding wires. In addition, a plurality of upper surfaces of the substrate 110 including the semiconductor chips 130, 150, and 170 and the bonding wires 190 are sealed by the encapsulation unit 210 and formed on the lower surface of the substrate 110. Borland (not shown) is composed of a solder ball 220 to form an electrical connection to the outside.

Here, the plurality of bonding pads 140a, 140b, and 140c provided in the first semiconductor chip 130 are formed of redistribution layers (RDLs) formed in the first semiconductor chip 130.

In addition, the first bonding pads 140a are disposed at the edge of the first semiconductor chip 130, and the second bonding pads 140b are disposed inside the first bonding pads 140a and the second bonding pads. The 140b are disposed inside the third bonding pads 140c.

In addition, the plurality of first conducting means 160 formed on the input / output pads (not shown) of the second semiconductor chip 150 may include the third bonding pads 140c provided on the first semiconductor chip 130. The plurality of second conducting means 180 formed on the input / output pads (not shown) of the three semiconductor chips 170 may be attached to the second bonding pads 140b of the first semiconductor chip 130 in a one-to-one correspondence. It is physically connected.

In addition, the first conducting means 160 may be a bump, such as a solder bump, etc. may be used and is formed before the sawing process of the wafer in a wafer level process, the second conducting means 180 is a solder ball is used It may be formed before the sawing process or in the solder ball mounting process in the wafer level unit process.

The encapsulant forming the encapsulation portion 210 is filled between the first semiconductor chip 130 and the second semiconductor chip 150 or between the first semiconductor chip 130 and the third semiconductor chip 170, but the first semiconductor chip 130 and the first semiconductor chip 130 and the third semiconductor chip 170 are filled with the encapsulant 210. A buried material may be added in place of the encapsulant to protect the energizing means 160 and the second energizing means 180 and the joints.

The multilayer chip package of the present invention can be multi-layered regardless of the size of each semiconductor chip, and since the electrical connection between the stacked chips is made using solder bumps or solder balls instead of metal wires, the multilayer chip package is long in the molding process. Sweep due to the bonding wire does not occur, and it is possible to prevent a problem such as an electrical short.

Hereinafter, a manufacturing process of a multilayer chip package according to an exemplary embodiment of the present invention will be described with reference to FIGS. 3A to 3D.

First, referring to FIG. 3A, redistribution layers are formed on a substrate 110 having a circuit pattern (not shown) formed therein, a connection pad (not shown) formed on an upper surface thereof, and a borland (not shown) formed on a lower surface thereof. The first semiconductor chip 130 provided with the first, second, and third bonding pads 140a, 140b, and 140c may be attached to the face-up type via an adhesive tape (not shown). The redistribution layer forming the first, second, and third bonding pads 140a, 140b, and 140c may be formed by a photolithography process, an electroplating process, or the like, which is a general wafer level process.

Next, as shown in FIG. 3B, the second semiconductor chip (1) having a smaller size than the first semiconductor chip 130 and having the first conducting means 160 formed on a plurality of input / output pads (not shown) 150 is mounted on the first semiconductor chip 130 as a face down type. In this case, the first conducting means 160 formed on the second semiconductor chip 150 and the third bonding pads 140c provided on the first semiconductor chip 130 are attached to each other in a one-to-one correspondence.

Subsequently, as shown in FIG. 3C, the second conductive means 180 is formed on the plurality of input / output pads (not shown) and has a size larger than that of the second semiconductor chip 150. ) Is mounted on the first semiconductor chip 130 while being positioned on the second semiconductor chip 150 as a face down type. In this case, the plurality of second conducting means 180 formed on the third semiconductor chip 170 and the second bonding pads 140b provided on the first semiconductor chip 130 are attached in a one-to-one correspondence.

Subsequently, the first bonding pad 140a of the first semiconductor chip 130 and the connection pad (not shown) provided of the substrate 110 are connected to each other by a bonding wire 190. An electrical path is formed between the three semiconductor chips 130, 150, and 170 and the substrate 110.

Finally, an encapsulation part 210 is formed to seal the top surface of the substrate 110 including the first to third semiconductor chips 130, 150, and 170 and the bonding wire 190, and the substrate 110 is formed. A solder ball 220 forming an electrical connection to the outside is attached to a plurality of borland (not shown) formed on the lower surface of the lower surface to complete the stacked chip package.

The present invention forms an electrical path between the semiconductor chip and the substrate by using a first conducting means such as solder bumps and a second conducting means such as solder balls, rather than a bonding wire, thereby shortening a path of an electrical signal to provide excellent electrical characteristics. The branch can manufacture a laminated package.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, the stacking structure of the package can be multi-layered regardless of the size of each semiconductor chip, and the wiring space of the stacked chip package can be solved by making the electrical connection with solder bumps or solder balls instead of bonding wires. The solution can provide electrical wiring in a narrow space and provide a thin and stacked chip package.

In addition, since the electrical connection between the stacked chips is made of solder bumps or solder balls, a sweep due to the bonding wire does not occur in the molding process, thereby preventing a problem such as an electrical short. It can be shortened to produce a multilayer chip package having excellent electrical characteristics.

Claims (2)

A substrate having a connection pad on an upper surface and a ball land on a lower surface thereof; Third bonding pads attached to the substrate in a face-up type and disposed at edges thereof, second bonding pads disposed inside the first bonding pads, and third bonding pads disposed inside the second bonding pads. A first semiconductor chip having a redistribution layer formed of bonding pads; A second semiconductor chip that is flip chip bonded with a third bonding pad on the first semiconductor chip; A third semiconductor chip disposed on the second semiconductor chip, the third semiconductor chip being flip chip bonded to the second bonding pad of the first semiconductor chip; A metal wire connecting the first bonding pad of the first semiconductor chip and the connection pad of the substrate; An encapsulation part sealing an upper surface of the substrate including the first to third semiconductor chips and the metal wire; And Solder ball attached to the ball land of the substrate; Laminated chip package comprising a. The method of claim 1, And a buried material is further added between the first semiconductor chip and the second semiconductor chip or between the first semiconductor chip and the third semiconductor chip.

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