TWI447869B - Chip stacked package structure and applications thereof - Google Patents

Description

Wafer stack package structure and its application

The present invention relates to a semiconductor package structure, and more particularly to a stacked package structure.

As the demand for electronic product functions and applications increases rapidly, packaging technology is also moving toward high-density miniaturization, single-chip packaging to multi-chip packaging, and from two-dimensional to three-dimensional. System In Package is a preferred method for integrating different circuit function chips. The surface mount technology (SMT) process is used to integrate different wafer stacks on the same substrate, thereby effectively reducing the package area. . It has the advantages of small size, high frequency, high speed, short production cycle and low cost.

Please refer to FIG. 5, which is a cross-sectional view of a structure according to a conventional wafer stack package structure 500. The wafer stack package structure 500 includes a substrate 510, a first wafer 520, a second wafer 530, and a plurality of wires 540 and 550. The first wafer 520 is fixed on the substrate 510 and electrically connected to the substrate 510 by the wire 540. The second wafer 530 is stacked on the first wafer 520 and electrically connected to the substrate 510 by the bonding wires 550.

However, since the wafer stacked on the upper layer, for example, the second wafer 530, must be placed in the wire bonding (wire bonding 540) configuration of the lower wafer (first wafer 520), the upper wafer (second wafer 530) must be smaller in size than the lower wafer. This also limits the number and flexibility of the wafer stack. Moreover, since the size of the upper layer wafer is small, it is necessary to lengthen the wiring length of the 550 and expand the line arc to electrically connect it to the substrate 510. When the subsequent molding process is performed, the extended wire is easily subjected to the displacement, and a short circuit occurs, which affects the process yield.

Please refer to FIG. 6. FIG. 6 is a cross-sectional view of the structure according to another conventional wafer stack package structure 600. The wafer stack package structure 600 includes a substrate 610, a first wafer 620, a second wafer 630, a plurality of wires 640 and 650, and a dummy wafer 660 between the first wafer 620 and the second wafer 630. The first wafer 620 is stacked on the substrate 610, and the first pad 670 is electrically connected to the substrate 610 by wire bonding 640; the dummy wafer 660 is stacked on the first wafer 620; and the second wafer is stacked. The second pad 680 is electrically connected to the substrate 610 by the wire 650. By the arrangement of the dummy wafer 560 having a smaller size than the first wafer 620, not only a sufficient wiring space and a line arc height can be provided between the first wafer 620 and the second wafer 630 to accommodate the wire 640, and the upper layer is not limited. The stack size of the wafer (second wafer 630). Therefore, the size of the second wafer 630 is substantially equal to the size of the first wafer 620.

However, the setting of the virtual wafer not only increases the thickness of the wafer stack, but also increases the manufacturing process cost, and further limits the trend of miniaturization and high density of the package structure.

Therefore, there is a need to provide a wafer stack package structure that has high yield, low process, and does not limit package density.

It is an object of the present invention to provide a wafer stack package structure comprising: a substrate, a first wafer, a second wafer, a patterned wiring layer, and a conductive element. The substrate has a first surface and an opposite second surface. The first wafer is located on the first surface of the substrate and is electrically connected to the substrate. The second wafer is located above the first wafer, the second wafer has a second active surface, and wherein the second active surface is configured with at least one second bonding pad. The patterned circuit layer is formed on the second active surface and matched with the second bonding pad, and then electrically connected to the substrate via the conductive element.

Another object of the present invention is to provide a wafer stack package structure comprising: a substrate, a first wafer, a second wafer, a first patterned wiring layer, and a first wiring. Wherein the substrate has a first surface and an opposite second surface. The first wafer has a first crystal back corresponding to the first surface and a first active surface opposite the first crystal back. The second wafer is located above the first wafer and has a second active surface facing the first active surface, wherein the second active surface is provided with at least one second bonding pad. The first patterned wiring layer is over the first active surface and mates with the second bonding pad. And electrically connecting the first patterned circuit layer and the substrate by the first wire.

In a preferred embodiment of the invention, a patterned wiring layer is formed on the active layer of the upper layer of the stacked wafer structure. When the upper wafer is flip-chip stacked on the lower wafer, and the wiring of the patterned wiring layer is used, the bonding positions of the pads of the upper wafer are redistributed to correspond to the edges of the wafer, and then the pattern is patterned by a set of conductive elements. The circuit layer is electrically connected to the substrate.

In another preferred embodiment of the present invention, the underlying wafer is provided with a pad patterned layer to match the pads of the upper wafer, thereby redistributing the bonding positions of the pads of the upper wafer, and then soldering by wire bonding. The pad is electrically connected to the substrate.

Thereby, in the prior art, the problem that the length of the wire bonding wire of the upper layer wafer and the substrate is electrically connected and the wire arc is excessively large can be solved.

Therefore, according to the embodiments described above, by the technical advantages provided by the present invention, the problem that the conventional wafer stack package structure yield seal and the package density are not high can be solved.

The above and other objects, features, advantages and embodiments of the present invention will become more apparent.

Please refer to FIG. 1 , which is a cross-sectional view of a wafer stack package structure 100 according to a first preferred embodiment of the present invention.

The wafer stack package structure 100 includes a substrate 101, a first wafer 102, a patterned wiring layer 105, a second wafer 106, a conductive member 120, a sealant resin 122, and a plurality of external connection terminals 111.

The substrate 101 has a first surface 118 and a second surface 119 relative to the first surface 118. In a preferred embodiment of the invention, substrate 101 is comprised of a lead frame, a printed circuit board, or a die carrier. In the present embodiment, the substrate 101 is a printed circuit board, and the material thereof is, for example, a BT or FR4 circuit board or other flexible circuit board, and the substrate 101 has a through hole 111.

The first wafer 102 is stacked on the first surface 118 of the substrate 101 by an adhesive layer (not shown), and the first wafer 102 has a first active surface 107 facing the substrate 101, and a first An active surface 107 is opposite the first crystal back 108. In this embodiment, one portion of the first active surface 107 is adhered to the first surface 118 of the substrate 101; and the other portion is exposed to the through opening 111, and a plurality of first pads 117 are disposed. At least one of the first pads 117 is electrically connected to the substrate 101 by a wire 113 passing through the through opening 111.

Conductive element 120 is located on first crystal back 108 of first wafer 102. In the present embodiment, the conductive element 120 includes a patterned wiring layer 103 formed on the first crystal back 108, at least one wire, such as a wire 104, and at least one conductive bump, such as a conductive bump 116. The patterned circuit layer 103 is a redistribution layer (RDL), and the patterned circuit layer 103 includes a plurality of wires, one end of which extends toward an edge of the first crystal back 108 of the first wafer 102. And electrically connected to the substrate 101 by the wire 104; the other end is electrically connected to the conductive bump 116.

The second wafer 106 is located above the first wafer 102, and the second active surface 109 of the second wafer 106 facing the first wafer 102 is configured with at least one second bonding pad, such as a second bonding pad 110, and a second bonding The pads 110 are patterned to match each other. The patterned circuit layer 105 includes a plurality of wires, one end of the at least one wire is electrically connected to one of the second pads 110, and the other end is matched with one of the conductive bumps 116. When the second wafer 106 is stacked on the first wafer 102 in a flip chip manner, the at least one second pad 110 can be patterned by the patterned wiring layer 105, the conductive bumps 116, the patterned wiring layer 103, and the bonding wires 104. The substrate is electrically connected.

The sealant resin 120 is filled between the substrate 101, the first wafer 102, and the second wafer 106, and finally a plurality of external connection terminals 111 are formed on the second surface 119 of the substrate. These external terminals 111 may preferably be, for example, solder balls. The wafer stack package structure 100 can be electrically connected to other external circuits by these external connection terminals 111.

In some embodiments of the present invention, the patterned wiring layer 105 can change the wiring pattern in accordance with the pad configuration of different wafers, and then match the wiring pattern of the patterned wiring layer 103, the wiring 104, and the conductive bump 116 of the conductive element 120. Significantly increase the flexibility of line configuration in a stacked package structure. Therefore, when the second wafer 106 having the same size as the first wafer 102 and the first wafer 102 are stacked on each other, the patterned wiring layer 105 and the conductive member 120 may bring the second pad 110 originally close to the center of the second wafer 106, or The second pad 110 at other locations is rerouted so that the second pad 110 can correspond to other locations of the second wafer 106, for example to the edge of the second wafer 106, and the second pad 110 and the substrate are 101 electrical connection, without the problem of excessive wiring or excessive arcing.

In still other embodiments of the present invention, after the second pad 110 of the second wafer 106 is rerouted through the patterned wiring layer 105 and the conductive element 120, the first wafer 101 and the second wafer 106 may be designed with various different lines. The substrate is such that the stack of wafers is adapted to the design of the various package structures.

Please refer to FIG. 2, which is a cross-sectional view of a wafer stack package structure 200 according to a second preferred embodiment of the present invention.

The wafer stack package structure 200 includes a substrate 201, a first wafer 202, a second patterned wiring layer 205, a second wafer 206, a conductive member 220, and a sealant resin 222, and a plurality of external connection terminals 211.

The substrate 201 has a first surface 218 and a second surface 219 opposite the first surface 218. In a preferred embodiment of the invention, the substrate 201 is constructed of a lead frame, a printed circuit board, or a die carrier, such as a BT or FR4 circuit board or other flexible circuit board.

The first wafer 202 is stacked on the first surface 218 of the substrate 201 by an adhesive layer (not shown), and the first wafer 202 has a first active surface 208 opposite to the substrate 201, and a The first active surface 208 is opposite to the first crystal back 207. In the embodiment, the first active surface 208 has at least one first bonding pad 217, and the first bonding pad 217 is electrically connected to the substrate 201 by a second bonding wire 212.

Conductive element 220 is located on first active surface 208 of first wafer 202. In the present embodiment, the conductive element 220 includes a first patterned circuit layer 203 formed on the first active surface 208, at least one wire, such as a first wire 204, and at least one conductive bump, such as a conductive bump 216. . The first patterned circuit layer 203 is a redistributed circuit layer, and the first patterned circuit layer 203 includes a plurality of wires, such as a first wire 203a and a second wire 203b.

One end of the at least one first wire 203a extends toward the edge of the first active surface 208 of the first wafer 202, and the first wire 203a is electrically connected to the substrate 201 by the first wire 204; the first wire 203a is further One end is electrically connected to the conductive bump 216. The one end of the at least one second wire 203b is electrically connected to the first pad 217 on the first active surface 208; the other end of the second wire 203b extends to other positions of the first chip 202, for example, to the first wafer 202. The edge of the first active surface 208 extends. The first wafer 202 can be electrically connected to the substrate 201 by the second bonding line 212.

The second wafer 206 is located above the first wafer 202, and the second wafer 206 faces the second active surface 209 of the first wafer 202, and is configured with at least one second bonding pad, such as the second bonding pad 210, and one and the second The second patterned circuit layer 205 is matched to the pads 210.

The second patterned circuit layer 205 includes a plurality of wires, such as a third wire 205a and a fourth wire 205b. At least one of the wires, for example, the third 205a, one end is electrically connected to one of the second pads 210, and the other end of the third wire 205a is matched with one of the conductive bumps 216. When the second wafer 206 is stacked on the first wafer 202 in a flip chip manner, the at least one second pad 210 may be the third wire 205a of the second patterned circuit layer 205, the conductive bumps 216, and the first The first wire 203a and the first wire 204 of the patterned circuit layer 203 are electrically connected to the substrate 201.

The sealing resin 220 is filled between the substrate 201, the first wafer 202 and the second wafer 206, and finally a plurality of external connection terminals 211 are formed on the second surface 219 of the substrate 201. The external terminals may preferably be For example, it is a solder ball. The wafer stack package structure 200 can be electrically connected to other external circuits by these external connection terminals 211.

In some embodiments of the present invention, the second patterned circuit layer 205 can change the wiring pattern in accordance with the pad configuration of different wafers, and then match the first patterned circuit layer 203 of the conductive element 220, the first bonding line 204, and the conductive bumps. The wiring variation of 216 can greatly increase the flexibility of the line configuration in the stacked package structure. Therefore, when the second wafer 206 having the same size as the first wafer 202 and the first wafer 202 are stacked on each other, the second patterned wiring layer 205 and the conductive member 220 may be adjacent to the second pad 210 of the center of the second wafer 106. Or the second pad 210 in another position is re-routed, and the second pad 210 can be corresponding to the edge of the second wafer 206 via the conductive component 220, and the second pad 210 is electrically connected to the substrate 201. There is no problem that the wiring is too long or the line arc is too large.

In still other embodiments of the present invention, after the second pad 210 of the second wafer 206 is rewired through the second patterned wiring layer 205 and the conductive element 220, the first wafer 201 and the second wafer 206 may be matched with various types. The substrate of the circuit design is such that the stack of wafers is adapted to the design of various package structures.

Please refer to FIG. 3, which is a cross-sectional view of a wafer stack package structure 300 according to a third preferred embodiment of the present invention.

The wafer stack package structure 300 includes a substrate 301, a first wafer 302, a second patterned circuit layer 305, a second wafer 306, a conductive element 320, a sealant resin 322, and a plurality of external connection terminals 311.

The substrate 301 has a first surface 321 and a second surface 323 opposite the first surface 321 . In a preferred embodiment of the invention, the substrate 301 is constructed of a lead frame, a printed circuit board, or a die carrier, such as a BT or FR4 circuit board or other flexible circuit board. In the present embodiment, the substrate 301 is a printed circuit board, and the substrate 301 has a through opening 311.

The first wafer 302 is stacked on the first surface 321 of the substrate 301 by a flip chip bonding process, and the first wafer 302 has a first active surface 307 facing the substrate 301, and a first active The face 307 is opposite the first crystal back 308. In the embodiment, the first active surface 307 is provided with a plurality of first pads 317, and the first pads 317 are electrically connected to the substrate 301 by a plurality of bumps 318. In addition, the bumps 318 are covered by a primer 312, and the first active surface 307 is fixed to the first surface 321 of the substrate 301.

In a preferred embodiment of the present invention, a heat dissipation fin 319 is further formed on the first active surface 307 to extend outward from the first active surface 307 via the through opening 311, thereby increasing the wafer stack package structure. 300 heat dissipation effect.

Conductive element 320 is located on first crystal back 308 of first wafer 302. In the present embodiment, the conductive element 320 includes a first patterned wiring layer 303 formed on the first crystal back 308, at least one wire, such as a wire 304, and at least one conductive bump, such as a conductive bump 316. The first patterned circuit layer 303 is a redistributed circuit layer, and the first patterned circuit layer 303 includes a plurality of wires, and one of the at least one wires extends to other locations of the first die 302, for example, to the edge of the first die 302. The extension is electrically connected to the substrate 301 by the wire 304; and the other end of the wire is electrically connected to the conductive bump 316.

The second wafer 306 is located above the first wafer 302, and the second wafer 306 faces the second active surface 309 of the first wafer 302, and is configured with at least one second bonding pad, such as the second bonding pad 310, and one and the second The second patterned circuit layer 305 is matched to the pads 310. The second patterned circuit layer 305 includes a plurality of wires, wherein one end of the at least one wire is electrically connected to one of the second pads 310, and the other end is matched with one of the conductive bumps 316. When the second wafer 306 is stacked on the first wafer 302 in a flip chip manner, the at least one second pad 310 may be formed by the second patterned circuit layer 305, the conductive bumps 316, and the first patterned circuit layer 303. And the wire 304 is electrically connected to the substrate 301.

The sealing resin 322 is filled between the substrate 301, the first wafer 302 and the second wafer 306, and finally a plurality of external connection terminals 314 are formed on the second surface 323 of the substrate. The external terminals may preferably be For example, tin balls. And through these external connection terminals 314, the wafer stack package structure 300 can be electrically connected to other external circuits.

In some embodiments of the present invention, the second patterned circuit layer 305 can change the wiring pattern in accordance with the pad configuration of different wafers, and then match the first patterned circuit layer 303, the wire 304, and the conductive bump 316 of the conductive element 320. Wiring changes can greatly increase the flexibility of line configuration in a stacked package structure. Therefore, when the second wafer 306 having the same size as the first wafer 302 and the first wafer 302 are stacked on each other, the second patterned wiring layer 305 and the conductive member 320 may be adjacent to the second pad 310 originally adjacent to the center of the second wafer 306. Alternatively, the second pad 310 at other positions of the second crystal 306 is re-routed to correspond to the edge of the second wafer 306, and the second pad 310 is electrically connected to the substrate 301 without wiring. The problem of too long or too large a line arc.

In still other embodiments of the present invention, after the second pad 310 of the second wafer 306 is rewired through the second patterned wiring layer 305 and the conductive element 320, the first wafer 301 and the second wafer 306 may be combined with different types. The substrate of the circuit design is such that the stack of wafers is adapted to the design of various package structures.

Referring to FIG. 4, FIG. 4 is a cross-sectional view of a wafer stack package structure 400 according to a fourth preferred embodiment of the present invention.

The wafer stack package structure 400 includes a substrate 401 a first wafer 402, a second patterned wiring layer 405, a second wafer 406, a conductive member 420, and a sealant resin 422 and a plurality of external connection terminals 414.

The substrate 401 has a first surface 418 and a second surface 419 relative to the first surface 418. In a preferred embodiment of the invention, the substrate 401 is constructed of a lead frame, a printed circuit board, or a die carrier, such as a BT or FR4 circuit board or other flexible circuit board. In the present embodiment, the substrate 401 is a printed circuit board, and the substrate 401 has a through opening 411.

The first wafer 402 is stacked on the first surface 418 of the substrate 401 by an adhesive layer (not shown), and the first wafer 402 has a first active surface 407 facing the substrate 401, and a The first active surface 407 is opposite to the first crystal back 408. In this embodiment, one portion of the first active surface 407 is adhered to the first surface 418 of the substrate 401; and the other portion is exposed to the through opening 411, and a plurality of first pads 417 are disposed. At least one of the pads 417 is electrically connected to the substrate 401 by a wire 413 passing through the through opening 411.

The second wafer 406 has a second active surface 409 and a second crystal back 412 opposite the second active surface 409. In this embodiment, the second crystal back 412 is fixed on the first crystal back 408 of the first wafer 402 by an adhesive layer (not shown). The second active surface 409 of the second wafer 406 is provided with at least one second bonding pad 410 and a second patterned wiring layer 405 matching the second bonding pad 410. The second patterned circuit layer 405 is a redistributed circuit layer, and includes a plurality of wires, wherein one end of at least one of the wires is electrically connected to one of the second pads 410, and the other end is second to the second wafer 406. The edges of face 409 extend and are mated with conductive elements 420.

In this embodiment, at least one of the conductive elements 420 is wire-bonded, for example, wire-bonded, for electrically connecting to the substrate 401.

The sealing resin 420 is filled between the substrate 401, the first wafer 402 and the second wafer 406, and finally a plurality of external connection terminals 414 are formed on the second surface 419 of the substrate 401. The external terminals 411 are preferably Yes, for example, solder balls. The wafer stack package structure 400 can be electrically connected to other external circuits by these external connection terminals 411.

In this embodiment, the second patterned circuit layer 405 can change the wiring pattern in accordance with the pad configuration of different wafers, redistribute the wire bonding position of the second pad 410, and go to other positions of the second wafer 406, for example, The second wafer 406 is extended on the edge, and the second pad 410 is electrically connected to the substrate 401 by the conductive member 420 (wire bonding).

Referring to FIG. 7, FIG. 7 is a cross-sectional view of a wafer stack package structure 700 according to a fifth preferred embodiment of the present invention.

The wafer stack package structure 700 includes a substrate 701, a first wafer 702, a second patterned circuit layer 705, a second wafer 706, a conductive element 720, and a sealant resin 722 and a plurality of external connection terminals 711.

Substrate 701 has a first surface 718 and a second surface 719 opposite first surface 718. In a preferred embodiment of the invention, the substrate 701 is constructed of a lead frame, a printed circuit board, or a die carrier, such as a BT or FR4 circuit board or other flexible circuit board.

The first wafer 702 is stacked on the first surface 718 of the substrate 701 by an adhesive layer (not shown), and the first wafer 702 has a first active surface 708 facing away from the substrate 701, and a The first active surface 708 is opposite to the first crystal back 707. In the present embodiment, the first active surface 708 has at least one first pad 717.

Conductive element 720 is located on first active surface 708 of first wafer 702. In the present embodiment, the conductive element 720 includes a first patterned circuit layer 703 formed on the first active surface 708, at least one wire, such as a first wire 704, and at least one conductive bump, such as a conductive bump 716. . The first patterned circuit layer 703 is a redistributed circuit layer, and the first patterned circuit layer 703 includes a plurality of wires. One of the at least one wire of the first patterned circuit layer 703 is terminated to the first active surface 708 of the first wafer 702. The edge of the wire is electrically connected to the substrate 701 by the first wire 704; the other end of the wire is electrically connected to the conductive bump 716. In this embodiment, the first patterned pad layer 703 and the conductive bump 716 are electrically connected to the first pad 717, and the first pad 717 is electrically connected to the first pad 717. The substrate 701 is turned on.

The second wafer 706 is located above the first wafer 702, and the second wafer 706 faces the second active surface 709 of the first wafer 702, and is configured with at least one second bonding pad, such as the second bonding pad 710, and one and the second The pads 710 are matched to each other by a second patterned circuit layer 705.

The second patterned circuit layer 705 includes a plurality of wires, wherein one end of at least one of the wires is electrically connected to one of the second pads 710, and the other end of the wire is matched with one of the conductive bumps 716. . When the second wafer 706 is stacked on the first wafer 702 in a flip chip manner, the at least one second pad 710 may pass through the second patterned circuit layer 705, the conductive bumps 716, and the first patterned circuit layer 703. The first bonding wire 704 is electrically connected to the substrate 701. Since the first patterned circuit layer 703 can be simultaneously connected to the first pad 717 of the first wafer 702 and the second pad 710 of the second wafer 706, the first pad 71 and the second pad 710 can transmit the same signal. .

The sealing resin 720 is filled between the substrate 701, the first wafer 702 and the second wafer 706, and finally a plurality of external connection terminals 711 are formed on the second surface 719 of the substrate 701. The external terminals may preferably be For example, it is a solder ball. The wafer stack package structure 700 can be electrically connected to other external circuits by these external connection terminals 711.

In some embodiments of the present invention, the second patterned wiring layer 705 can change the wiring pattern in accordance with the pad configuration of different wafers, and then match the first patterned wiring layer 703 of the conductive element 720, the first bonding line 704, and the conductive bumps. The 716 wiring changes can greatly increase the flexibility of the line configuration in the stacked package structure. Therefore, when the second wafer 706 having the same size as the first wafer 702 and the first wafer 702 are stacked on each other, the second patterned wiring layer 705 and the conductive member 720 may be adjacent to the second pad 710 originally adjacent to the center of the second wafer 706. Or the second pad 710 at other locations is re-routed, and the second pad 710 can be corresponding to the edge of the second wafer 706 via the conductive component 720, and the second pad 710 is electrically connected to the substrate 701. There is no problem that the wiring is too long or the line arc is too large.

In still other embodiments of the present invention, after the second pad 710 of the second wafer 706 is rewired through the second patterned wiring layer 705 and the conductive element 720, the first wafer 701 and the second wafer 706 may be combined with different types. The substrate of the circuit design is such that the stack of wafers is adapted to the design of various package structures.

Referring to FIG. 8, FIG. 8 is a cross-sectional view of a wafer stack package structure 800 according to a sixth preferred embodiment of the present invention.

The wafer stack package structure 800 includes a substrate 801, a first wafer 802, a first patterned circuit layer 803a, a second wafer 804, a first wire 803, a sealant resin 815, and a plurality of external connection terminals 805.

Substrate 801 has a first surface 806 and a second surface 807 opposite first surface 806. In a preferred embodiment of the invention, the substrate 801 is constructed of a lead frame, a printed circuit board, or a die carrier, such as a BT or FR4 circuit board or other flexible circuit board. In the present embodiment, the substrate 801 is a printed circuit board.

The first wafer 802 has a first active surface 808 facing the substrate 801, and a first crystal back 809 opposite the first active surface 808, and the first crystal back 809 of the first wafer 802 is bonded by surface The process is stacked on the first surface 806 of the substrate 801. In this embodiment, the first active surface 808 is provided with a plurality of first pads 810, and the first pads 810 are electrically connected to the substrate 801 by the first bonding wires 803.

The second wafer 804 is located above the first wafer 802, and the second wafer 804 faces the second active surface 811 of the first wafer 802, and is configured with at least one second bonding pad, such as the second bonding pad 812. The size of the second wafer 804 is smaller than the size of the first wafer 802.

The first patterned wiring layer 803a is located on the first active surface 808 of the first wafer 802 and is at a distance from the first pad 810. Therefore, the first patterned circuit layer 803a is not directly electrically connected to the first pad 810. The first patterned circuit layer 803a includes a plurality of wires, wherein one of the ends of the at least one wire and the second pad 812 are matched with each other, and electrically connected to each other by the conductive bumps 813; the other end is directed to the first die 802. The other locations extend, for example, to the edge of the first active surface 808 of the first wafer 802 and are electrically connected to the substrate 801 by the second bonding wires 814.

The sealing resin 815 is filled between the substrate 801, the first wafer 802 and the second wafer 804, and finally a plurality of external connection terminals 805 are formed on the second surface 807 of the substrate 801. Preferably, the external portions are external. The terminals are, for example, solder balls, and by these external connection terminals 805, the wafer stack package structure 800 can be electrically connected to other external circuits.

In this embodiment, the first patterned circuit layer 803a can be matched with the configuration of the second pad 812 of the second wafer 804 to change the wiring pattern of the wiring pattern to correspond to the edge of the first wafer 802 to make the substrate The second wire 814 electrically connected to the 301 does not have a problem that the wiring is too long or the arc is too large. The flexibility of the line configuration in the stacked package structure can be greatly increased.

According to the above, a preferred embodiment of the present invention is an active layer of an upper wafer of a wafer stack structure, forming an upper patterned wiring layer, so that the upper patterned wiring layer and the upper wafer pad are matched, thereby The bonding positions of the pads of the upper wafer are redistributed, and the bonding pads are electrically connected to the substrate by conductive members.

In another preferred embodiment of the present invention, the underlying wafer is provided with a pad patterned layer to match the pads of the upper wafer, thereby redistributing the bonding positions of the pads of the upper wafer, and then soldering by wire bonding. The pad is electrically connected to the substrate.

Thereby, not only the pad design of different upper layers can be matched, but also the wiring in the patterned circuit layer can be modified to provide a variety of selection space for the upper layer wafer. When the upper wafer and the lower wafer have the same size, the bonding positions of the pads of the upper wafer can be redistributed to be dispersed to the edge of the wafer without causing problems of excessive wiring or excessive arcing. By eliminating the need for virtual wafers, stack thickness and process cost can be significantly reduced while increasing package density.

In addition, in some embodiments of the invention, the conductive element comprises a lower patterned circuit layer between the lower wafer and the upper wafer, wherein the wiring of the lower patterned wiring layer and the upper patterned wiring layer match each other. When the upper wafer is flip-chip stacked on the lower wafer, the upper patterned wiring layer is electrically connected to the lower patterned wiring layer. The patterned circuit layer is electrically connected to the substrate by wire bonding. Since the upper patterned circuit layer can be matched with the pad configuration of different upper wafers to change the wiring pattern, and the lower patterned circuit layer and the wiring conductive variation, the flexibility of line configuration and design in the stacked package structure can be greatly increased.

Therefore, by the technical features provided by the present invention, the problem that the conventional wafer stack package structure yield seal and the package density are not high can be solved, and the process components can not be shared due to product diversity, and the derivative cost is too high. problem.

While the invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and it is to be understood by those of ordinary skill in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100. . . Wafer stack package structure

101. . . Substrate

102. . . First wafer

103. . . Patterned circuit layer

104. . . Line

105. . . Patterned circuit layer

106. . . Second chip

107. . . First active surface

108. . . First crystal back

109. . . Second active surface

110. . . Second pad

111. . . Through opening

113. . . Line

114. . . External connection terminal

116‧‧‧Electrical bumps

117‧‧‧First pad

118‧‧‧The first surface of the substrate

119‧‧‧The second surface of the substrate

120‧‧‧Conducting components

122‧‧‧ Sealing resin

200‧‧‧ wafer stacking structure

201‧‧‧Substrate

202‧‧‧First chip

203‧‧‧First patterned circuit layer

203a‧‧‧First wire

203b‧‧‧second wire

204‧‧‧First line

205‧‧‧Second patterned circuit layer

205a‧‧‧ Third wire

205b‧‧‧fourth wire

206‧‧‧second chip

207‧‧‧ crystal back

208‧‧‧First active surface

209‧‧‧second active surface

210‧‧‧Second pad

212‧‧‧Second line

214‧‧‧External connection terminal

216‧‧‧Electrical bumps

217‧‧‧First pad

218‧‧‧ The first surface of the substrate

219‧‧‧Second surface of the substrate

220‧‧‧Conducting components

222‧‧‧ Sealant resin

300‧‧‧ wafer stacking structure

301‧‧‧Substrate

302‧‧‧First chip

303‧‧‧First patterned circuit layer

304‧‧‧Line

305‧‧‧Second patterned circuit layer

306‧‧‧second chip

307‧‧‧First active surface

308‧‧‧First crystal back

309‧‧‧second active surface

310‧‧‧Second pad

311‧‧‧through opening

312‧‧‧Bottom glue

314‧‧‧External connection terminal

316‧‧‧Electrical bumps

317‧‧‧First pad

318‧‧‧Bumps

319. . . Heat sink fin

320. . . Conductive component

321. . . First surface of the substrate

322. . . Sealing resin

323. . . Second surface of the substrate

400. . . Wafer stack package structure

401. . . Substrate

402. . . First wafer

405. . . Second patterned circuit layer

406. . . Second chip

407. . . First active surface

408. . . First crystal back

409. . . Second active surface

410. . . Second pad

411. . . Through opening

412. . . Second crystal back

413. . . Line

414. . . External connection terminal

417. . . Solder pad

418. . . First surface of the substrate

419. . . Second surface of the substrate

420. . . Conductive component

422. . . Sealing resin

500. . . Wafer stack package structure

510. . . Substrate

520. . . First wafer

530. . . Second chip

540. . . Line

550. . . Line

610. . . Substrate

620. . . First wafer

630. . . Second chip

640. . . Line

650. . . Line

660. . . Virtual chip

670. . . Solder pad

680. . . Solder pad

700. . . Wafer stack package structure

701. . . Substrate

702. . . First wafer

703. . . First patterned circuit layer

704. . . First line

705. . . Second patterned circuit layer

706. . . Second chip

707. . . First crystal back

708. . . First active surface

709. . . Second active surface

710. . . Second pad

711. . . External connection terminal

716. . . Conductive bump

717. . . First pad

718. . . First surface of the substrate

719. . . Second surface of the substrate

720. . . Conductive component

722. . . Sealing resin

800. . . Wafer stack package structure

801. . . Substrate

802. . . First wafer

803. . . First line

803a. . . First patterned circuit layer

804. . . Second chip

805. . . External connection terminal

806. . . First surface of the substrate

807. . . Second surface of the substrate

808. . . First active surface

809. . . First crystal back

810. . . First pad

811. . . Second active surface

812. . . Second pad

813. . . Conductive bump

814. . . Second line

815. . . Sealing resin

The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood.

1 is a cross-sectional view of a wafer stack package structure 100 in accordance with a first preferred embodiment of the present invention.

2 is a cross-sectional view of a wafer stack package structure 200 in accordance with a second preferred embodiment of the present invention.

3 is a cross-sectional view of a wafer stack package structure 300 in accordance with a third preferred embodiment of the present invention.

Referring to FIG. 4, FIG. 4 is a cross-sectional view of a wafer stack package structure 400 according to a fourth preferred embodiment of the present invention.

Figure 5 is a cross-sectional view of the structure of a conventional wafer stack package structure 500.

Figure 6 is a cross-sectional view of the structure of another conventional wafer stack package structure 600.

Figure 7 is a cross-sectional view of a wafer stack package structure 700 in accordance with a fifth preferred embodiment of the present invention.

Figure 8 is a cross-sectional view of a wafer stack package structure 800 in accordance with a sixth preferred embodiment of the present invention.

100. . . Wafer stack package structure

101. . . Substrate

102. . . First wafer

103. . . Patterned circuit layer

104. . . Line

105. . . Patterned circuit layer

106. . . Second chip

107. . . First active surface

108. . . First crystal back

109. . . Second active surface

110. . . Second pad

111. . . Through opening

113. . . Line

114. . . External connection terminal

115. . . Internal connection

116. . . Conductive bump

117. . . First pad

118. . . Upper surface of substrate

119. . . Second surface of substrate

120. . . Conductive component

122. . . Sealing resin

Claims (12)

A wafer stack package structure comprising: a substrate having a first surface and an opposite second surface, wherein the substrate has a through opening; a first wafer located at the first of the substrate a surface electrically connected to the substrate, wherein the first active surface and the first crystal back of the first wafer are respectively located on opposite sides of the first wafer, and the first active surface and the substrate The first surface of the first surface opposite to the first surface of the first wafer facing the substrate is exposed to the through opening, the first active surface has a plurality of first pads, and the first pads are at least One is electrically connected to the substrate by at least one wire passing through the through opening; a second wafer is located on the first crystal back of the first wafer, and the opposite sides of the second wafer respectively have a second active surface and a second crystal back surface, wherein the second active surface faces the first crystal back, and the second active surface is configured with at least one second solder pad; and a second patterned circuit layer Located on the second active surface and matching the second bonding pad; An electrical component is bonded between the first crystal back and the second patterned circuit layer on the second active surface to electrically connect the second patterned circuit layer and the substrate, wherein the conductive component comprises: a first patterned circuit layer is disposed on a first crystal back of the first wafer facing the second active surface, and the first patterned circuit layer and the second patterned circuit layer are matched with each other; at least one conductive a bump electrically connecting the second patterned circuit layer and the a first patterned circuit layer; and a plurality of wires electrically connected to the substrate and the first patterned circuit layer. The stacked package structure of claim 1, wherein the substrate is a lead frame, a printed circuit board, or a die carrier. The stacked package structure of claim 1, wherein the first active mask is at least one first bonding pad, and the first bonding pad is electrically connected to the substrate by a plurality of bumps. The stacked package structure of claim 3, further comprising a primer covering the bumps and fixing the first active surface on the substrate. The stacked package structure of claim 4, further comprising a heat dissipation fin disposed on the first active surface and extending outward through the through opening. The stacked package structure of claim 1, wherein the second wafer is fixed to the first wafer opposite to the first active surface with respect to the second crystal back of the second active surface The first crystal is on the back. The stacked package structure according to claim 6, wherein the The conductive component is at least one wire for electrically connecting the second patterned circuit layer to the substrate. The stacked package structure of claim 7, wherein the first patterned circuit layer and the second patterned circuit layer are both a Redistribution Layer (RDL). A wafer stack package structure comprising: a substrate having a first surface and an opposite second surface; a first wafer on the first surface of the substrate and electrically connected to the substrate The first wafer has a first crystal back and a first active surface on opposite sides of the first wafer, and the first crystal back faces the first surface of the substrate; a second wafer on the first active surface of the first wafer, wherein the second wafer has a second active surface and a second crystal back on opposite sides of the second wafer, the second active surface and the second active surface The first active surface faces, the second active surface is configured with at least one second pad, and the first wafer has a size larger than one of the second wafers; and a first patterned circuit layer is located at the first active surface And matching with the second bonding pad; and a first bonding wire electrically connecting the first patterned circuit layer and the substrate. The stacked package structure of claim 9, wherein the first active surface is further configured with at least one first bonding pad and by a second bonding line The substrate is electrically connected to the substrate, and the first pad is spaced apart from the first patterned circuit layer by a distance. The stacked package structure of claim 9, further comprising a glue resin filled between the substrate, the first wafer and the second wafer. The stacked package structure of claim 9, wherein the first patterned circuit layer is a redistributed circuit layer.