200845334 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體封裝結構，且特別是有關於 一種堆疊封裝結構。 ' 【先前技術】 隨著電子產品功能與應用之需求的急遽增加，封裝技術 亦朝著高密度微小化、單晶片封裝到多晶片封裝、二維尺度 到三維尺度的方向發展。其中系統化封裝技術比 Package)係一種可整合不同電路功能晶片的較佳方法，利用 表面黏著（Surface Mount Technology ; SMT)製程將不同的晶 片堆疊整合於同一基板上，藉以有效縮減封裝面積。具有體 積小、南頻、南速、生產週期短與低成本之優點。 請參照第5圖，第5圖係根據一習知的晶片堆疊封裝結 構500所繪示的結構剖面圖。晶片堆疊封裝結構5〇〇包括基 板510、第一晶片520、第二晶片53〇以及複數條打線54〇 和550。其中第一晶片52〇固設於基材51〇之上，並藉由打 線540與基材510電性連接。第二晶片53〇堆疊於第一晶片 520之上，且藉由打線55〇與基板51〇電性連接。 然而，由於疊設於上層的晶片，例如第二晶片53〇，必 須遷就下層晶片（第一晶片520)的打線（打線54〇)配置，因此 上層晶片（第二晶片530)尺寸必須小於下層晶片。因此也限制 了晶片堆疊的數量與彈性。又因為上層晶片的尺寸較小，必 須延長打550的配線長度並擴大其線弧，方能使其與基材51〇 5 200845334 電性連接。當後續進行壓模製程時，該些被延長的打線容易 受到沖移，而出現短路的現象，影響製程良率。 请參照第6圖，第6圖係根據另一種習知晶片堆疊封裝 結構600所緣示的結構剖面圖。晶片堆疊封裝結構6〇〇包括 ' 基板610、第一晶片620、第二晶片630、複數條打線64〇和 . 650以及位於第一晶片620和第二晶片630之間的虛擬晶片 660。其中第一晶片620疊設於基板610上，並藉由打線64〇 ( 使第一銲墊670與基材610電性連接；虛擬晶片060疊設於第 一晶片620之上；第二晶片則疊設於虚擬晶片66〇之上，並藉 由打線650使第二銲墊680與基材61 〇電性連接。藉由尺寸 小於第一晶片620的虛擬晶片56〇的設置，不僅可在第一晶 片620和第二晶片630之間，提供足夠的佈線空間與線弧高 度，以容納打線640,而且不會限制上層晶片（第二晶片“Ο) 的堆&尺寸。因此第二晶片63〇之尺寸實質等於第一晶片㈣ 之尺寸。 f 而虛擬晶片㈣置，不僅會增加晶片堆疊的厚度，且 徒增製程成本，更限制了裝結構微小化與高密度的趨勢。 —口此有而要提供-種良率高、製程低廉且不會限制封裝 密度的晶片堆疊封裝結構。 L發明内容】 本發明的目的在提供_種晶片堆疊封裝結構，包括： 第曰曰片、第一晶片、圖案化線路層以及導電元件。 材具有第一表面以及相對 τ的弟一表面。弟一晶片位於基材 200845334 第表面，並與基材電性連接。第_ 上，第二晶片具有第_主“ #-晶片位於第-晶片之 、另乐—主動面，直由络^ / 一個第二銲墊。圖幸 /、 一主動面配置有至少 盥第形成於第二主動面之上，且 弟一知墊匹配，再經 ^ .. Μ λα 田令电70件與基材電性連接。 ^ . A ^供一種晶片堆疊封裝結構，包 ,^ #丄 乐一日日片、弟一圖案化線路層以及第200845334 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor package structure, and more particularly to a stacked package structure. [Prior Art] With the rapid increase in demand for electronic product functions and applications, packaging technology is also moving toward high-density miniaturization, single-chip packaging to multi-chip packaging, and from two-dimensional to three-dimensional. Among them, the systematic packaging technology is a better method for integrating different circuit function chips, and the surface mount technology (SMT) process is used to integrate different wafer stacks on the same substrate, thereby effectively reducing the package area. It has the advantages of small volume, south frequency, south speed, short production cycle and low cost. Referring to Figure 5, a fifth embodiment is a cross-sectional view of a structure according to a conventional wafer stack package structure 500. The wafer stack package structure 5 includes a substrate 510, a first wafer 520, a second wafer 53A, and a plurality of wires 54 and 550. The first wafer 52 is fixed on the substrate 51A and electrically connected to the substrate 510 by the wire 540. The second wafer 53 is stacked on the first wafer 520 and electrically connected to the substrate 51 by a wire 55. However, since the wafer stacked on the upper layer, for example, the second wafer 53 is, the wiring (wire 54) of the lower wafer (first wafer 520) must be disposed, so the size of the upper wafer (second wafer 530) must be smaller than that of the lower wafer. . This also limits the number and flexibility of the wafer stack. Moreover, since the size of the upper layer wafer is small, it is necessary to lengthen the wiring length of the 550 and expand the line arc to electrically connect it to the substrate 51〇 5 200845334. When the subsequent molding process is performed, the extended wire is easily subjected to the displacement, and a short circuit occurs, which affects the process yield. Please refer to FIG. 6. FIG. 6 is a cross-sectional view showing the structure of another conventional wafer-stacked package structure 600. The wafer stack package structure 6A includes a substrate 610, a first wafer 620, a second wafer 630, a plurality of wires 64A and .650, and a dummy wafer 660 between the first wafer 620 and the second wafer 630. The first wafer 620 is stacked on the substrate 610 and electrically connected to the substrate 610 by the bonding wires 64 ; (the dummy wafer 060 is stacked on the first wafer 620; the second wafer is The second pad 680 is electrically connected to the substrate 61 by wire bonding 650. The setting of the dummy chip 56 is smaller than that of the first wafer 620, not only in the first Between a wafer 620 and the second wafer 630, sufficient wiring space and line arc height are provided to accommodate the wire 640, and the stack size of the upper wafer (second wafer "Ο" is not limited. Therefore, the second wafer 63 The size of the crucible is substantially equal to the size of the first wafer (4) f. The virtual wafer (four) placement not only increases the thickness of the wafer stack, but also increases the manufacturing process cost, which further limits the trend of miniaturization and high density of the package structure. However, it is required to provide a wafer stack package structure with high yield, low process, and no limitation on package density. SUMMARY OF THE INVENTION The object of the present invention is to provide a wafer stack package structure including: a second chip, a first wafer Patterned circuit layer And the conductive member has a first surface and a surface opposite to the τ. The first wafer is located on the surface of the substrate 200845334 and is electrically connected to the substrate. On the _th, the second wafer has the first _ main "#-chip Located on the first-wafer, another music-active surface, straight-through network ^ / a second solder pad. Tu Xing /, an active surface is configured with at least 盥 formed on the second active surface, and the brother knows the mat to match And then ^.. Μ λα Tian Ling electricity 70 pieces are electrically connected to the substrate. ^ . A ^ for a wafer stack package structure, package, ^ #丄乐日日片, 弟一 patterned circuit layer and
Ο 片：有對庫基材具有第-表面與相對的第二表面。第-晶 片具有對應於該第一矣而哲 、面的弟一日日背以及相對於第一晶背 的弟一主動面。箆-曰y从从# 一曰日片^於弟一晶片之上，具有應於該第 # 一曰面的第一主動面對’其中第二主動面配置有至少一個 弟^鋅墊。第—圖案化線路層位於第-主動面之上，且與第 -銲墊匹配。並藉由第—打線電性連結第—圖案化線路層與 基材。 本發明的-較佳實施例係在堆疊晶片結構的上層片的 主動層上$成-個圖案化線路層。當上層晶片覆晶堆疊於下 層曰曰片日守，並藉由圖案化線路層的佈線，將上層晶片之銲墊 的打線位置重新分配，使其對應至晶片的邊緣，再藉由一組 導電元件使圖案化線路層與基材電性連接。 本發明的另一較佳實施例則係，下層晶片上提供一下層 圖案化線路層與上層晶片的的銲墊匹配，藉以將上層晶片之 銲墊的打線位置重新分配，再藉由打線使銲墊與基材電性連 結。 藉此，可解決習知技術中，電性連接上層晶片與基材之 打線配線長度過長以及線弧過大的問題。 200845334 因此根據以上所述之實施例，藉由本發明所提供的技術 優勢，可以解決習知晶片堆疊封裝結構良率封及封裝密度不 而的問題。 【實施方式】 為讓本發明之上述和其他目的、特徵、優點與實施例能 更明顯易懂，特提供數種晶片堆疊封裝結構作為較佳實施例Ο Piece: There is a first surface and an opposite second surface to the substrate. The first-crystal wafer has a day-to-day back corresponding to the first cymbal and a face, and an active surface opposite to the first crystal back.箆-曰y from the #一曰日片^于弟一芯片, has a first active facing should be on the #一曰面', wherein the second active surface is provided with at least one younger zinc pad. The first patterned circuit layer is over the first active surface and matches the first pad. And electrically connecting the first-patterned circuit layer and the substrate by the first-wire bonding. The preferred embodiment of the present invention is a patterned circuit layer on the active layer of the upper layer of the stacked wafer structure. When the upper layer wafer is overlaid on the lower layer of the wafer, and by patterning the wiring of the wiring layer, the bonding position of the pad of the upper wafer is redistributed to correspond to the edge of the wafer, and then by a set of conductive The component electrically connects the patterned wiring layer to the substrate. In another preferred embodiment of the present invention, the underlying wafer is provided with a pad patterned layer to match the pads of the upper wafer, thereby redistributing the bonding positions of the pads of the upper wafer, and then soldering by wire bonding. The pad is electrically connected to the substrate. Thereby, in the prior art, the problem that the length of the wire bonding wiring of the upper layer wafer and the substrate is electrically connected and the line arc is excessively large can be solved. According to the embodiments described above, the problem of the yield seal and the package density of the conventional wafer stack package structure can be solved by the technical advantages provided by the present invention. [Embodiment] The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood.
來進一步說明。 請參照第1圖，第丨圖係根據本發明的第—較佳實施例 所繪示之晶片堆疊封裝結構100的剖面示意圖。 晶片102、 '封膠樹脂 晶片堆疊封裝結構1〇〇包括：基材1〇1第一 圖案化線路層105、第二晶片1〇6、導電元件 122及多個外部連接端子1丨i。 〜基材1G1具有第—表面m以及相對於第—表面m =一表面119。在本發明的較佳實施例之中，基材如係1 導線架（Lead Frame)、印刷電路板Anting Circuit B〇ard)j 晶粒承載器（CarHer)所構成。而在本實施例之中，基材lc 係一印刷電路板，其材質例如是BT或者是刚電路板心 是其⑽性電路板1基材⑻具有—個貫穿開口⑶。御 从第aa片1〇2係藉由一黏著層（未繪示）疊設於基材⑺ 弟表面118’且第—晶片1〇2具有_個面對基材⑻合 北-主動面107,以及一個與第一主動面107相對的第一曰， 於其#纟本二&例之中’第—主動面107之—部分係黏邊 ;土 101的第一表面118;而另-部分則暴露於該貫穿開口 200845334 117。其中至少一第一銲墊117 條打線113，與基材101電性 111，且設有複數個第一銲墊 係藉由穿過貫穿開口 1丨1的一 連結。To further explain. Referring to FIG. 1, a cross-sectional view of a wafer stack package structure 100 in accordance with a first preferred embodiment of the present invention is shown. The wafer 102, 'sealant resin wafer stack package structure 1' includes: a substrate 1?1 first patterned wiring layer 105, a second wafer 1?6, a conductive member 122, and a plurality of external connection terminals 1?i. The substrate 1G1 has a first surface m and a surface 119 with respect to the first surface m. In a preferred embodiment of the invention, the substrate is constructed of a lead frame, a printed circuit board, and a die carrier (CarHer). In the present embodiment, the substrate lc is a printed circuit board, and the material thereof is, for example, BT or a rigid circuit board. The substrate (8) of the (10) circuit board 1 has a through opening (3). The slave AA film 1〇2 is stacked on the substrate (7) by an adhesive layer (not shown) and the first wafer 1〇2 has a facing substrate (8) and a north-active surface 107. And a first 相对 opposite to the first active surface 107, wherein the portion of the 'first active surface 107' is viscous; the first surface 118 of the soil 101; and the other A portion is exposed to the through opening 200845334 117. At least one of the first pads 117 is electrically connected to the substrate 101, and a plurality of first pads are provided by a connection through the through opening 1丨1.
導電几件12〇位於第一晶片102的第—晶背⑽上。在 =施例之中’導電元件120包括形成於第—晶背⑽上的 木化線路層103、至少一條打線，例如打線1〇4,以及至 個導電凸塊，例如導電凸塊116。其中圖案化線路層ι〇3 =-重佈線路層（RedistHbuticm_Layer，rdl)，且圖案化線路 層=包括複數料線，至少—條導線之—端往第—晶片1〇2 之第-晶背108的邊緣延伸’並藉由打線m與基材ι〇ι電 性連結；另一端則與導電凸塊116電性連結。 第二晶片106位於第一晶片1〇2上方，且第二晶片 面對第曰曰>；102之第二主動自1〇9酉己置有至少一個第二鲜 塾，例如第二銲塾UG’以及-個與第二銲墊11G相互匹配 的圖案化線路層1〇5。其中圖案化線路層1〇5包括複數條導 線，至少一條導線之一端與第二銲墊11〇之一者電性連結， 另一端則與導電凸塊116之一者相互匹配。當第二晶片'°1〇6 以覆晶方式疊設於第一晶片1〇2上時’至少—個第二銲塾ιι〇 即可藉由圖案化線路層1G5、導電凸塊116、圖案化線路層 以及打線1〇4與基材電性連結。 封膠樹脂120則係填充於基材101、第一晶片1〇2及第 二晶片106之間，最後再於基材的第二表面119形成複數個 外部連接端子111。這些外部端子lu較佳可以是，例如是 錫球。藉由這些外部連接端子m，可以將晶片堆疊封裝結 9 200845334 構100電性連接至其他外部電路。 在本發明的一些實施例中，圖案化線路層105可以配合 不同阳片的#塾配置改變配線圖案，再配合導電元件m的 圖案化線路層103、打線104以及導電凸塊116的佈線變化， 可大·1½增加堆豐封裝結構中線路配置的靈活性。因此當具有 與第日日#102相同尺寸的第二晶片106與第一晶片102相 互堆疊時，圖案化線路層1G5和導電元件m可以將原來靠 近苐二晶片1〇6中心的楚— 々 弟一一墊110，或者是將其他位置的 第-#墊11G重新佈線，使第二銲墊ug可以對應至第二晶 片106的其他位置，例如對應至第二晶片·的邊緣，並使 第二鲜塾U〇與基# 101電性連結，而不會產生佈線過長或 線弧過大的問題。 在本發明的另外-些實施例中，第二晶片1〇6的第二銲 墊^經過圖案化線路層105和導電元件12〇的重新佈線 後第B曰片101和第二晶片1〇6可以配合多種不同線路設 計的基材，以使晶片的堆疊適應各種封裝結構之設計。 請參照第2圖，第2圖餘據本發明的第二較佳實施例 所繪不之晶片堆疊封裝結構2〇〇的剖面示意圖。 晶片堆疊封裝結構包括：基材2G1帛—晶片2〇2、 第二圖案化線路層2〇5、第二晶片襄、導電元件220以及 封膠樹脂222及多個外部連接端子2丨}。 外基材201具有第—表面218以及相對於第一表面218的 弟-表面219。在本發明的較佳實施例之中，基材扣 導線架、印刷電路板或晶粒承載器所構成，其材質例如是Μ 200845334 或者是FR4電路板或者是其他軟性電路板 ^ ^ a u . 弟一晶片202係藉由一黏著居（去 ^ ^ 71δ 4者層（未繪不）疊設於基材201 t弟一表面218，且該^_ati Μα 且仏4 2G2具有-個背對基材2〇1 的弟一主動面208，以及一個盥第_ 日H7 α — ”弟主動面208相對的第一 日日月207。在本貫施例之中，第一主 望一 ^曰埶？17 # 動面208具有至少一個 弟~墊217’而第一銲墊217传蕪出 基請電性連結。 係错由-條弟二打線212與 Ο c ㈣元件220位於第_晶片2()2的第—主動面細上。 在本貫施例之中，導電元件22〇 U匕括形成於弟一主動面208 上的弟一圖案化線路層203、至少一乞 204 , ri Β , ㈢㈧至^條打線，例如第一打線 乂及至個導電凸塊’例如導電凸塊216。其中第一 圖案化線路層203係一重佈绫踗厣B # 佈線路層且弟-圖案化線路層203 包括複數條導線，例如第—導線2仏和第二導線遍。 叙中至夕條第一導線2〇3a之—端往第一晶片202之第 一動面208的邊緣延伸，並藉由第_打線2〇4，使第一導 線203a與基材2〇1電性遠社·望一道 連、、、。，弟一 V線203a另一端則與導電 凸塊216電性連結。而 彳木弟一 V線203b之一端與位 、一主動面208上的第一銲墊217電性連姓·第—導 203b的另外一破目p士斤 电Γ生遷、、、口，弟一 V線 一曰 、< 弟一晶片202其他位置延伸，例如往第 曰曰 '之第一主動面2〇8的邊緣延伸，。再藉由第二打 ”、〜，使第一晶片202可與基材201電性連結。 ^二晶片裏位於第—晶片搬上方，以二晶片施 面對弟一晶片2〇2之第一 ^ ^ ^ 弟一主動面209，配置有至少一個第二 ‘墊，例如第二銲塾210,以及一個與第二輝塾21〇相互匹 11 200845334 配的第二圖案化線路層205。 其中第二圖案化線路層205包括複數條導線，例如第二 導線205a和第四導線205b。其中至少有一條導線，例如第 三205a，之一端與第二銲墊210之一者電性連結，第三導線 . 205a之另一端則與導電凸塊216之一者相互匹配。當第二晶 • 片206以覆晶方式疊設於第一晶片202上時，至少一個第二 鮮塾210即可藉由第二圖案化線路層2〇5的第三導線2〇5&、 ( 導電凸塊216、第一圖案化線路層203的第一導線203a以及 ' 第一打線2〇4與基材201電性連結。 封膠樹脂220則係填充於基材201、第一晶片2〇2及第 二晶片206之間，最後再於基材2〇1的第二表面219形成複 數個外部連接端子211，這些外部端子較佳可以是，例如是 錫球。藉由這些外部連接端子211，可以將晶片堆疊封裝結 構200電性連接至其他外部電路。 在本發明的一些實施例中，第二圖案化線路層2〇5可以 配合不同晶片的銲墊配置改變配線圖案，再配合導電元件 220的第圖案化線路層203、第一打線204以及導電凸塊 6的佈線臺化，可大幅增加堆疊封裝結構中線路配置的靈 活性。因此當具有與第一晶片2〇2相同尺寸的第二晶片206 與第-晶片202相互堆疊時，第二圖案化線路層2()5和導電 几件細可以將原來靠近第二晶41〇6中心的第二銲墊21〇 或者疋其他位置的第二銲塾21()重新佈線，再經由導電元件 3使第-銲塾210可以對應至第二晶片施的邊緣，並使 第#墊210與基材2〇1電性連結，而不會產生佈線過長或 12 200845334 線弧過大的問題。 在本發明的另外一些實施例中，第二晶片寫的第二辉 :ιο =弟二圖案化線路層2〇5和導電元件㈣的重新佈 設1 十的ϋ片201和第二^片鹰可以配合多種不同線路 又& 土 以使晶片的堆疊適應各種封裝結構之設計。 :“知第3圖’第3圖係根據本發明的第三較佳實施例 所繪示之晶片堆疊封裝結構3〇〇的剖面示意圖。A plurality of conductive members 12 are located on the first crystal back (10) of the first wafer 102. In the embodiment, the conductive element 120 includes a wooded wiring layer 103 formed on the first crystal back (10), at least one wire, such as a wire 1〇4, and a conductive bump, such as a conductive bump 116. Wherein the patterned circuit layer ι〇3 =- redistributed circuit layer (RedistHbuticm_Layer, rdl), and the patterned circuit layer = including a plurality of material lines, at least - the end of the wire to the first - the first back of the first wafer 1 〇 2 The edge of the extension 108 is electrically connected to the substrate ι〇ι by the wire m; the other end is electrically connected to the conductive bump 116. The second wafer 106 is located above the first wafer 1〇2, and the second wafer facing the second surface of the second substrate has at least one second fresh sputum, for example, the second solder 塾UG' and a patterned circuit layer 1〇5 matching the second pad 11G. The patterned circuit layer 1 〇 5 includes a plurality of wires, one end of the at least one wire is electrically connected to one of the second pads 11 , and the other end is matched with one of the conductive bumps 116 . When the second wafer '°1〇6 is overlaid on the first wafer 1〇2 in a flip chip manner, 'at least one second solder bump 〇ι〇 can be patterned by the wiring layer 1G5, the conductive bump 116, the pattern The circuit layer and the wire 1〇4 are electrically connected to the substrate. The sealant resin 120 is filled between the substrate 101, the first wafer 1〇2 and the second wafer 106, and finally a plurality of external connection terminals 111 are formed on the second surface 119 of the substrate. These external terminals lu may preferably be, for example, solder balls. With these external connection terminals m, the wafer stack package can be electrically connected to other external circuits. In some embodiments of the present invention, the patterned circuit layer 105 can change the wiring pattern in accordance with the #塾 configuration of the different positive electrodes, and then match the wiring changes of the patterned wiring layer 103, the wiring 104, and the conductive bumps 116 of the conductive element m. The large 11⁄2 increases the flexibility of the line configuration in the stack package structure. Therefore, when the second wafer 106 having the same size as the first day #102 and the first wafer 102 are stacked on each other, the patterned wiring layer 1G5 and the conductive member m can be close to the center of the second wafer 1〇6. One pad 110, or re-wiring the #-pad 11G at other locations, so that the second pad ug can correspond to other locations of the second wafer 106, for example to the edge of the second wafer, and make the second The fresh 塾U〇 is electrically connected to the base #101 without causing the problem that the wiring is too long or the line arc is too large. In still other embodiments of the present invention, the second pad of the second wafer 1〇6 passes through the patterned wiring layer 105 and the rewiring of the conductive element 12A after the second B slice 101 and the second wafer 1〇6 Substrates that can be designed with a variety of different traces to accommodate stacking of wafers for a variety of package designs. Referring to FIG. 2, FIG. 2 is a cross-sectional view showing a wafer stack package structure 2A according to a second preferred embodiment of the present invention. The wafer stack package structure includes a substrate 2G1 帛-wafer 2 〇 2, a second patterned wiring layer 2 〇 5, a second wafer cassette, a conductive member 220, and a sealant resin 222 and a plurality of external connection terminals 2 丨}. The outer substrate 201 has a first surface 218 and a second surface 219 opposite the first surface 218. In a preferred embodiment of the present invention, the substrate buckle lead frame, the printed circuit board or the die carrier is made of a material such as Μ 200845334 or an FR4 circuit board or other flexible circuit board ^ ^ au . A wafer 202 is stacked on the surface 201 of the substrate 201 by an adhesive layer (not shown), and the ^_ati Μα and 仏4 2G2 have a back-to-substrate 2〇1's younger one active face 208, and one 盥th day _ H7 α — ” brother active face 208 relative to the first day of the sun and the moon 207. In the present example, the first main hope one ^? 17# The moving surface 208 has at least one younger pad 217' and the first bonding pad 217 is electrically connected. The error is caused by - the second line 212 and the Ο c (four) element 220 is located at the first wafer 2 () In the present embodiment, the conductive element 22〇U includes a patterned circuit layer 203 formed on the active surface 208, at least one 乞204, ri Β, (3) (8) To the wire, for example, the first wire and the conductive bumps, such as the conductive bumps 216. The first patterned circuit layer 203 is a red tape. The 厣B #布线层层和弟- patterned circuit layer 203 includes a plurality of wires, such as a first wire 2仏 and a second wire. The middle wire of the first wire 2〇3a is forwarded to the first wafer 202. The edge of the first moving surface 208 extends, and by the first wire 2〇4, the first wire 203a and the substrate 2〇1 are electrically connected to each other, and the second wire is 203a. One end is electrically connected to the conductive bump 216. The one end of the V-line 203b is electrically connected to the first pad 217 on the active surface 208, and the other one is broken.士金电Γ生迁,,,口,弟一V线一曰,< 弟一芯片202 extends at other locations, for example, to the edge of the first active surface 2〇8 of Dijon'. The second hit ", ~, so that the first wafer 202 can be electrically connected to the substrate 201. ^ The second wafer is located above the first wafer, and the first wafer is facing the second wafer 2〇2 ^ ^ ^ An active surface 209 is provided with at least one second 'pad, such as a second pad 210, and a second patterning with the second illuminator 21 2008 The circuit layer 205. The second patterned circuit layer 205 includes a plurality of wires, such as a second wire 205a and a fourth wire 205b. At least one of the wires, for example, the third 205a, one of the ends and the second pad 210 Electrically coupled, the other end of the third wire 205a is matched with one of the conductive bumps 216. When the second chip 206 is stacked on the first wafer 202 in a flip chip manner, at least one second fresh The second line 2〇5&, (the conductive bump 216, the first wire 203a of the first patterned circuit layer 203, and the first wire 2〇4) of the second patterned circuit layer 2〇5 It is electrically connected to the substrate 201. The sealing resin 220 is filled between the substrate 201, the first wafer 2〇2 and the second wafer 206, and finally a plurality of external connection terminals 211 are formed on the second surface 219 of the substrate 2〇1, and the external terminals are formed. Preferably, it may be, for example, a solder ball. The wafer stack package structure 200 can be electrically connected to other external circuits by these external connection terminals 211. In some embodiments of the present invention, the second patterned circuit layer 2〇5 can change the wiring pattern in accordance with the pad configuration of different wafers, and then match the patterned circuit layer 203 of the conductive element 220, the first bonding line 204, and the conductive bump. The wiring of block 6 can greatly increase the flexibility of the line configuration in the stacked package structure. Therefore, when the second wafer 206 and the first wafer 202 having the same size as the first wafer 2〇2 are stacked on each other, the second patterned wiring layer 2() 5 and the conductive pieces may be close to the second crystal 41〇. The second pad 21 of the center 6 or the second pad 21 of the other position is rerouted, and the first pad 210 can be made to correspond to the edge of the second wafer via the conductive member 3, and the # pads are 210 is electrically connected to the substrate 2〇1 without causing the problem that the wiring is too long or the 12200845334 line arc is too large. In still other embodiments of the present invention, the second wafer written by the second wafer: ιο = Di Er patterned circuit layer 2〇5 and the conductive element (4) are re-arranged for ten ϋ 201 201 and the second 鹰 鹰With a variety of different lines and & soil to make the stack of wafers adapt to the design of various package structures. Fig. 3 is a cross-sectional view showing a wafer stack package structure 3A according to a third preferred embodiment of the present invention.
晶片堆疊封裝結構300包括：基材3〇1第一晶片3〇2、 第^圖案化線路層305、第二晶片裏、導電元件320、封穋 树月曰322及多個外部連接端子3 11。 基材301具有第一表面321以及相對第一表面32ι的第 二表面323。在本發明的較佳實施例之中，基材3〇丨係由導 線架、印刷電路板或晶粒承載器所構成，其材質例如是π 或者是FR4電路板或者是其他軟性電路板。而在本實施例之 中，基材301係一印刷電路板，且基材3〇1具有一個貫穿開 口 311 。 ' 第一晶片302係藉由一覆晶接合製程疊設於基材3〇1之 第一表面321，且此第一晶片3〇2具有一個面對基材3〇1的 第一主動面307，以及一個與第一主動面3〇7相對的第一晶 背308。在本實施例之令，第一主動面3〇7設有複數個第一 銲墊317,並且藉由複數個凸塊318，將這些第一銲墊317 與基材301電性連結。另外，更包括使用一底膠312將該些 凸塊318包覆，並藉以將第一主動面3〇7固定於基材3〇1之 第一表面321。 13 200845334 在本發明的較佳實施例之中， 形成在第-主動面3。7上，使U —個散熱縛片319 使， 主動面307經由貫穿 :旲向外延伸，藉此増加晶片堆疊封裝結構·的散熱 效果。 導電元件32〇位於第一晶片3〇2的第—晶背3〇8上。在 =施例之中，導電元件320包括形成於第一晶背规上的 弟圖案化線路層303、至少一條打線，例如打線3〇4，以 ^至少-個導電凸塊，例如導電凸塊316。其中第一圖案化 線路層3〇3係一重佈線路層，且第一圖案化線路層303包括 複數條導線，至少-條導線之—端往第—晶片搬之其他位 置延伸，例如往第-晶片3〇2的邊緣延伸，並藉由打線3〇4 與基材3G1電性連結；而此導線之另—端則與導電凸塊 電性連結。 户第二晶片306位於第一晶片3〇2上方，且第二晶片3〇6 面對第一晶片302之第二主動面3〇9，配置有至少一個第二 銲墊，例如第二銲墊310，以及一個與第二銲墊31〇相互匹 配的第一圖案化線路層3〇5。其中第二圖案化線路層包 括複數條導線，其中至少一條導線之一端與第二銲墊31〇之 一者電性連結，另一端則與導電凸塊316之一者相互匹配。 當第二晶片306以覆晶方式疊設於第一晶片3〇2上時，至少 個第二銲墊310即可藉由第二圖案化線路層305、導電凸 塊316、第一圖案化線路層3〇3以及打線3〇4與基材3〇1電 性連結。 封膠樹脂322則係填充於基材301、第一晶片302及第 14 200845334 二晶片306之間，最後再於基材的第二表面323形成複數個 二卜部連接端子314，些外部端子較佳可以是，例如錫球。並 藉由故些外部連接端子314，可以使晶片堆疊封裝結構綱 電性連接至其他外部電路。 一在本發明的一些實施例中，第二圖案化線路層305可以 配合不同晶片的銲墊配置改變配線圖案，再配合導電元件 32〇的第一圖案化線路層303、打線304以及導電凸塊316 的布線全化可大幅增加堆疊封裝結構中線路配置的靈活 性。因此當具有與第一晶片302相同尺寸的第二晶片3〇6與 第曰曰片302相互堆疊時，第二圖案化線路層3〇5和導電元 件:20可以將原來靠近第二晶片306中心的第二銲墊31〇或 者是在第二晶3〇6片其他位置的第二銲墊3ig重新佈線，使 其對應至第二晶片306的邊緣，並使第二銲墊31〇與基材3〇1 電性連結，而不會產生佈線過長或線弧過大的問題。 在本發明的另外一些實施例中，第二晶片306的第二銲 塾10、、、工過第_圖案化線路層3〇5和導電元件⑽的重新佈 Λ 7灸第曰曰片301和第二晶片306可以配合多種不同線路 設計的基材，以使晶片的堆疊適應各種封裝結構之設計。 睛參照第4圖，第4圖係根據本發明 所繪^晶片堆疊封裝結構彻的剖面示意圖。 ^晶片堆疊封裝結構400包括：基材401第一晶片4〇2、 弟-圖案化線路層4G5、第二晶片傷、導電元件細以及 封膠樹脂422及多個外部連接端子414。 基材401具有第一表自418以及相對於第一表面418的 15 200845334 第二表面419。在本發明的較佳實施例之中，基材彻係由 導線架、印刷電路板或晶粒承載器所構成，其材質例如是Μ 或者是FR4電路板或者是其他軟性電路板。而在本實施例之 中’基材係一印刷電路板，且基材4〇ι具有一個 口 411 〇 、The wafer stack package structure 300 includes a substrate 3〇1, a first wafer 3〇2, a first patterned circuit layer 305, a second wafer, a conductive element 320, a sealing tree 曰322, and a plurality of external connection terminals 3 11 . . The substrate 301 has a first surface 321 and a second surface 323 opposite the first surface 32i. In a preferred embodiment of the invention, the substrate 3 is constructed of a wire frame, printed circuit board or die carrier, such as a π or FR4 circuit board or other flexible circuit board. In the present embodiment, the substrate 301 is a printed circuit board, and the substrate 3〇1 has a through opening 311. The first wafer 302 is stacked on the first surface 321 of the substrate 3〇1 by a flip chip bonding process, and the first wafer 3〇2 has a first active surface 307 facing the substrate 3〇1. And a first crystal back 308 opposite the first active surface 3〇7. In the embodiment, the first active surface 3〇7 is provided with a plurality of first pads 317, and the first pads 317 are electrically connected to the substrate 301 by a plurality of bumps 318. In addition, the bumps 318 are covered by a primer 312, and the first active surface 3〇7 is fixed to the first surface 321 of the substrate 3〇1. 13 200845334 In a preferred embodiment of the present invention, formed on the first active surface 3. 7 such that the U heat sinking tab 319 causes the active surface 307 to extend outward through the through: ,, thereby adding the wafer stack The heat dissipation effect of the package structure. The conductive member 32 is located on the first crystal back 3〇8 of the first wafer 3〇2. In the embodiment, the conductive element 320 includes a patterned circuit layer 303 formed on the first crystal back gauge, at least one wire, such as a wire 3〇4, to at least one conductive bump, such as a conductive bump. 316. The first patterned circuit layer 3〇3 is a redistributed circuit layer, and the first patterned circuit layer 303 includes a plurality of wires, and at least the ends of the wires extend to other positions of the first wafer, for example, The edge of the chip 3〇2 extends and is electrically connected to the substrate 3G1 through the wire 3〇4; and the other end of the wire is electrically connected to the conductive bump. The second wafer 306 is located above the first wafer 3〇2, and the second wafer 3〇6 faces the second active surface 3〇9 of the first wafer 302, and is configured with at least one second bonding pad, such as a second bonding pad. 310, and a first patterned circuit layer 3〇5 matching the second pad 31〇. The second patterned circuit layer comprises a plurality of wires, wherein one of the ends of the at least one wire is electrically connected to one of the second pads 31 and the other end is matched with one of the conductive bumps 316. When the second wafer 306 is stacked on the first wafer 3〇2, the at least two second pads 310 may be formed by the second patterned circuit layer 305, the conductive bumps 316, and the first patterned lines. The layer 3〇3 and the wire 3〇4 are electrically connected to the substrate 3〇1. The encapsulating resin 322 is filled between the substrate 301, the first wafer 302 and the second wafer 306, and finally a plurality of second connecting terminals 314 are formed on the second surface 323 of the substrate. It can be, for example, a solder ball. And by the external connection terminals 314, the wafer stack package structure can be electrically connected to other external circuits. In some embodiments of the present invention, the second patterned circuit layer 305 can change the wiring pattern in accordance with the pad configuration of different wafers, and then match the first patterned circuit layer 303, the wiring 304, and the conductive bumps of the conductive element 32A. The full wiring of the 316 can greatly increase the flexibility of the line configuration in the stacked package structure. Therefore, when the second wafer 3〇6 and the second wafer 302 having the same size as the first wafer 302 are stacked on each other, the second patterned wiring layer 3〇5 and the conductive element 20 can be brought close to the center of the second wafer 306. The second pad 31〇 or the second pad 3ig at other positions of the second die 3〇6 is re-routed to correspond to the edge of the second wafer 306, and the second pad 31 is bonded to the substrate. 3〇1 Electrical connection without the problem of excessive wiring or excessive arcing. In still other embodiments of the present invention, the second pad 10 of the second wafer 306, the re-wiring, and the re-wiring of the conductive layer (10) The second wafer 306 can be mated to a variety of substrates of different circuit designs to accommodate the stacking of wafers to accommodate various package designs. Referring to Fig. 4, Fig. 4 is a schematic cross-sectional view showing the structure of the wafer stack package according to the present invention. The wafer stack package structure 400 includes a substrate 401, a first wafer 4, a patterned circuit layer 4G5, a second wafer damage, a conductive member thin, and a sealant 422, and a plurality of external connection terminals 414. Substrate 401 has a first gauge from 418 and a second surface 419 of 15 200845334 relative to first surface 418. In a preferred embodiment of the invention, the substrate is constructed entirely of leadframes, printed circuit boards or die carriers, such as Μ or FR4 boards or other flexible boards. In the present embodiment, the substrate is a printed circuit board, and the substrate 4 〇 has a port 411 〇 ,
弟B曰片4〇2係藉由一黏著層（未繪示）疊設於基材 之第一表面418 ’且此第一晶片402具有一個面對基材4〇1 的第-主動面407,以及一個與第—主動面術相對的第一 ，背408。在本實施例之中，第—主動面彻之—部分係黏 著於基材4G1的第-表面4丨8;而另_部分則暴露於該貫穿開 口 41卜且設有複數個第—銲墊417。其中至少一個㈣417 係藉由牙過貫穿開口 411的一條打線413，與基材4〇1電性 連結。 第二晶片406具有一第二主動面4〇9以及相對於第二主 動面409的第二晶f 412。在本實施例之中，第二晶背化 藉由一黏著層（未繪示），固設於第一晶片4〇2的第一晶背4⑽ 上。且第二晶片406的第二主動面4〇9，配置有至少一個第 二銲墊410,以及一個與第二銲墊41〇相互匹配的第二圖案 化線路層405。其中第二圖案化線路層4〇5係一重佈線路層， 包括複數條導線，其中至少—條導線之一端與第二銲塾49ι〇 之一者電性連結，另一端則往第二晶片406之第二主動面409 的邊緣延伸，並且與導電元件42〇相互匹配。 在本實施例之中，導電元件420係至少一條與打線，例 如打線，用來與基材401電性連結。 16 200845334 封膠樹脂420則係填充於基材4〇1、第一晶片4〇2及第 二晶片406之間，最後再於基材401的第二表面419形成複 數個外部連接端子414，這些外部端子41丨較佳可以是，例 錫球藉由這些外部連接端子411，可以將晶片堆疊封裝 結構400電性連接至其他外部電路。 在本貫施例中，第二圖案化線路層4〇5可以配合不同晶 片的鋅墊配置改變配線圖案，將第二銲墊41〇的打線位置重 新刀配，亚往第二晶片4〇6的其他位置，例如是第二晶片4㈧ 邊緣延伸’再藉由導電元件42()(打線)使第二銲墊㈣與基材 401電性連結。 清茶照第7圖，第7 ®係根據本發明的第五較佳實施例 所緣示之晶片堆疊封裝結構7〇〇的剖面示意圖。 一晶片堆疊封裝結構70〇包括：基材701第一晶片702、 第二圖案化線路層7〇5、第二晶片706、導電元件72〇以及 封膠樹脂722及多個外部連接端子711。 外基材7〇1具有第—表面718以及相對於第一表面718的 =二表面719。在本發明的較佳實施例之中，基材7〇1係由 ¥線木、印刷電路板或晶粒承載器所構成，其材質例如是bt 或者疋FR4電路板或者是其他軟性電路板。 第曰曰片702係藉由一黏著層（未繪示）疊設於基材7〇1 的第-^叙*且該第_晶片7G2具有一個背對基材701 曰一 以及—個與第一主動面708相對的第一 晶背707。在本實施例中， 7弟 第-銲墊717。 #-主動面708具有至少一個 17 端往第-晶片7G2之第-主動面谓的邊緣延伸，並藉由第 -打線704’使導線與基材7()1電性連結；導線的另—端則鱼 導電凸塊716電性連結。在本實施例中，第一圖案化線路層 703與導電凸塊716電性連結的導線，又同時與第一鮮墊 電性連結，並藉由第一打線704使第一銲墊717與基材7〇1 導通。The B film 4〇2 is stacked on the first surface 418′ of the substrate by an adhesive layer (not shown) and the first wafer 402 has a first active surface 407 facing the substrate 4〇1. And a first, back 408 opposite to the first-active face. In this embodiment, the first active surface is partially adhered to the first surface 4丨8 of the substrate 4G1; and the other portion is exposed to the through opening 41 and provided with a plurality of first pads. 417. At least one (four) 417 is electrically connected to the substrate 4〇1 by a wire 413 passing through the opening 411. The second wafer 406 has a second active surface 4〇9 and a second crystal f 412 with respect to the second active surface 409. In this embodiment, the second crystallization is fixed on the first crystal back 4 (10) of the first wafer 4 2 by an adhesive layer (not shown). And the second active surface 4〇9 of the second wafer 406 is provided with at least one second pad 410 and a second patterned wiring layer 405 matching the second pad 41〇. The second patterned circuit layer 4〇5 is a redistributed circuit layer, and includes a plurality of wires, wherein at least one of the wires is electrically connected to one of the second pads 49ι and the other end is directed to the second wafer 406. The edge of the second active surface 409 extends and mates with the conductive elements 42A. In the present embodiment, at least one of the conductive members 420 is wire-bonded, for example, wire-bonded, for electrically connecting to the substrate 401. 16 200845334 The encapsulating resin 420 is filled between the substrate 4〇1, the first wafer 4〇2 and the second wafer 406, and finally a plurality of external connection terminals 414 are formed on the second surface 419 of the substrate 401. The external terminal 41 can preferably be such that the solder ball can electrically connect the wafer stack package structure 400 to other external circuits by using the external connection terminals 411. In the present embodiment, the second patterned circuit layer 4〇5 can change the wiring pattern in accordance with the zinc pad configuration of different wafers, and re-align the wire bonding position of the second pad 41〇 to the second wafer 4〇6. Other locations, such as the second wafer 4 (eight) edge extension 'and then electrically connect the second pad (4) to the substrate 401 by conductive elements 42 (). Fig. 7 is a cross-sectional view showing a wafer stack package structure 7A according to a fifth preferred embodiment of the present invention. A wafer stack package structure 70 includes a substrate 701, a first wafer 702, a second patterned wiring layer 7.5, a second wafer 706, a conductive member 72A, and a sealant resin 722 and a plurality of external connection terminals 711. The outer substrate 7〇1 has a first surface 718 and a second surface 719 with respect to the first surface 718. In a preferred embodiment of the present invention, the substrate 〇1 is composed of a wire, a printed circuit board or a die carrier, and is made of, for example, a bt or 疋 FR4 circuit board or other flexible circuit board. The second wafer 702 is stacked on the substrate 7〇1 by an adhesive layer (not shown) and the first wafer 7G2 has a back-to-substrate 701 and a An active surface 708 is opposite the first crystal back 707. In the present embodiment, the 7th pad-pad 717. The active surface 708 has at least one end extending toward the edge of the first active surface of the first wafer 7G2, and electrically connecting the wire to the substrate 7()1 by the first bonding wire 704'; The fish conductive bumps 716 are electrically connected. In this embodiment, the first patterned wiring layer 703 and the conductive bump 716 are electrically connected to the first fresh pad and electrically connected to the first fresh pad, and the first bonding pad 717 is grounded by the first bonding wire 704. Material 7〇1 is turned on.
200845334 導電元件™位於第一晶片702的第一主動面7〇8上。 在本!施例之中’導電元件72G包括形成於第-主動面观 上的弟-圖案化線路層703、至少—條打線，例如第一打線 704,以及至少一個導電凸塊’例如導電凸塊μ。其中第一 圖案化線路層703係一重佈、線路層，且第_圖案化線路層期 包括複數條導線，第一圖案化線路層7〇3至少一條導線之一 第一日曰片706位於第一晶片702上方，且第二晶片7〇6 面對第一晶片702之第二主動面709，配置有至少一個第二 銲墊，例如第二銲墊710，以及一個與第二銲墊71〇相互匹 配的第二圖案化線路層705。 其中第一圖案化線路層705包括複數條導線，其中至少 有一條導線之一端與第二銲墊710之一者電性連結，而此導 線之另一端則與導電凸塊716之一者相互匹配。當第二晶片 706以覆晶方式疊設於第一晶片702上時，至少一個第二銲 墊710即可藉由第二圖案化線路層705、導電凸塊716、第 一圖案化線路層703以及第一打線704與基材701電性連 結。由於第一圖案化線路層703可同時與第一晶片702的第 一銲墊717以及第二晶片706的第二銲墊710導通，因此第 18 200845334 一銲墊71與第二銲墊710可傳輸相同訊號。 曰封膠樹脂720則係填充於基材7〇1、第一晶片7〇2及第 一曰曰片706之間，最後再於基材7〇1的第二表面719形成複 數個外連接端子7U，這些外部端子較佳可以是，例如是 錫球。藉由⑨些外部連接端子7U，可以將晶片堆疊封裝結 構700電性連接至其他外部電路。200845334 The conductive element TM is located on the first active surface 7〇8 of the first wafer 702. In the present embodiment, the conductive element 72G includes a younger-patterned wiring layer 703 formed on the first active surface, at least one wire, such as a first wire 704, and at least one conductive bump, such as a conductive bump. Block μ. The first patterned circuit layer 703 is a redistribution layer and a circuit layer, and the first patterned circuit layer layer includes a plurality of wires, and the first patterned circuit layer 7〇3 is at least one of the wires. Above a wafer 702, and the second wafer 7〇6 faces the second active surface 709 of the first wafer 702, at least one second bonding pad, such as the second bonding pad 710, and one and the second bonding pad 71 are disposed. A second patterned circuit layer 705 that matches each other. The first patterned circuit layer 705 includes a plurality of wires, wherein one end of at least one of the wires is electrically connected to one of the second pads 710, and the other end of the wire is matched with one of the conductive bumps 716. . When the second wafer 706 is stacked on the first wafer 702 in a flip chip manner, the at least one second pad 710 may pass through the second patterned circuit layer 705, the conductive bumps 716, and the first patterned circuit layer 703. The first bonding wire 704 is electrically connected to the substrate 701. Since the first patterned wiring layer 703 can be simultaneously connected to the first pad 717 of the first wafer 702 and the second pad 710 of the second wafer 706, the 18th 200845334 solder pad 71 and the second pad 710 can be transferred. The same signal. The sealant resin 720 is filled between the substrate 7〇1, the first wafer 7〇2 and the first wafer 706, and finally a plurality of external connection terminals are formed on the second surface 719 of the substrate 7〇1. 7U, these external terminals may preferably be, for example, solder balls. The wafer stack package structure 700 can be electrically connected to other external circuits by the nine external connection terminals 7U.
在本發明的一些實施例中，第二圖案化線路層705可以 配合不同晶片的銲墊配置改變配線圖案，再配合導電元件 720的第一圖案化線路層7〇3、第一打線7〇4以及導電凸塊 716的佈線&化’可大幅增加堆疊封裝結構中線路配置的靈 活性。因此當具有與第一晶片702相同尺寸的第二晶片7〇6 與第-晶片7〇2相互堆疊時，第二圖案化線路層7〇5和導電 元件720可以將原來靠近第二晶片706中心的第二銲塾71〇 或者是其他位置的第二録墊71〇重新佈線，再經由導電元件 二20一使第—#塾71〇可以對應至第二晶片观的邊緣，並使 第-知塾710與基材7〇1電性連結，而不會產生佈線過長或 線弧過大的問題。 在本lx月的另外一些實施例中，第二晶片的第二 塾/10經過第二圖案化線路層7G5和導電it件72G的重新 :後’第一晶片701和第二晶片706可以配合多種不同線 心十:基材’以使晶片的堆疊適應各種封裝結構之設計。 :參第8圖’第8圖係根據本發明的第六較佳實施 所、’曰不之日日片叠封裝結構綱的剖面示意圖。 日日片堆$封裝結構8〇〇包括：基材8(H、第一晶片8〇2 19 200845334 第-圖案化線路層8G3a、第二晶片m、第 膠樹脂815及多個外部連接端子⑽。 、、、、、 二第一表面806以及相對第-表面8。6的第 ::面广。在本發明的較佳實施例之中，基材 印刷電路板或晶粒承載器所構成，其材質例如是Β丁 I，：：4電路板或者是其他軟性電路板。而在本實施例之 中，基材801係一印刷電路板。 第一晶片802具有一個面對基材8〇1的第一主動面 曰’以及一個與第一主動面8〇8相對的第一晶背_，且第 -晶片802的第-晶背_係藉由表面接合製程疊設於基材 綱之第-表面806。此在本實施例之中，第一主動面8〇8 设有複數個第—銲墊810，並且藉由第-打線803,將這些 第一銲墊810與基材8〇1電性連結。 第二晶片804位於第-晶片802上方，且第二晶片8〇4 面對第一晶片802之第二主動面8U，配置有至少一個第二In some embodiments of the present invention, the second patterned circuit layer 705 can change the wiring pattern in accordance with the pad configuration of different wafers, and then match the first patterned circuit layer 7〇3 of the conductive element 720, the first bonding line 7〇4. And the routing &lification of the conductive bumps 716 can greatly increase the flexibility of the line configuration in the stacked package structure. Therefore, when the second wafer 7〇6 and the first wafer 7〇2 having the same size as the first wafer 702 are stacked on each other, the second patterned wiring layer 7〇5 and the conductive member 720 may be close to the center of the second wafer 706. The second soldering pad 71〇 or the second recording pad 71〇 at another position is re-routed, and then the first to the second wafer view via the conductive element 20#, and the first knowledge is made The crucible 710 is electrically connected to the substrate 7〇1 without causing a problem that the wiring is too long or the arc is too large. In still other embodiments of the present invention, the second 塾/10 of the second wafer passes through the second patterned circuit layer 7G5 and the conductive ED 72G: the first 'first wafer 701 and the second wafer 706 can be combined with a plurality of Different cores: substrate 'to make the stack of wafers adapt to the design of various package structures. Fig. 8 is a cross-sectional view showing the outline of a package structure according to a sixth preferred embodiment of the present invention. The Japanese wafer stack package structure 8 includes: a substrate 8 (H, a first wafer 8〇2 19 200845334 a first patterned circuit layer 8G3a, a second wafer m, a first resin 815, and a plurality of external connection terminals (10) The first surface 806 and the first surface of the first surface 8.6 are wider than the first surface 8.6. In a preferred embodiment of the invention, the substrate printed circuit board or the die carrier is formed. The material is, for example, a Kenting I, ::4 circuit board or other flexible circuit board. In the present embodiment, the substrate 801 is a printed circuit board. The first wafer 802 has a facing substrate 8〇1. a first active surface 曰' and a first crystal back _ opposite to the first active surface 8 〇 8 , and the first crystal back _ of the first wafer 802 is stacked on the substrate by a surface bonding process - surface 806. In this embodiment, the first active surface 8 〇 8 is provided with a plurality of first pads 810, and the first pads 810 and the substrate 8 〇1 are formed by the first bonding wires 803 The second wafer 804 is located above the first wafer 802, and the second wafer 8〇4 faces the second active surface 8U of the first wafer 802, and is configured with at least Second
C 銲塾，例如第二鲜塾812。其中第二晶片綱的尺寸小於第 一晶片802的尺寸。 第一圖案化線路層803a位於第一晶片8〇2的第一主動面 808上，且與第一銲電81〇相距有一段距離。因此第一圖案 化線路層803a並未與第一銲電81〇直接電性連接。第一圖案 =線路層803a包括複數條導線，其中至少一條導線之一端與 第二銲墊812之一者相互匹配，並藉由導電凸塊813彼此電 性連結；另一端則往第一晶片802之其他位置延伸，例如往第 一晶片802之第一主動面808的邊緣延伸，並藉由第二打線 20 200845334 8 1 4與基材8 〇 1電性連結。 一曰封膠樹脂815則係填充於基材80卜第-晶片8〇2及第 曰曰片804之間，最後再於基材801的第二表面8〇7形成複 v 數^外σ卩連接端子8G5，較佳的，該些外部端子例如是錫球， 、 I猎由沒些外部連接端子805,可以使晶片堆疊封裝結構8〇〇 電性連接至其他外部電路。 在本實施例中，第一圖案化線路層8〇%可以配合第二晶 # 804之第二銲墊812的配置，改變配線圖案的佈線變化， ，其對應至第-晶片8〇2的邊緣，使與基材3〇1電性連結的 第二打線814,不會有佈線過長或線弧過大的問題。可大幅 支曰加堆$封裝結構中線路配置的靈活性。 根據以上所述，本發明的—較佳實施例係在晶片堆疊結 構的的上層晶片的主動層，形成_個上層圖案化線路層，使 上層圖案化線路層與上層晶片的銲塾匹配，藉以將上層晶片 之銲墊的打線位置重新分配，再藉由導電元件使辉墊與基材 0 電性連結。 本發明的另—較佳實施例則係，下層晶片上提供一下層 圖案化線路層與上層晶片的的銲塾匹配，藉以將上層晶片之 銲塾的打線位置重新分配，再藉由打線使銲墊與基材電性連 結。 藉此不僅可以配合不同上層晶片之銲墊設計，來改電圖 案化線路層中的佈線，以提供上層晶片多樣化㈣擇空間。 當上層晶片與下層晶片具有相同尺寸時，更可將上層晶片之 銲墊的打線位置重新分配，使其分散至晶片的邊緣，而不會 21 200845334 ^生佈線過長或線弧過大的叫。_ 更可大幅降低堆疊厚度度 …线虛擬B曰片， 另外本發明# ^ ^ ，同時提高封裝密度。 力月的一些實施 晶片與上層晶片之間的下厚_ 包括位於下層 線路層的佈線和上層圖宰 ，，中下層圖案化 晶堆疊於下層晶片時s路層相互匹配。當上層晶片覆 路層電性連結。再t由^線^化^路層會與下層圖案化線 f 接。由於上層目t 層與基材電性連 活性。 隹且封裝、、·°構中線路配置與設計的靈 因此’藉由本發明所提供的技術特徵，可 片堆疊《結構良率封及封裝密度不高的問題，更可解決: =產品多樣性設導致製程元件無法制，衍生成本過 題。 a雖然本發明已以較佳實施例揭露如上，然其並非用以限 疋本發明，任何相關技術領域具有通常知識者，在不脫離本 發明之精神和範_ ’當可作各種之更動與潤飾，因此本發 明之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 為讓本發明之上述和其他目的、特徵、優點與實施例能 更明顯易懂，所附圖式之詳細說明如下： 第1圖係根據本發明的第一較佳實施例所繪示之晶片堆 22 200845334 疊封裝結構100的剖面示意圖。 第2圖係根據本發明的第二較佳實施例所繪示之晶片堆 且封裝結構200的剖面示意圖。 晶第3圖係根據本發明的第三較佳實施例所繪示之晶片堆 且封衣結構3 0 0的剖面示意圖。 請參照第4圖’第4圖係、根據本發明㈣四較佳實施例 所綠二之晶片堆疊封裝結構的剖面示意圖。C Weld, such as the second fresh 塾812. The size of the second wafer is smaller than the size of the first wafer 802. The first patterned wiring layer 803a is located on the first active surface 808 of the first wafer 8〇2 and at a distance from the first soldering 81〇. Therefore, the first patterned wiring layer 803a is not directly electrically connected to the first soldering wire 81A. The first pattern=the circuit layer 803a includes a plurality of wires, wherein one of the ends of the at least one wire and the second pad 812 are matched with each other, and electrically connected to each other by the conductive bumps 813; the other end is directed to the first wafer 802. The other locations extend, for example, to the edge of the first active surface 808 of the first wafer 802, and are electrically connected to the substrate 8 〇1 by the second bonding wire 20 200845334 8 1 4 . A sealant resin 815 is filled between the substrate 80 - the first wafer 8 〇 2 and the second wafer 804, and finally forms a complex v number σ outside the second surface 8 〇 7 of the substrate 801 The connection terminal 8G5, preferably, the external terminals are, for example, solder balls, and the external connection terminals 805 are used to electrically connect the wafer stack package structure 8 to other external circuits. In this embodiment, the first patterned circuit layer 8〇% can be matched with the configuration of the second pad 812 of the second crystal #804, changing the wiring variation of the wiring pattern, which corresponds to the edge of the first wafer 8〇2 The second wire 814 electrically connected to the substrate 3〇1 has no problem that the wiring is too long or the wire arc is too large. The flexibility of the line configuration in the $package structure can be greatly supported. According to the above, the preferred embodiment of the present invention is based on the active layer of the upper wafer of the wafer stack structure, forming an upper patterned circuit layer, so that the upper patterned circuit layer matches the solder of the upper wafer, thereby The wire bonding position of the pad of the upper wafer is redistributed, and the glow pad is electrically connected to the substrate 0 by a conductive member. In another preferred embodiment of the present invention, the underlying wafer is provided with a solder layer of the underlying patterned circuit layer and the upper wafer, thereby redistributing the bonding positions of the solder pads of the upper wafer, and then soldering by wire bonding. The pad is electrically connected to the substrate. In this way, not only the pad design of different upper wafers can be matched, but also the wiring in the circuit layer can be modified to provide a variety of space for the upper wafer. When the upper wafer and the lower wafer have the same size, the bonding positions of the pads of the upper wafer can be redistributed to be dispersed to the edge of the wafer without being too long or too large. _ can greatly reduce the thickness of the stack ... line virtual B ,, in addition to the invention # ^ ^, while increasing the packing density. Some implementations of the force month The under-thickness between the wafer and the upper wafer _ includes the wiring and the upper layer of the lower layer, and the s-layers match each other when the middle-lower patterned crystal is stacked on the lower wafer. When the upper layer of the chip is electrically connected. Then, the line layer will be connected to the lower layer pattern line f. Since the upper layer t layer is electrically connected to the substrate.封装In addition, the structure and design of the circuit in the package, and the structure of the structure can be solved by the technical features provided by the present invention. The design causes the process components to be unmanageable, and the derivative cost is overdue. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art will be able to make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; The wafer stack 22 is illustrated as a cross-sectional view of the stacked package structure 100. 2 is a cross-sectional view of a wafer stack and package structure 200 in accordance with a second preferred embodiment of the present invention. The crystal 3 is a schematic cross-sectional view of the wafer stack and the sealing structure 300 according to the third preferred embodiment of the present invention. Referring to Figure 4, Figure 4, a cross-sectional view of a green chip stack package structure according to a fourth preferred embodiment of the present invention.
第5®係根據-f知的晶片堆疊封裝結構所繪 結構剖面圖。 弟6圖係根據另 的結構剖面圖。 種習知晶片堆疊封裝結構600所繪示 第7圖係根據本發明的第五較佳實施例所繪示之晶片堆 且'于裝結構7 0 0的剖面示意圖。 第8圖係根據本發明的第六較佳實施例所繪示之 璺封裝結構800的剖面示意圖。 【主要元件符號說明】 101 :基材 103 :圖案化線路層 105 :圖案化線路層 107 :第一主動面 109 :第二主動面 1 π:貫穿開口 Π4 :外部連接端子 100 :晶片堆疊封裝結構 102:第一晶片 ·'打線 106 ··第二晶片 108 :第一晶背 110 :第二銲墊 113 :打線 23 200845334 116 :導電凸塊 118 :基材第一表面 120 ··導電元件 200 :晶片堆疊封裝結構 202 :第一晶片 203a :第一導線 2〇4 :第一打線 205a :第三導線 206 :第二晶片 208 :第一主動面 210 :第二銲墊 214 :外部連接端子 217 :第一銲墊 219:基材的第二表面 222 :封膠樹脂 300 :晶片堆疊封裝結構 302 :第一晶片 304 ··打線 306 :第二晶片 308 :第一晶背 310 :第二銲墊 312 :底膠 316 :導電凸塊 317 :第一銲墊 117 :第一銲墊 119 :基材第二表面 122 :封膠樹脂 201 ··基材 203 :第一圖案化線路層 203b :第二導線 205 :第一圖案化線路層 205b :第四導線 207 :晶背 209 :第二主動面 212 :第二打線 216 ··導電凸塊 218 :基材的第一表面 220 :導電元件 301 :基材 303 :第一圖案化線路層 305 ··第二圖案化線路層 307 ··第一主動面 309 :第二主動面 311 :貫穿開口 314 :外部連接端子 3 1 8 :凸塊 24 200845334 319 ： 散熱鰭片 320 ： 導電元件 321 ： 基材的第一表面 322 ： 封膠樹脂 323 ： 基材的第二表面 400 ： 晶片堆疊封裝結構 401 ： 基材 402 ： 第一晶片 405 ： 第二圖案化線路層 406 ： 弟二晶片 407 ： 第一主動面 408 ： 第一晶背 409 ： 第二主動面 410 ： 第二銲墊 411 ： 貫穿開口 412 : 第二晶背 413 ： 打線 414 ： 外部連接端子 417 ： 鲜塾 418 ： 基材的第一表面 419 ： 基材的第二表面 420 ： 導電元件 422 ： 封膠樹脂 500 ： 晶片堆疊封裝結構 510 ： 基板 520 ： 第一晶片 530 ： 弟二晶片 540 ： 打線 550 : 打線 610 ： 基板 620 ： 第一晶片 630 ： 弟二晶片 640 ： 打線 650 ： 打線 660 ： 虛擬晶片 670 ： 銲塾 680 ： 銲墊 700 ： 晶片堆疊封裝結構 701 ： 基材 702 ： 弟一晶片 703 ： 第一圖案化線路層 704 ： 第一打線 705 ： 第二圖案化線路層 706 ： 弟二晶片 707 ： 第一晶背 708 ： 第一主動面 709 ： 弟-—主動面 25 200845334 710 ： 716 ·· 718 ： 720 ： 800 ： 802 ： 803a 805 ： 807 ： 809 : 811 ： 813 ： 815 ： 第二銲墊 導電凸塊 基材的第一表面 導電元件 晶片堆疊封裝結構 第一晶片 :第一圖案化線路層 外部連接端子 基材的第二表面 第一晶背 第二主動面 導電凸塊 封膠樹脂 711 :外部連接端子 717 :第一銲墊 719 :基材的第二表面 722 :封膠樹脂 801 ··基材 803 :第一打線 804 :第二晶片 806:基材的第一表面 808 ··第一主動面 810 :第一銲墊 812 :第二銲墊 814 :第二打線 26Section 5® is a cross-sectional view of the structure of the wafer stack package structure according to the -f. The brother 6 is based on a cross-sectional view of another structure. FIG. 7 is a cross-sectional view of the wafer stack and the mounting structure 700 according to the fifth preferred embodiment of the present invention. Figure 8 is a cross-sectional view of a package structure 800 in accordance with a sixth preferred embodiment of the present invention. [Main component symbol description] 101: Substrate 103: Patterned wiring layer 105: Patterned wiring layer 107: First active surface 109: Second active surface 1 π: Through opening Π4: External connection terminal 100: Wafer stacking package structure 102: first wafer · 'wire 106 · · second wafer 108 : first crystal back 110 : second pad 113 : wire 23 200845334 116 : conductive bump 118 : substrate first surface 120 · conductive element 200 : The wafer stack package structure 202: the first wafer 203a: the first wire 2〇4: the first wire 205a: the third wire 206: the second wafer 208: the first active surface 210: the second pad 214: the external connection terminal 217: First pad 219: second surface 222 of substrate: encapsulant resin 300: wafer stack package structure 302: first wafer 304 · wire 306: second wafer 308: first crystal back 310: second pad 312 : primer 316 : conductive bump 317 : first pad 117 : first pad 119 : substrate second surface 122 : sealant 201 · substrate 203 : first patterned circuit layer 203b : second wire 205: first patterned circuit layer 205b: fourth wire 207: crystal back 209: second active surface 212 : second wire 216 · conductive bump 218: first surface 220 of the substrate: conductive element 301: substrate 303: first patterned circuit layer 305 · second patterned circuit layer 307 · · first active surface 309: second active surface 311: through opening 314: external connection terminal 3 1 8 : bump 24 200845334 319 : heat sink fin 320 : conductive member 321 : first surface of substrate 322 : sealant 323 : substrate Second surface 400: wafer stack package structure 401: substrate 402: first wafer 405: second patterned circuit layer 406: second wafer 407: first active surface 408: first crystal back 409: second active surface 410 : second pad 411 : through opening 412 : second crystal back 413 : wire 414 : external connection terminal 417 : fresh 塾 418 : first surface of the substrate 419 : second surface 420 of the substrate : conductive element 422 : Glue resin 500: wafer stack package structure 510: substrate 520: first wafer 530: second wafer 540: wire 550: wire 610: substrate 620: first wafer 630: second wafer 64 0: wire 650: wire 660: virtual wafer 670: wire 680: pad 700: wafer stack package structure 701: substrate 702: chip one wafer 703: first patterned circuit layer 704: first wire 705: second Patterned wiring layer 706: second wafer 707: first crystal back 708: first active surface 709: younger--active surface 25 200845334 710: 716 · · 718 : 720 : 800 : 802 : 803a 805 : 807 : 809 : 811 : 813 : 815 : first surface conductive element of the second pad conductive bump substrate, wafer stack package structure, first wafer: first patterned circuit layer, external connection terminal substrate, second surface, first crystal back, second Active surface conductive bump sealing resin 711: external connection terminal 717: first bonding pad 719: second surface 722 of substrate: encapsulating resin 801 · substrate 803: first bonding line 804: second wafer 806: base First surface 808 of the material · first active surface 810: first bonding pad 812: second bonding pad 814: second bonding line 26