WO2018072424A1

WO2018072424A1 - Multi-chip frame package structure and manufacturing method thereof

Info

Publication number: WO2018072424A1
Application number: PCT/CN2017/082262
Authority: WO
Inventors: 谢业磊
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2016-10-17
Filing date: 2017-04-27
Publication date: 2018-04-26
Also published as: CN107958898A; CN107958898B

Abstract

A multi-chip frame package structure is provided. The package structure comprises: at least one carrier (102), at least one lower chip (105), and at least one upper chip (108). The at least one carrier is configured to accommodate the at least one lower chip and the at least one upper chip. The package structure further comprises: at least one first dielectric layer (107), in which the first dielectric layer is disposed above the lower chip, the upper chip is disposed above the first dielectric layer, and the positional relationship between the lower chip and the upper chip can be adjusted by adjusting the tilt angle of the first dielectric layer, thus increasing the number of chips stacked on the at least one carrier. Embodiments of the present invention further provide a manufacturing method of the multi-chip frame package structure.

Description

Multi-chip frame package structure and manufacturing method thereof

Cross-reference to related applications

The present application is based on a Chinese patent application filed on Jan. 17, 2016, the entire disclosure of which is hereby incorporated by reference.

Technical field

The present invention relates to semiconductor device packaging technology, and more particularly to a multi-chip frame package structure and a method of fabricating the same.

Background technique

Today, with the gradual development of electronic engineering, miniaturized, lightweight and functional integrated circuit (IC) chips are becoming more and more popular. Moreover, as the semiconductor industry's crystal garden process is about to reach a bottleneck, packaging technology will become an important role in improving the profitability of chip manufacturing and challenging Moore's Law. Under this huge demand, the density of semiconductor packaging will continue to increase, from the development of a component to the stage of assembling multiple components into one system. System-in-package (SiP) as a multi-chip packaging technology is currently the trend of future packaging technology. The package is available in a variety of forms and can be customized or flexibly produced by changing the different chip arrangement and internal bonding technology according to the needs of customers or products, and is suitable for various consumer product markets. However, as the density of SiP packages continues to increase, the number of chips that need to be built is increasing, and the difference in chip size leads to difficulties in many bonding technologies due to SiP packaging. This requires a reasonable allocation of the location and packaging of each component in the SiP package.

QFP (Quad Flat Package) is a surface mount package that connects the internal chip to the board level by taking out pins of different shapes on four sides, because the QFP intermediate frame is used for placement. The size of the chip carrier is closely related to the number of pins of the chip, thus limiting the feasibility of implementing SiP using QFP. Currently, frame-type packages are usually used to implement SiP. However, when SiP packages are completed, the size of different components can seriously limit the package density. Especially for thinner products, the number of packageable components becomes a framework-type package and promotes SiP technology. The more serious problems encountered.

Summary of the invention

In order to solve the existing technical problems, embodiments of the present invention provide a multi-chip frame package structure and a manufacturing method thereof to solve at least the above technical problems.

To achieve the above objective, the technical solution of the embodiment of the present invention is implemented as follows:

A first aspect of the embodiments of the present invention provides a multi-chip frame package structure, the package structure including: at least one carrier stage, at least one underlying chip, and at least one upper layer chip; the at least one stage is configured to be accommodated The at least one underlying chip and the at least one upper layer chip; the package structure further comprising: at least one first dielectric layer; wherein

The first dielectric layer is disposed above the underlying chip; the upper chip is disposed above the first dielectric layer; the underlying chip can be adjusted by adjusting an inclination angle of the first dielectric layer The positional relationship between the upper chips in order to increase the number of chips stacked on the at least one stage.

In the above solution, the package structure further includes: at least one second dielectric layer;

The second dielectric layer is disposed above the first layer upper chip of the at least one upper chip, and the second upper layer chip of the at least one upper chip is disposed above the second dielectric layer; wherein, by adjusting The tilt angle of the second dielectric layer can adjust a positional relationship between the first layer upper chip and the second layer upper chip in order to increase the number of chips stacked on the at least one stage.

In the above solution, the package structure further includes: a ground plane, a dielectric frame, and an extraction pin; wherein

The ground plane is configured to connect to the underlying chip and/or the upper layer chip needs to be connected Ground pad

The lead-out pin is configured to connect the bottom chip and/or the pad on the upper chip that needs to be externally led out;

The medium frame is configured to connect the at least one stage, the ground plane, and the lead-out pin, and is configured to support the multi-chip frame package structure to ensure the multi-chip frame The structure of the package structure is firm.

In the above solution, the package structure further includes: a molding body;

The molding body is configured to package the at least one carrier stage, the at least one underlying chip, the at least one upper layer chip, and the at least one first dielectric layer to: the at least one stage, at least one underlying chip, at least An upper chip and at least one first dielectric layer are encapsulated inside the plastic body.

In the above solution, the package structure further includes: at least one third dielectric layer and at least one top chip;

The third dielectric layer is disposed above the molding body, and the top chip is disposed above the third dielectric layer, and the top chip can be adjusted by adjusting an inclination angle of the third dielectric layer The position on the molding body is such as to increase the number of chips stacked on the at least one stage.

In the above solution, the package structure further includes: a metal connection line; wherein

The metal connection line is configured to connect pads between each of the bottom chip of the at least one underlying chip or each of the at least one upper chip; and/or, the underlying chip and the upper layer a pad connection between the chips; and/or a pad of the chip in the underlying chip and the upper chip that needs to be connected to the lead pin, the ground plane, and the lead pin and the ground Flat connection.

A second aspect of the embodiments of the present invention provides a method for fabricating a multi-chip frame package structure, the package structure including: at least one carrier stage, at least one underlying chip, and at least one upper layer a chip and at least one first dielectric layer; the method comprising:

Arranging the underlying chip on the at least one stage;

Disposing the first dielectric layer on the underlying chip, the first dielectric layer being disposed above the underlying chip;

The upper chip is disposed above the first dielectric layer, and the upper chip is disposed above the first dielectric layer; wherein the bottom chip can be adjusted by adjusting an inclination angle of the first dielectric layer a positional relationship with the upper chip to facilitate increasing the number of chips stacked on the at least one stage.

In the above solution, the package structure further includes: at least one second dielectric layer; and correspondingly, the method further includes:

Providing the second dielectric layer above the first layer upper chip in the at least one upper chip, and setting a second upper layer chip in the at least one upper chip above the second dielectric layer, wherein Adjusting the tilt angle of the second dielectric layer can adjust a positional relationship between the first layer upper chip and the second layer upper chip in order to increase the number of chips stacked on the at least one stage.

In the above solution, the package structure further includes: a molding body; correspondingly, the method further includes:

Encapsulating the at least one carrier stage, the at least one underlying chip, the at least one upper layer chip, and the at least one first dielectric layer to form the molding body to at least one of the carrier stages, at least one underlying chip, at least An upper chip and at least one first dielectric layer are encapsulated inside the plastic body.

In the above solution, the package structure further includes: at least one third dielectric layer and at least one top chip; and correspondingly, the method further includes:

The third dielectric layer is disposed above the molding body, and the top chip is disposed above the third dielectric layer, wherein the tilt angle of the third dielectric layer can be adjusted The position of the top chip on the molding body is to increase the number of chips stacked on the at least one stage.

The multi-chip frame package structure and the manufacturing method thereof according to the embodiments of the present invention can skillfully make the chips are angularly offset from each other through various dielectric layers of oblique angles, so that the stacked chips have enough space to wire, so The embodiment of the invention can effectively increase the number of the frame SiP package sealing chip, meet the requirements of the diversification of the package, and effectively solve the problem that the existing SiP frame package structure has limited number of chips in the multi-chip package, and the problem is increased. The number of stacked chips lays the foundation for adapting to the current demand for lighter and thinner products.

DRAWINGS

In the drawings, which are not necessarily to scale, the Like reference numerals with different letter suffixes may indicate different examples of similar components. The drawings generally illustrate the various embodiments discussed herein by way of example and not limitation.

1 is a schematic structural view 1 of a multi-chip frame package structure according to an embodiment of the present invention;

2 to FIG. 4 are schematic structural diagrams of a multi-chip frame package structure in a manufacturing process according to an embodiment of the present invention;

FIG. 5 is a second schematic structural diagram of a multi-chip frame package structure according to an embodiment of the present invention; FIG.

FIG. 6 is a schematic structural diagram 3 of a multi-chip frame package structure according to an embodiment of the present invention.

detailed description

The invention will be described in detail with reference to the accompanying drawings, and the accompanying drawings are only for the purpose of illustration.

Embodiment 1

This embodiment provides a multi-chip frame package structure; the multi-chip frame described in this embodiment The package structure can effectively increase the number of packaged SiP packaged and sealed chips, meets the requirements of diverse packages, and effectively solves the problem that the existing SiP frame package structure has a limited number of chips for multi-chip packaging; specifically, The multi-chip frame package structure includes: at least one stage, at least one underlying chip, and at least one upper chip; the at least one stage is configured to receive the at least one underlying chip and the at least one upper chip; The package structure further includes: at least one first dielectric layer; wherein the first dielectric layer is disposed above the underlying chip; the upper chip is disposed above the first dielectric layer; The tilt angle of a dielectric layer can adjust a positional relationship between the underlying chip and the upper chip to increase the number of chips stacked on the at least one stage.

In practical applications, the package structure further includes: a ground plane, a dielectric frame, an extraction lead, and a plastic package; wherein

The ground plane is configured to connect the underlying chip and/or the pad on the upper chip that needs to be grounded;

The medium frame is configured to connect the at least one stage, the ground plane, and the lead-out pin, and is configured to support the multi-chip frame package structure to ensure the multi-chip frame The structure of the package structure is firm;

The molding body is configured to package the at least one carrier stage, the at least one underlying chip, the at least one upper layer chip, and the at least one first dielectric layer to: the at least one stage, at least one underlying chip, at least An upper chip and at least one first dielectric layer are encapsulated inside the plastic body. Specifically, the molding body is configured to encapsulate the at least one carrier stage, the at least one underlying chip, the at least one upper layer chip, and the at least one first dielectric layer, and the ground plane, the dielectric frame, and the lead-out pins.

The embodiment of the present invention is further described in detail below with reference to FIG. 1; specifically, as shown in FIG. The multi-chip frame package structure includes:

At least one of the stage 102, the stage 102 is made of a metal material, and is configured to place a chip (such as an underlying chip and an upper chip) to be packaged; here, the underlying chip and the upper chip may be specifically a semiconductor chip; Correspondingly, the stage 102 is specifically configured to carry a semiconductor chip to be packaged and has a heat conducting effect;

The ground plane 103 is made of a metal material and is configured to connect pads (or pins) on the chip (such as the upper chip and/or the bottom chip) in the carrier 102 to be grounded; specifically, configured to provide The ground connection between the pad (or pin) of the chip and the external ground plane of the package (that is, the multi-chip frame package structure);

The lead pin 101 is configured to be connected to a chip (such as a chip on the upper layer and/or an underlying chip) in the stage 102 to be externally extracted; specifically, configured to provide a chip pad (or pin) and Electrical connection path of the external pins of the package;

The medium frame 104 is configured to connect the stage 102, the ground plane 103, and the lead-out pin 101, and is configured to support the entire package structure (ie, a package) to ensure the entire package. The structure is firm.

At least one underlying chip 105 is laid flat above the stage 102;

At least one first dielectric layer 107 is placed over the underlying chip 105, and at least one upper chip 108 may be placed over the first dielectric layer 107. The upper chip 108 may be in the form of a metal wire. The bottom layer chips 105 are electrically connected through the pads 106; the upper layer chips 108 may be electrically connected to the ground plane 103 or the lead-out pins 101 by metal wire bonding;

The molding body 109 is configured to connect the stage 102, the ground plane 103, the lead pin 101, the dielectric frame 104, the underlying chip 105, the dielectric layer 107, the upper chip 108, and the chip (the upper chip and/or the lower chip) The upper pad is plasticized to place the stage 102, the ground plane 103, the lead pin 101, the dielectric frame 104, the underlying chip 105, the pad 106 on the chip, and the dielectric layer 107. The upper chip 108 is wrapped around the inside of the molding body 109. In practical applications, the molding body 109 is used to fill the entire package after the entire semiconductor chip is placed.

Of course, in order to facilitate the connection between the components in the package structure, the package structure further includes: a metal connection line; wherein the metal connection line is configured to be the bottom chip or the bottom layer of the at least one underlying chip a pad connection between each of the upper chips in the at least one upper chip; and/or connecting the pad between the underlying chip and the upper chip; and/or, the underlying chip and the upper layer A pad of a chip in the chip that needs to be connected to the lead pin and a ground plane is connected to the lead pin and the ground plane. That is to say, in practical applications, the metal connection line is configured to connect the underlying chip, the upper chip, the lead-out pin, and the components in the ground plane that need to be connected.

In a specific embodiment, the package structure further includes: at least one second dielectric layer; the second dielectric layer is disposed above the first layer upper chip of the at least one upper chip, the at least one upper chip a second upper layer chip is disposed above the second dielectric layer; wherein, between adjusting the tilt angle of the second dielectric layer, between the first layer upper chip and the second layer upper chip Positional relationship in order to increase the number of chips stacked on the at least one stage. That is to say, the positional relationship can also be adjusted through the dielectric layer between the upper chips, so that the positional relationship between the upper chips can be further adjusted, thereby facilitating the increase of the number of chips stacked on the at least one stage.

In another embodiment, the package structure further includes: at least one third dielectric layer and at least one top chip; the third dielectric layer is disposed above the molding body, and the top chip is placed in the Above the third dielectric layer, the position of the top chip on the molding body can be adjusted by adjusting the inclination angle of the third dielectric layer, so as to increase the number of chips stacked on the at least one stage. That is to say, a dielectric layer can be further stacked on the upper chip, and an upper layer chip is stacked on the dielectric layer, so that it is convenient to adapt to the application scenario of multi-chip sealing.

In this way, the multi-chip frame package structure according to the embodiment of the present invention can ingeniously change the positional relationship between the stacked semiconductor chips by changing the shape of the dielectric layer added when stacking the semiconductor chips, thereby effectively improving the multi-layer chip playing. The line space makes full use of the inner space of the package size, and completes more chip sealing in the same frame, which solves the problem that the chip cannot be properly stacked due to the excessive size of the chip in the prior art, and the problem that the excessive chip cannot be sealed is solved. .

Moreover, the embodiment of the present invention can make the chips are angularly offset from each other through various inclined angle dielectric layers, so that the stacked chips have enough space to wire, thereby increasing the number of stacked chips, so as to adapt to the current It lays the foundation for the needs of lighter and thinner product applications.

In addition, since the embodiment of the present invention completes stacking of multiple chips by changing the dielectric layer, the embodiment of the present invention is lower in cost and meets the existing high performance and low cost compared with the existing method of changing the frame. Chip development needs.

Embodiment 2

The embodiment provides a method for manufacturing a multi-chip frame package structure according to the first embodiment. Specifically, the method includes:

Locating the underlying chip on the at least one stage; disposing the first dielectric layer on the underlying chip, the first dielectric layer being placed over the underlying chip; The upper layer chip is disposed above the dielectric layer, and the upper layer chip is disposed above the first dielectric layer; wherein the bottom layer chip and the upper layer chip can be adjusted by adjusting an inclination angle of the first dielectric layer A positional relationship between them in order to increase the number of chips stacked on the at least one stage.

In a specific embodiment, the package structure further includes: at least one second dielectric layer; and correspondingly, the method further includes: disposing the second layer above the first layer upper chip in the at least one upper chip a dielectric layer, a second layer upper chip of the at least one upper chip is disposed above the second dielectric layer, wherein the first layer upper chip and the first layer can be adjusted by adjusting an inclination angle of the second dielectric layer Positional relationship between the upper layers of the second layer so that And increasing the number of chips stacked on the at least one stage.

In another embodiment, the package structure further includes: a molding body; and correspondingly, the method further includes: the at least one stage, at least one underlying chip, at least one upper chip, and at least one A dielectric layer is packaged to form the molding body to encapsulate the at least one carrier stage, the at least one underlying chip, the at least one upper layer chip, and the at least one first dielectric layer in the interior of the molding body.

In a practical application, the package structure further includes: at least one third dielectric layer and at least one top chip; respectively, the method further includes: disposing the third dielectric layer above the molding body, The top chip is disposed above the third dielectric layer, wherein a position of the top chip on the molding body can be adjusted by adjusting an inclination angle of the third dielectric layer, so as to increase the at least one slide The number of chips stacked on the stage.

2 to FIG. 4 are schematic structural diagrams of a multi-chip frame package structure in a manufacturing process according to an embodiment of the present invention; the method according to the embodiment of the present invention is further described in detail below with reference to FIG. 2 to FIG. 4;

Step 1, as shown in FIG. 2, using a Candence SiP design software to complete a design of a multi-chip frame package structure having good heat dissipation characteristics; specifically, the multi-chip frame package structure includes a centrally located stage 102, distributed A lead pin 101 and a ground plane 103 around the stage 102, and a dielectric frame 104 connecting the stage 102, the lead pin 101, and the ground plane 103.

Specifically, a Kovar alloy (Fe-Ni-Co) is used as the material of the stage 102 and the lead-out pin 101 and the ground plane 103, and a multi-layer method as shown in FIG. 1 is prepared by a punching method. The chip frame; further, using hexagonal boron nitride as the material of the dielectric frame 104, the stage 102, the lead-out pin 101, and the ground plane 103 are partially joined by a die.

Here, in practical applications, the stage can be a single block or a plurality of spaced planes. The ground planes can be distributed around the entire package. The lead pin can be divided Spread around the entire package.

Step 2, as shown in FIG. 3, a bottom chip 105 is laid on the upper surface of the stage 102, and the bottom chip 105 is bonded to the stage 102 by a conductive silver paste 110.

Step 3, a metal bump 106 is prepared on the upper surface of the underlying chip 105, and the metal bump 106 is made of gold. Between the metal bumps 106 on the underlying chip 105, and the metal bumps 106 on the underlying chip 105 and the ground plane 103 and the lead-out pins 101, by ultrasonic bonding technology, according to the metal The preparation of the electrical interconnection 111 is completed in the form of a wire. The material of the interconnect is silver.

Step 4, as shown in FIG. 4, a first dielectric layer 107 is placed on the underlying chip 105, and the first dielectric layer 107 is bonded over the underlying chip 105 by a die attach film 112. The material of the first dielectric layer 107 is hexagonal boron nitride. Here, the first dielectric layer may be set to a different shape as needed.

Step 5, as shown in FIG. 4, an upper layer chip 108 is placed on the upper surface of the first dielectric layer 107, and the upper layer chip 108 is bonded over the first dielectric layer 107 by a die bonding film.

In step six, a metal bump 106 is prepared on the upper surface of the upper chip 108, and the metal bump 106 is made of gold. The metal bumps 106 on the upper chip 108 and the metal bumps 106 on the underlying chip 105 and the metal bumps 106 on the upper chip 108 and the ground plane 103 and the lead-out pins The preparation of the electrical metal interconnection 111 is completed in the form of metal wire by ultrasonic bonding technique between 101. The material of the metal interconnect (ie, the metal connection) is silver.

Step 7: As shown in FIG. 1 , after the entire chip stack is completed, the entire package structure is plastically sealed by using a transfer molding technique in the entire package, and the silicone package is used as a material of the molding compound 109 to complete the fixing of the entire package. . After the plastic molding is completed, the stage 102, the ground plane 103, the lead pin 101, the dielectric frame 104, the bottom chip 105, and the solder on the chip The disk 106, the first dielectric layer 107, and the upper chip 108 are all located inside the molded body 109.

Here, the metal bumps described above are pads on the chip; further, the above-mentioned carrier stage, ground plane, and lead pin materials are Kovar alloy (Fe-Ni-Co), alloy 42 (Alloy42) And one of the copper alloys; the method for preparing the metal interconnect is a wire bonding technique in thermocompression bonding and ultrasonic bonding; the material of the metal bump is gold, silver, lead One of the tin alloys; the material of the metal interconnection may be one of aluminum, gold, silver, copper, and palladium; the material of the dielectric layer and the dielectric frame may be hexagonal boron nitride, white gemstone, One of a spinel and a ceramic; the preparation method of the molded body is one of a transfer molding technique, a spray molding technique, and a preforming technique; and the material of the molded body is a phenolic resin or a silicone resin. .

In practical applications, as shown in FIG. 5, on the basis of the package structure shown in FIG. 1, a dielectric layer is stacked on the upper chip, and a top chip is stacked on the dielectric layer to accommodate multi-chip bonding. Further, as shown in FIG. 6 , inside the package, different sizes of the underlying chips can be placed above the carrier, and the dielectric layers of different shapes are also placed to complete the multi-chip packaging requirements, thereby adapting to More application scenarios.

The specific embodiments of the present invention have been described in detail, and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and scope of the present invention are intended to be included within the scope of the present invention.

Industrial applicability

The embodiment of the present invention can make the chips in the angled manner of the dielectric layers of the various angles, so that the chips in the stack have sufficient space to be wired. Therefore, the embodiment of the present invention can effectively increase the frame SiP package. The number of chips satisfies the needs of various packages, and effectively solves the problem that the number of chips in the existing SiP frame package structure is limited for multi-chip packaging, and increases the number of stacked chips, so as to adapt to the current lighter and thinner The product application requirements laid the foundation.

Claims

A multi-chip frame package structure comprising: at least one stage, at least one underlying chip, and at least one upper chip; the at least one stage configured to receive the at least one underlying chip and the At least one upper layer chip; the package structure further comprising: at least one first dielectric layer; wherein

The first dielectric layer is disposed above the underlying chip; the upper chip is disposed above the first dielectric layer; the underlying chip can be adjusted by adjusting an inclination angle of the first dielectric layer The positional relationship between the upper chips in order to increase the number of chips stacked on the at least one stage.
The multi-chip frame package structure according to claim 1, wherein the package structure further comprises: at least one second dielectric layer;

The second dielectric layer is disposed above the first layer upper chip of the at least one upper chip, and the second upper layer chip of the at least one upper chip is disposed above the second dielectric layer; wherein, by adjusting The tilt angle of the second dielectric layer can adjust a positional relationship between the first layer upper chip and the second layer upper chip in order to increase the number of chips stacked on the at least one stage.
The multi-chip frame package structure according to claim 1 or 2, wherein the package structure further comprises: a ground plane, a dielectric frame, and an extraction lead; wherein

The ground plane is configured to connect the underlying chip and/or the pad on the upper chip that needs to be grounded;

The lead-out pin is configured to connect the bottom chip and/or the pad on the upper chip that needs to be externally led out;

The medium frame is configured to connect the at least one stage, the ground plane, and the lead-out pin, and is configured to support the multi-chip frame package structure to ensure the multi-chip frame The structure of the package structure is firm.
The multi-chip frame package structure according to claim 1 or 2, wherein the package structure further comprises: a molding body;

The molding body is configured to package the at least one carrier stage, the at least one underlying chip, the at least one upper layer chip, and the at least one first dielectric layer to: the at least one stage, at least one underlying chip, at least An upper chip and at least one first dielectric layer are encapsulated inside the plastic body.
The multi-chip frame package structure according to claim 4, wherein the package structure further comprises: at least one third dielectric layer and at least one top chip;

The third dielectric layer is disposed above the molding body, and the top chip is disposed above the third dielectric layer, and the top chip can be adjusted by adjusting an inclination angle of the third dielectric layer The position on the molding body is such as to increase the number of chips stacked on the at least one stage.
The multi-chip frame package structure according to claim 1 or 2, wherein the package structure further comprises: a metal connection line;

The metal connection line is configured to connect pads between each of the bottom chip of the at least one underlying chip or each of the at least one upper chip; and/or, the underlying chip and the upper layer a pad connection between the chips; and/or a pad of the chip in the underlying chip and the upper chip that needs to be connected to the lead pin, the ground plane, and the lead pin and the ground Flat connection.
A method of fabricating a multi-chip frame package structure, the package structure comprising: at least one carrier stage, at least one underlying chip, at least one upper layer chip, and at least one first dielectric layer; the method comprising:

Arranging the underlying chip on the at least one stage;

Disposing the first dielectric layer on the underlying chip, the first dielectric layer being disposed above the underlying chip;

The upper chip is disposed above the first dielectric layer, and the upper chip is disposed above the first dielectric layer; wherein the bottom chip can be adjusted by adjusting an inclination angle of the first dielectric layer a positional relationship with the upper chip to facilitate increasing the number of chips stacked on the at least one stage.
The method of claim 7, wherein the package structure further comprises: at least one second dielectric layer; and correspondingly, the method further comprises:

Providing the second dielectric layer above the first layer upper chip in the at least one upper chip, and setting a second upper layer chip in the at least one upper chip above the second dielectric layer, wherein Adjusting the tilt angle of the second dielectric layer can adjust a positional relationship between the first layer upper chip and the second layer upper chip in order to increase the number of chips stacked on the at least one stage.
The method according to claim 7 or 8, wherein the package structure further comprises: a molding body; correspondingly, the method further comprises:

Encapsulating the at least one carrier stage, the at least one underlying chip, the at least one upper layer chip, and the at least one first dielectric layer to form the molding body to at least one of the carrier stages, at least one underlying chip, at least An upper chip and at least one first dielectric layer are encapsulated inside the plastic body.
The method of claim 9, wherein the package structure further comprises: at least one third dielectric layer and at least one top chip; and correspondingly, the method further comprises:

The third dielectric layer is disposed above the molding body, and the top chip is disposed above the third dielectric layer, wherein the top chip can be adjusted by adjusting an inclination angle of the third dielectric layer The position on the molding body is to increase the number of chips stacked on the at least one stage.