WO2017107548A1 - Heat dissipating multi-chip frame package structure and preparation method therefor - Google Patents

Heat dissipating multi-chip frame package structure and preparation method therefor Download PDF

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Publication number
WO2017107548A1
WO2017107548A1 PCT/CN2016/097607 CN2016097607W WO2017107548A1 WO 2017107548 A1 WO2017107548 A1 WO 2017107548A1 CN 2016097607 W CN2016097607 W CN 2016097607W WO 2017107548 A1 WO2017107548 A1 WO 2017107548A1
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Prior art keywords
semiconductor chip
chip
package structure
heat sink
metal heat
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PCT/CN2016/097607
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French (fr)
Chinese (zh)
Inventor
谢业磊
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深圳市中兴微电子技术有限公司
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Publication of WO2017107548A1 publication Critical patent/WO2017107548A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to heat dissipation technology in the field of semiconductor device packaging, and in particular to a heat dissipation multi-chip frame package structure and a preparation method thereof.
  • SiP system-in-package
  • Quadrature Flat No-lead Package which has a rectangular appearance, a horizontal soldered end on the bottom of the component, and a pad for heat conduction in the center, which is realized around the periphery of the large pad.
  • the soldered end of the electrical connection, the chip conducts heat through the thermal pad on the bottom of the package to the heat sink.
  • the existing frame SiP package integrates multiple chips, so that the total power consumption increases sharply.
  • the heat dissipation channel at the bottom of the package is not enough to conduct the heat of the chip to the PCB, which easily leads to failure of the entire frame package system due to overheating. .
  • an embodiment of the present invention provides a heat dissipation multi-chip frame seal. Packing structure and preparation method thereof.
  • At least one conductive pad for providing an electrical connection path between the chip pin and the external pin of the package; a thermal pad; at least two underlying semiconductor chips placed over the thermal pad; A metal heat sink over the uppermost semiconductor chip for providing a heat dissipation path for the underlying semiconductor chip.
  • the package structure further includes:
  • One or more upper semiconductor chips placed over the underlying semiconductor chip.
  • the package structure further includes:
  • the conductive pad, the thermal pad, the underlying semiconductor chip, the upper semiconductor chip, and the metal heat sink are located inside the molding body, and the upper surface of the molding body is flush with the upper surface of the metal heat sink, and The upper surface of the metal heat sink is exposed to the plastic body.
  • the package structure further includes:
  • the metal heat dissipation cover being located on an upper surface of the molding body and in contact with the metal heat sink.
  • the underlying semiconductor chip is electrically connected to the conductive pad by a metal wire
  • the upper semiconductor chip is electrically connected to the underlying semiconductor chip and the conductive pad by a metal wire. connection.
  • the conductive pad is configured to provide an electrical connection path between the chip pin and the external pin of the package;
  • a metal heat sink is disposed over the uppermost semiconductor chip for providing a heat dissipation path for the underlying semiconductor chip.
  • the method further includes:
  • One or more upper semiconductor chips are placed over the underlying semiconductor chip.
  • the method further includes:
  • the conductive pad, the thermal pad, the underlying semiconductor chip, the upper semiconductor chip, and the metal heat sink are encapsulated inside the plastic package;
  • Sanding is performed on an upper surface of the molding body such that an upper surface of the molding body is flush with an upper surface of the metal heat sink, and an upper surface of the metal heat sink is exposed to the molding body.
  • the method further includes:
  • a metal heat dissipation cover is disposed on the upper surface of the molding body, and the metal heat dissipation cover is disposed in contact with the metal heat sink.
  • the method further includes:
  • the upper semiconductor chip and the underlying semiconductor chip and the conductive pad are electrically connected by a metal wire.
  • the heat-dissipating multi-chip frame package structure has good heat dissipation characteristics
  • the package structure includes: at least one conductive pad for providing a chip pin and a package external pin Electrical connection path; thermal pad; at least two underlying semiconductor chips placed over the thermally conductive pad; a metal heat sink disposed over the uppermost semiconductor chip, the metal heat sink being used to provide the underlying semiconductor chip Cooling channel.
  • a metal heat sink is added for each of the uppermost semiconductor chips, and the metal heat sink can respectively set different heat sinks according to different semiconductor chip sizes and heat dissipation requirements.
  • the structure can greatly improve the flexibility of multi-chip frame package structure design. For the chips with different heights after stacking, different heights of metal heat sinks are set, so that the overall structure height is controllable. Finally, a metal heat dissipation cover is added to the upper surface of the metal heat sink, and the package structure of the embodiment of the invention can effectively increase the heat dissipation of each semiconductor chip. Improve the heat dissipation of the entire package system.
  • FIG. 1 is a schematic structural view of a frame formed by a conductive pad and a heat conductive pad according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a package structure after placing a plurality of chips on a heat conductive pad according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a package structure after adding a heat sink according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram 1 of a package structure completed in the embodiment of the present invention.
  • FIG. 5 is a second schematic diagram of a package structure according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram 3 of a package structure according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram 4 of a package structure in an embodiment of the present invention.
  • FIG. 8 is a schematic flow chart of a method for fabricating a heat dissipation multi-chip frame package structure according to an embodiment of the present invention.
  • the embodiment of the present invention provides a multi-chip frame package structure with good heat dissipation characteristics and a preparation method thereof. It can effectively increase the heat dissipation channel of the frame SIP package and improve the thermal conductivity of the package structure.
  • At least one conductive pad for providing an electrical connection path between the chip pin and the external pin of the package; a thermal pad; at least two underlying semiconductor chips placed over the thermal pad; a metal heat sink over the uppermost semiconductor chip, the metal heat sink
  • the device is used to provide a heat dissipation channel for the underlying semiconductor chip.
  • the package structure further includes one or more upper semiconductor chips placed over the underlying semiconductor chip.
  • the package structure may not include the upper semiconductor chip, and the number of upper semiconductor chips may be set according to actual conditions.
  • the conductive pad, the thermal pad, the underlying semiconductor chip, the upper semiconductor chip, and the metal heat sink are located inside the molding body, the upper surface of the molding body is flush with the upper surface of the metal heat sink, and the metal heat sink The upper surface is exposed to the molded body.
  • the upper surface of the molding body has a metal heat dissipation cover, and the metal heat dissipation cover is in contact with the metal heat sink.
  • the underlying semiconductor chip may be electrically connected to the conductive pad in the form of a metal wire
  • the upper semiconductor chip may be in the form of a metal wire and the underlying semiconductor chip and the guide.
  • the electrical pads are electrically connected.
  • the package structure includes: at least one conductive pad 101 for providing an electrical connection path between the chip pin and the external pin of the package;
  • thermally conductive pad 102 the thermally conductive pad 102 being made of a metal material
  • At least two underlying semiconductor chips 103 are placed on top of the thermally conductive pads 102.
  • One or more upper semiconductor chips 202 may be placed over the underlying semiconductor chips 103.
  • the chip 103 may be electrically connected to the conductive pad 101 by a metal wire, and the upper semiconductor chip may be electrically connected to the underlying semiconductor chip 103 and the conductive pad 101 by metal wire bonding;
  • the film provides a heat dissipation channel
  • the molding body 108, the conductive pad 101, the thermal pad 102, the underlying semiconductor chip 103, the upper semiconductor chip 202, and the metal heat sink 109 are all located inside the molding body 108, and the upper surface of the molding body 108 and the metal The upper surface of the heat sink 109 is flush, and the upper surface of the metal heat sink 109 is exposed to the molding body 108;
  • the metal heat dissipation cover 110 is located on the upper surface of the molding body 108 and is in contact with the metal heat sink 109.
  • the metal heat sink 109 is a zigzag metal heat sink 109.
  • the metal heat sink 109 may have other shapes.
  • the shape of the metal heat sink 109 can be prepared according to a specific application.
  • the embodiment of the invention further provides a method for preparing a heat dissipation multi-chip frame package structure. As shown in FIG. 8 , the method for preparing the heat dissipation multi-chip frame package structure includes the following steps:
  • Step 801 Set a thermal pad.
  • Step 802 Locating at least one conductive pad around the heat conductive pad, the conductive pad is used to provide an electrical connection path between the chip pin and the external pin of the package.
  • a lead frame of a multi-chip package is prepared, the frame includes a thermal pad, and at least one conductive pad is provided around the thermally conductive pad.
  • the heat conductive pad and the conductive pad material are one of Alloy 42 (Alloy 42), copper alloy and Kovar alloy (Fe-Ni-Co).
  • Step 803 placing at least two underlying semiconductor chips over the thermally conductive pads.
  • the underlying semiconductor chips are at least two and placed in a tile.
  • one or more upper semiconductor chips are placed over the underlying semiconductor chip.
  • the underlying semiconductor chip and the conductive pad are electrically connected by metal wire bonding; the upper semiconductor chip and the bottom are electrically connected by metal wire bonding. a layer semiconductor chip and the conductive pad.
  • metal bumps are prepared on the upper surface of the underlying semiconductor chip.
  • An electrical interconnection line is formed between the metal bump on the upper surface of the underlying semiconductor chip and the conductive pad.
  • Metal bumps are formed on the upper surface of the upper semiconductor chip. Between the metal bumps on the upper surface of the upper semiconductor chip, the metal bump on the upper surface of the upper semiconductor chip and the upper surface metal bump of the underlying semiconductor chip and the upper surface metal bump of the upper semiconductor chip An electrical interconnection is prepared between the block and the conductive pad.
  • the method for preparing the electrical interconnection line is a wire bonding technique in ultrasonic bonding and thermocompression bonding.
  • the material of the electrical interconnect may be one of aluminum, gold, silver, copper, and palladium.
  • the material of the metal bump is one of gold and lead-tin alloy.
  • Step 804 Providing a metal heat sink over the uppermost semiconductor chip, the metal heat sink for providing a heat dissipation channel for the underlying semiconductor chip.
  • the material of the metal heat sink is copper.
  • a metal heat sink is prepared on the upper surface of the uppermost semiconductor chip, and the package is plastically sealed.
  • the conductive pad, the thermal pad, the underlying semiconductor chip, the upper semiconductor chip, and the metal heat sink are encapsulated inside the molded body. Sanding is performed on an upper surface of the molding body such that an upper surface of the molding body is flush with an upper surface of the metal heat sink, and an upper surface of the metal heat sink is exposed to the molding body.
  • the preparation method of the plastic sealing body is one of a transfer molding technology, a spray molding technology, and a preform molding technology.
  • the material of the molded body is one of a phenol resin and a silicone resin.
  • a metal heat dissipation cover is disposed on the upper surface of the molding body, and the metal heat dissipation cover is disposed in contact with the metal heat sink.
  • the material of the metal heat dissipation cover is one of copper, gold, silver and aluminum.
  • the heat dissipation multi-chip frame package structure of the embodiment of the present invention is combined with a specific application scenario.
  • the preparation method is explained in detail.
  • a design of a multi-chip frame package structure having good heat dissipation characteristics is completed by using Candence SiP design software.
  • At least one conductive pad 101 is first provided, and a thermal pad 102 is provided.
  • the conductive pads 101 may be distributed around the thermally conductive pads 102, and the thermally conductive pads 102 are located at the center of the conductive pads 101.
  • an alloy 42 (Alloy 42) is used as a material of the thermally conductive pad 102 and the conductive pad 101, and a multi-chip frame is prepared by a filming method.
  • two underlying semiconductor chips 103, 201 are placed on the upper surface of the thermally conductive pad 102, and the underlying semiconductor chips 103, 201 are bonded to the thermally conductive pad 102 by a conductive silver paste 104.
  • Metal bumps 105 are formed on the upper surfaces of the underlying semiconductor chips 103 and 201, and the metal bumps 105 are made of gold.
  • a thermocompression bonding technique is performed between the metal bumps 105 on the upper surface of the underlying semiconductor chips 103 and 201 and between the metal bumps 105 on the upper surface of the underlying semiconductor chips 103, 201 and the conductive pads 101,
  • the preparation of the electrical interconnects 106 is completed in the form of metal wires.
  • the material of the metal interconnect 106 is gold.
  • An upper semiconductor chip 202 is further placed on the underlying semiconductor chip 201, and the upper semiconductor chip 202 is bonded over the underlying semiconductor chip 201 by a die attach film 107.
  • Metal bumps 105 are formed on the upper surface of the upper semiconductor chip 202, between the metal bumps 105 on the upper surface of the upper semiconductor chip 202 and the metal bumps 105 on the upper surface of the underlying semiconductor chip 201, and the upper semiconductor
  • the preparation of the electrical interconnections 106 is performed in the form of metal wires by a thermocompression bonding technique between the metal bumps 105 on the upper surface of the chip 202 and the conductive pads 101.
  • the material of the metal interconnect is gold.
  • a zigzag metal heat sink 109 is disposed on the upper semiconductor chip 202 and the underlying semiconductor chip 103 on which the upper semiconductor chip is not disposed, and the zigzag metal heat sink 109 is bonded to the chip through the die bonding film 107, according to Single chip with different heights and stacked core
  • the heat sinks of different heights are selected, so that the overall height is kept consistent after the zigzag metal heat sink 109 is disposed.
  • the entire structure is molded by using a silicone resin as a material of the molding compound 108 by a transfer molding technique. After the molding is completed, the conductive pad 101, the thermal pad 102, the underlying semiconductor chip 103, the upper semiconductor chip 202, and the zigzag metal heat dissipation are formed. The devices 109 are all located inside the molded body 108.
  • the molding body 108 above the zigzag metal heat sink 109 is removed by photochemical etching so that the upper surface of the zigzag metal heat sink 109 is exposed to the air.
  • the thermal conductive silica gel 203 is coated on the upper surface of the zigzag metal heat sink 109 to the upper surface and is flush with the surface of the molding body.
  • a metal heat dissipating cover 110 is prepared over the entire frame structure, and the metal heat dissipating cover 110 is connected to the upper surface of the zigzag metal heat sink 109 via a thermally conductive silicone 203.
  • the molding compound 108 on the upper surface of the package is directly polished, so that the zigzag metal heat sink 109 inside the package is exposed, and the heat dissipation cover 110 is directly added.
  • an upper semiconductor chip is placed over the underlying semiconductor chip 103, and then a zigzag metal heat sink 109 is further added to the upper semiconductor chip.
  • a zigzag metal heat sink 109 is further added to the upper semiconductor chip.
  • an upper semiconductor chip is placed over the underlying semiconductor chip 103, and then an in-line heat sink 204 is further added to the upper semiconductor chip.
  • the semiconductor chip in the lower layer of the stacked package can be transferred from the thermal pad to transfer the heat down to the PCB, and the upper chip has a poor surface heat dissipation effect, resulting in a higher surface temperature and less heat dissipation.
  • the multi-chip frame structure in the present invention passes through each of the uppermost semiconductor cores The method of adding a heat sink to the chip solves the heat transfer problem caused by the increase in the number of stacked chips.
  • a heat sink is added for each uppermost semiconductor chip, and the heat sink can be separately set according to different chip size and heat dissipation requirements.
  • Different heat sink structures can greatly improve the flexibility of the design of the heat dissipation structure of the multi-chip frame package.
  • a metal heat dissipation cover is added on the upper surface of the heat sink, and the structure can effectively increase the heat dissipation channel of each chip and improve the heat dissipation capability of the entire package system.
  • the disclosed method and smart device may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner such as: multiple units or components may be combined, or Can be integrated into another system, or some features can be ignored or not executed.
  • the coupling, or direct coupling, or communication connection of the components shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, and may be electrical, mechanical or other forms. of.
  • the units described above as separate components may or may not be physically separated, and the components displayed as the unit may or may not be physical units, that is, may be located in one place or distributed to multiple network units; Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one second processing unit, or each unit may be separately used as one unit, or two or two.
  • the upper unit is integrated in one unit; the above integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • a metal heat sink is added for each of the uppermost semiconductor chips, and the metal heat sinks may be respectively set according to different semiconductor chip sizes and heat dissipation requirements.
  • the heat sink structure can greatly improve the flexibility of multi-chip frame package structure design. For the chips with different heights after stacking, different heights of metal heat sinks are set, so that the overall structure height is controllable.
  • a metal heat dissipation cover is added to the upper surface of the metal heat sink.
  • the package structure of the embodiment of the invention can effectively increase the heat dissipation channel of each semiconductor chip and improve the heat dissipation capability of the entire package system.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

Disclosed are a heat dissipating multi-chip frame package structure and a preparation method therefor. The package structure comprises: at least one electrically conductive bonding pad, used for providing an electrical connection path between a chip pin and an external pin of a package body; a thermally conductive bonding pad; at least two bottom semiconductor chips placed above the thermally conductive bonding pad; and a metal radiator arranged above the uppermost semiconductor chip and used for providing a heat dissipation channel for the semiconductor chips below.

Description

一种散热的多芯片框架封装结构及其制备方法Heat dissipation multi-chip frame package structure and preparation method thereof 技术领域Technical field
本发明涉及半导体器件封装领域中的散热技术，尤其涉及一种散热的多芯片框架封装结构及其制备方法。The present invention relates to heat dissipation technology in the field of semiconductor device packaging, and in particular to a heat dissipation multi-chip frame package structure and a preparation method thereof.
背景技术Background technique
随着电子工程的发展，小型化、轻量化及功能化的需求日渐增加，导致半导体封装密度不断增加。从一个组件的开发，逐渐进入到了集结多个组件成为一个系统的阶段，在随着产品高效能及外观轻薄的要求的带动下，不同功能的芯片迈向整合的阶段。在此期间，封装技术的不断发展和突破，成为推动整合的力量之一。多芯片封装技术的一个最重要的应用—系统级封装(SiP，System in Package)概念随即被提出，SiP的封装形态多样，不同的芯片排列方式及内部接合技术可依照客户或产品的需求加以克制化或弹性生产，适用于各种消费性产品市场。SiP技术对于半导体芯片封装的整体成本、性能及可靠度有着巨大的贡献。With the development of electronic engineering, the demand for miniaturization, weight reduction, and functionalization is increasing, resulting in an increasing density of semiconductor packages. From the development of a component, it gradually entered the stage of assembling multiple components into one system. With the requirements of high efficiency and thin appearance, the chips with different functions are moving towards integration. In the meantime, the continuous development and breakthrough of packaging technology has become one of the forces driving integration. One of the most important applications of multi-chip packaging technology, the system-in-package (SiP) concept, was proposed. The SiP package is available in various forms. Different chip arrangements and internal bonding technologies can be restrained according to customer or product requirements. Chemical or flexible production, suitable for a variety of consumer products market. SiP technology has a significant contribution to the overall cost, performance and reliability of semiconductor chip packages.
方形扁平无引脚封装(QFN，Quad Flat No-lead Package)，其外观多为矩形，元件底部具有水平焊端，在中央有一个用来导热的焊盘，围绕大焊盘的外围四周有实现电气连接的焊端，芯片把热量通过封装底部的导热焊盘传导到PCB上，来进行散热。现有的框架SiP封装，集成了多颗芯片，使得总功耗急剧增大，封装底部的散热通道不足以把芯片的热量都传导到PCB上，从而极易导致整个框架封装系统因过热而失效。Square Flat No-lead Package (QFN), which has a rectangular appearance, a horizontal soldered end on the bottom of the component, and a pad for heat conduction in the center, which is realized around the periphery of the large pad. The soldered end of the electrical connection, the chip conducts heat through the thermal pad on the bottom of the package to the heat sink. The existing frame SiP package integrates multiple chips, so that the total power consumption increases sharply. The heat dissipation channel at the bottom of the package is not enough to conduct the heat of the chip to the PCB, which easily leads to failure of the entire frame package system due to overheating. .
发明内容Summary of the invention
为解决上述技术问题，本发明实施例提供了一种散热的多芯片框架封 装结构及其制备方法。In order to solve the above technical problem, an embodiment of the present invention provides a heat dissipation multi-chip frame seal. Packing structure and preparation method thereof.
本发明实施例提供的散热的多芯片框架封装结构，包括：The heat dissipation multi-chip frame package structure provided by the embodiment of the invention includes:
至少一个导电焊盘，所述导电焊盘用于提供芯片管脚与封装体外部管脚的电性连接路径；导热焊盘；放置在所述导热焊盘上方的至少两个底层半导体芯片；设置在最上层半导体芯片上方的金属散热器，所述金属散热器用于为下方的半导体芯片提供散热通道。At least one conductive pad for providing an electrical connection path between the chip pin and the external pin of the package; a thermal pad; at least two underlying semiconductor chips placed over the thermal pad; A metal heat sink over the uppermost semiconductor chip for providing a heat dissipation path for the underlying semiconductor chip.
本发明实施例中，所述封装结构还包括：In the embodiment of the present invention, the package structure further includes:
放置在所述底层半导体芯片的上方的一个或者多个上层半导体芯片。One or more upper semiconductor chips placed over the underlying semiconductor chip.
本发明实施例中，所述封装结构还包括：In the embodiment of the present invention, the package structure further includes:
塑封体，所述导电焊盘、导热焊盘、底层半导体芯片、上层半导体芯片以及金属散热器位于所述塑封体内部，所述塑封体上表面与所述金属散热器的上表面平齐，且所述金属散热器上表面裸露于所述塑封体。a molding body, the conductive pad, the thermal pad, the underlying semiconductor chip, the upper semiconductor chip, and the metal heat sink are located inside the molding body, and the upper surface of the molding body is flush with the upper surface of the metal heat sink, and The upper surface of the metal heat sink is exposed to the plastic body.
本发明实施例中，所述封装结构还包括：In the embodiment of the present invention, the package structure further includes:
金属散热盖，所述金属散热盖位于所述塑封体的上表面且与所述金属散热器相接触。a metal heat dissipation cover, the metal heat dissipation cover being located on an upper surface of the molding body and in contact with the metal heat sink.
本发明实施例中，所述底层半导体芯片通过金属打线的形式与所述导电焊盘电连接，所述上层半导体芯片通过金属打线的形式与所述底层半导体芯片以及所述导电焊盘电连接。In the embodiment of the present invention, the underlying semiconductor chip is electrically connected to the conductive pad by a metal wire, and the upper semiconductor chip is electrically connected to the underlying semiconductor chip and the conductive pad by a metal wire. connection.
本发明实施例提供的散热的多芯片框架封装结构的制备方法，包括：The method for preparing a heat dissipation multi-chip frame package structure provided by the embodiment of the invention includes:
设置导热焊盘；Setting the thermal pad;
在所述导热焊盘的周围设置至少一个导电焊盘，所述导电焊盘用于提供芯片管脚与封装体外部管脚的电性连接路径；Providing at least one conductive pad around the heat conductive pad, the conductive pad is configured to provide an electrical connection path between the chip pin and the external pin of the package;
在所述导热焊盘的上方放置至少两个底层半导体芯片；Placing at least two underlying semiconductor chips over the thermally conductive pads;
在最上层半导体芯片上方设置金属散热器，所述金属散热器用于为下方的半导体芯片提供散热通道。 A metal heat sink is disposed over the uppermost semiconductor chip for providing a heat dissipation path for the underlying semiconductor chip.
本发明实施例中，所述方法还包括：In the embodiment of the present invention, the method further includes:
在所述底层半导体芯片的上方放置一个或者多个上层半导体芯片。One or more upper semiconductor chips are placed over the underlying semiconductor chip.
本发明实施例中，所述方法还包括：In the embodiment of the present invention, the method further includes:
将所述导电焊盘、导热焊盘、底层半导体芯片、上层半导体芯片以及金属散热器封装在塑封体内部；The conductive pad, the thermal pad, the underlying semiconductor chip, the upper semiconductor chip, and the metal heat sink are encapsulated inside the plastic package;
在所述塑封体的上表面进行打磨，以使所述塑封体上表面与所述金属散热器的上表面平齐，且所述金属散热器上表面裸露于所述塑封体。Sanding is performed on an upper surface of the molding body such that an upper surface of the molding body is flush with an upper surface of the metal heat sink, and an upper surface of the metal heat sink is exposed to the molding body.
本发明实施例中，所述方法还包括：In the embodiment of the present invention, the method further includes:
在所述塑封体的上表面设置金属散热盖，所设置的金属散热盖与所述金属散热器相接触。A metal heat dissipation cover is disposed on the upper surface of the molding body, and the metal heat dissipation cover is disposed in contact with the metal heat sink.
本发明实施例中，所述方法还包括：In the embodiment of the present invention, the method further includes:
通过金属打线的形式电连接所述底层半导体芯片与所述导电焊盘；Electrically connecting the underlying semiconductor chip and the conductive pad by metal wire bonding;
通过金属打线的形式电连接所述上层半导体芯片与所述底层半导体芯片以及所述导电焊盘。The upper semiconductor chip and the underlying semiconductor chip and the conductive pad are electrically connected by a metal wire.
本发明实施例的技术方案中，散热的多芯片框架封装结构具有良好的散热特性，该封装结构包括：至少一个导电焊盘，所述导电焊盘用于提供芯片管脚与封装体外部管脚的电性连接路径；导热焊盘；放置在所述导热焊盘上方的至少两个底层半导体芯片；设置在最上层半导体芯片上方的金属散热器，所述金属散热器用于为下方的半导体芯片提供散热通道。可见，本发明实施例中的多芯片框架封装结构中，为每个最上层的半导体芯片添加一个金属散热器，所述金属散热器可以根据不同半导体芯片的尺寸和散热要求分别设置不同的散热器结构，可以极大地提高多芯片框架封装结构设计的灵活性。对于堆叠后高度不一致的芯片分别设置不同高度的金属散热器，从而使得整体结构高度可控。最后在金属散热器的上表面添加金属散热盖，本发明实施例的封装结构可以有效地增加各半导体芯片的散热通 道，提高整个封装系统的散热能力。In the technical solution of the embodiment of the present invention, the heat-dissipating multi-chip frame package structure has good heat dissipation characteristics, and the package structure includes: at least one conductive pad for providing a chip pin and a package external pin Electrical connection path; thermal pad; at least two underlying semiconductor chips placed over the thermally conductive pad; a metal heat sink disposed over the uppermost semiconductor chip, the metal heat sink being used to provide the underlying semiconductor chip Cooling channel. It can be seen that, in the multi-chip frame package structure in the embodiment of the present invention, a metal heat sink is added for each of the uppermost semiconductor chips, and the metal heat sink can respectively set different heat sinks according to different semiconductor chip sizes and heat dissipation requirements. The structure can greatly improve the flexibility of multi-chip frame package structure design. For the chips with different heights after stacking, different heights of metal heat sinks are set, so that the overall structure height is controllable. Finally, a metal heat dissipation cover is added to the upper surface of the metal heat sink, and the package structure of the embodiment of the invention can effectively increase the heat dissipation of each semiconductor chip. Improve the heat dissipation of the entire package system.
附图说明DRAWINGS
图1为本发明实施例中导电焊盘与导热焊盘所形成的的框架结构示意图；1 is a schematic structural view of a frame formed by a conductive pad and a heat conductive pad according to an embodiment of the present invention;
图2为本发明实施例中导热焊盘上放置多个芯片后的封装结构示意图；2 is a schematic diagram of a package structure after placing a plurality of chips on a heat conductive pad according to an embodiment of the present invention;
图3为本发明实施例中加入散热器后封装结构示意图；3 is a schematic diagram of a package structure after adding a heat sink according to an embodiment of the present invention;
图4为本发明实施例中制作完成的封装结构示意图一；4 is a schematic diagram 1 of a package structure completed in the embodiment of the present invention;
图5为本发明实施例中封装结构示意图二；FIG. 5 is a second schematic diagram of a package structure according to an embodiment of the present invention; FIG.
图6是本发明实施例中封装结构示意图三；6 is a schematic diagram 3 of a package structure according to an embodiment of the present invention;
图7是本发明实施例中封装结构示意图四；7 is a schematic diagram 4 of a package structure in an embodiment of the present invention;
图8为本发明实施例的散热的多芯片框架封装结构的制备方法的流程示意图。FIG. 8 is a schematic flow chart of a method for fabricating a heat dissipation multi-chip frame package structure according to an embodiment of the present invention.
具体实施方式detailed description
为了能够更加详尽地了解本发明实施例的特点与技术内容，下面结合附图对本发明实施例的实现进行详细阐述，所附附图仅供参考说明之用，并非用来限定本发明实施例。The embodiments of the present invention are described in detail below with reference to the accompanying drawings.
为了解决现有SiP框架封装结构散热能力不足，容易导致整个SiP框架封装系统失效的问题，本发明实施例提供了一种具有良好散热特性的多芯片框架封装结构及其制备方法，所述封装结构可以有效增加框架SIP封装散热通道，提高封装结构导热性。In order to solve the problem that the heat dissipation capability of the existing SiP frame package structure is insufficient, which may easily lead to the failure of the entire SiP frame package system, the embodiment of the present invention provides a multi-chip frame package structure with good heat dissipation characteristics and a preparation method thereof. It can effectively increase the heat dissipation channel of the frame SIP package and improve the thermal conductivity of the package structure.
本发明实施例的散热的多芯片框架封装结构，包括：The heat dissipation multi-chip frame package structure of the embodiment of the invention includes:
至少一个导电焊盘，所述导电焊盘用于提供芯片管脚与封装体外部管脚的电性连接路径；导热焊盘；放置在所述导热焊盘上方的至少两个底层半导体芯片；设置在最上层半导体芯片上方的金属散热器，所述金属散热 器用于为下方的半导体芯片提供散热通道。At least one conductive pad for providing an electrical connection path between the chip pin and the external pin of the package; a thermal pad; at least two underlying semiconductor chips placed over the thermal pad; a metal heat sink over the uppermost semiconductor chip, the metal heat sink The device is used to provide a heat dissipation channel for the underlying semiconductor chip.
在一种实施方式中，所述封装结构还包括：放置在所述底层半导体芯片的上方的一个或者多个上层半导体芯片。当然，所述封装结构也可以不包括上层半导体芯片，可以根据实际情况对上层半导体芯片的数目进行设置。In one embodiment, the package structure further includes one or more upper semiconductor chips placed over the underlying semiconductor chip. Of course, the package structure may not include the upper semiconductor chip, and the number of upper semiconductor chips may be set according to actual conditions.
所述导电焊盘、导热焊盘、底层半导体芯片、上层半导体芯片以及金属散热器位于塑封体内部，所述塑封体上表面与所述金属散热器的上表面平齐，且所述金属散热器上表面裸露于所述塑封体。The conductive pad, the thermal pad, the underlying semiconductor chip, the upper semiconductor chip, and the metal heat sink are located inside the molding body, the upper surface of the molding body is flush with the upper surface of the metal heat sink, and the metal heat sink The upper surface is exposed to the molded body.
位于所述塑封体的上表面具有金属散热盖，所述金属散热盖与所述金属散热器相接触。The upper surface of the molding body has a metal heat dissipation cover, and the metal heat dissipation cover is in contact with the metal heat sink.
在一种实施方式中，所述底层半导体芯片可以通过金属打线的形式与所述导电焊盘电连接，所述上层半导体芯片可以通过金属打线的形式与所述底层半导体芯片以及所述导电焊盘电连接。In one embodiment, the underlying semiconductor chip may be electrically connected to the conductive pad in the form of a metal wire, and the upper semiconductor chip may be in the form of a metal wire and the underlying semiconductor chip and the guide. The electrical pads are electrically connected.
下面结合具体应用场景对本发明实施例的散热的多芯片框架封装结构进行详细的解释说明。The heat dissipation multi-chip frame package structure of the embodiment of the present invention is explained in detail below in conjunction with a specific application scenario.
参照图4，封装结构包括：至少一个导电焊盘101，所述导电焊盘101用于提供芯片管脚与封装体外部管脚的电性连接路径；Referring to FIG. 4, the package structure includes: at least one conductive pad 101 for providing an electrical connection path between the chip pin and the external pin of the package;
导热焊盘102，所述导热焊盘102为金属材料制成；a thermally conductive pad 102, the thermally conductive pad 102 being made of a metal material;
至少两个底层半导体芯片103，所述底层半导体芯片平铺放置于所述导热焊盘102的上方，在所述底层半导体芯片103的上方可以放置一个或者多个上层半导体芯片202，所述底层半导体芯片103可以通过金属打线的形式与所述导电焊盘101进行电连接，所述上层半导体芯片可以通过金属打线的形式与所述底层半导体芯片103以及所述导电焊盘101进行电连接；At least two underlying semiconductor chips 103 are placed on top of the thermally conductive pads 102. One or more upper semiconductor chips 202 may be placed over the underlying semiconductor chips 103. The chip 103 may be electrically connected to the conductive pad 101 by a metal wire, and the upper semiconductor chip may be electrically connected to the underlying semiconductor chip 103 and the conductive pad 101 by metal wire bonding;
金属散热器109，所述金属散热器109位于所述上层半导体芯片202以及未放置上层半导体芯片的底层半导体芯片103上方，用于为其下方的芯 片提供散热通道；a metal heat sink 109 above the upper semiconductor chip 202 and the underlying semiconductor chip 103 on which the upper semiconductor chip is not placed, for the core below it The film provides a heat dissipation channel;
塑封体108，所述导电焊盘101、导热焊盘102、底层半导体芯片103、上层半导体芯片202以及金属散热器109都位于所述塑封体108内部，所述塑封体108上表面与所述金属散热器109的上表面平齐，且所述金属散热器109上表面裸露于所述塑封体108；The molding body 108, the conductive pad 101, the thermal pad 102, the underlying semiconductor chip 103, the upper semiconductor chip 202, and the metal heat sink 109 are all located inside the molding body 108, and the upper surface of the molding body 108 and the metal The upper surface of the heat sink 109 is flush, and the upper surface of the metal heat sink 109 is exposed to the molding body 108;
金属散热盖110，所述金属散热盖110位于所述塑封体108的上表面且与所述金属散热器109相接触。The metal heat dissipation cover 110 is located on the upper surface of the molding body 108 and is in contact with the metal heat sink 109.
上述方案中，所述金属散热器109为锯齿形金属散热器109，当然，金属散热器109还可以为其他形状，金属散热器109的形状可以根据具体应用情况进行制备。In the above solution, the metal heat sink 109 is a zigzag metal heat sink 109. Of course, the metal heat sink 109 may have other shapes. The shape of the metal heat sink 109 can be prepared according to a specific application.
本发明实施例还提供了一种散热的多芯片框架封装结构的制备方法，如图8所示，所述散热的多芯片框架封装结构的制备方法包括以下步骤：The embodiment of the invention further provides a method for preparing a heat dissipation multi-chip frame package structure. As shown in FIG. 8 , the method for preparing the heat dissipation multi-chip frame package structure includes the following steps:
步骤801：设置导热焊盘。Step 801: Set a thermal pad.
步骤802：在所述导热焊盘的周围设置至少一个导电焊盘，所述导电焊盘用于提供芯片管脚与封装体外部管脚的电性连接路径。Step 802: Locating at least one conductive pad around the heat conductive pad, the conductive pad is used to provide an electrical connection path between the chip pin and the external pin of the package.
本发明实施例中，制备多芯片封装的引线框架，所述框架包括一个导热焊盘，及所述导热焊盘四周至少提供一个导电焊盘。In an embodiment of the invention, a lead frame of a multi-chip package is prepared, the frame includes a thermal pad, and at least one conductive pad is provided around the thermally conductive pad.
本发明实施例中，导热焊盘及导电焊盘材料为合金42(Alloy42)、铜合金及Kovar合金(Fe-Ni-Co)中的一种。In the embodiment of the invention, the heat conductive pad and the conductive pad material are one of Alloy 42 (Alloy 42), copper alloy and Kovar alloy (Fe-Ni-Co).
步骤803：在所述导热焊盘的上方放置至少两个底层半导体芯片。Step 803: placing at least two underlying semiconductor chips over the thermally conductive pads.
本发明实施例中，所述底层半导体芯片至少为两个且平铺放置。In the embodiment of the invention, the underlying semiconductor chips are at least two and placed in a tile.
本发明实施例中，在所述底层半导体芯片的上方放置一个或者多个上层半导体芯片。In an embodiment of the invention, one or more upper semiconductor chips are placed over the underlying semiconductor chip.
本发明实施例中，通过金属打线的形式电连接所述底层半导体芯片与所述导电焊盘；通过金属打线的形式电连接所述上层半导体芯片与所述底 层半导体芯片以及所述导电焊盘。In the embodiment of the present invention, the underlying semiconductor chip and the conductive pad are electrically connected by metal wire bonding; the upper semiconductor chip and the bottom are electrically connected by metal wire bonding. a layer semiconductor chip and the conductive pad.
具体地，在所述底层半导体芯片上表面制备金属凸块。在所述底层半导体芯片上表面的金属凸块与所述导电焊盘之间制备电性互连线。在所述上层半导体芯片上表面制备金属凸块。在所述上层半导体芯片上表面的金属凸块之间，所述上层半导体芯片上表面的金属凸块与所述底层半导体芯片上表面金属凸块之间以及所述上层半导体芯片的上表面金属凸块与所述导电焊盘之间制备电性互连线。Specifically, metal bumps are prepared on the upper surface of the underlying semiconductor chip. An electrical interconnection line is formed between the metal bump on the upper surface of the underlying semiconductor chip and the conductive pad. Metal bumps are formed on the upper surface of the upper semiconductor chip. Between the metal bumps on the upper surface of the upper semiconductor chip, the metal bump on the upper surface of the upper semiconductor chip and the upper surface metal bump of the underlying semiconductor chip and the upper surface metal bump of the upper semiconductor chip An electrical interconnection is prepared between the block and the conductive pad.
本发明实施例中，电性互连线的制备方法为超声波键合、热压键合中的一种打线键合技术。电性互连线的材料可以为铝、金、银、铜、钯中的一种。In the embodiment of the invention, the method for preparing the electrical interconnection line is a wire bonding technique in ultrasonic bonding and thermocompression bonding. The material of the electrical interconnect may be one of aluminum, gold, silver, copper, and palladium.
本发明实施例中，金属凸块的材料为金、铅锡合金中的一种。In the embodiment of the invention, the material of the metal bump is one of gold and lead-tin alloy.
步骤804：在最上层半导体芯片上方设置金属散热器，所述金属散热器用于为下方的半导体芯片提供散热通道。Step 804: Providing a metal heat sink over the uppermost semiconductor chip, the metal heat sink for providing a heat dissipation channel for the underlying semiconductor chip.
本发明实施例中，金属散热器的材料为铜。In the embodiment of the invention, the material of the metal heat sink is copper.
本发明实施例中，在完成芯片的堆叠后，在最上层半导体芯片的上表面制备金属散热器，并对封装体进行塑封。将所述导电焊盘、导热焊盘、底层半导体芯片、上层半导体芯片以及金属散热器封装在塑封体内部。在所述塑封体的上表面进行打磨，以使所述塑封体上表面与所述金属散热器的上表面平齐，且所述金属散热器上表面裸露于所述塑封体。In the embodiment of the present invention, after the stacking of the chips is completed, a metal heat sink is prepared on the upper surface of the uppermost semiconductor chip, and the package is plastically sealed. The conductive pad, the thermal pad, the underlying semiconductor chip, the upper semiconductor chip, and the metal heat sink are encapsulated inside the molded body. Sanding is performed on an upper surface of the molding body such that an upper surface of the molding body is flush with an upper surface of the metal heat sink, and an upper surface of the metal heat sink is exposed to the molding body.
本发明实施例中，塑封体的制备方法为转移成型技术、喷射成型技术、预成型技术中的一种。塑封体的材料为酚醛树脂、硅胶树脂中的一种。In the embodiment of the present invention, the preparation method of the plastic sealing body is one of a transfer molding technology, a spray molding technology, and a preform molding technology. The material of the molded body is one of a phenol resin and a silicone resin.
本发明实施例中，在所述塑封体的上表面设置金属散热盖，所设置的金属散热盖与所述金属散热器相接触。In the embodiment of the invention, a metal heat dissipation cover is disposed on the upper surface of the molding body, and the metal heat dissipation cover is disposed in contact with the metal heat sink.
本发明实施例中，金属散热盖的材料为铜、金、银、铝中的一种。In the embodiment of the invention, the material of the metal heat dissipation cover is one of copper, gold, silver and aluminum.
下面结合具体应用场景对本发明实施例的散热的多芯片框架封装结构 的制备方法进行详细的解释说明。The heat dissipation multi-chip frame package structure of the embodiment of the present invention is combined with a specific application scenario. The preparation method is explained in detail.
参照图1，通过使用铿腾(Candence)SiP设计软件完成一种具有良好散热特性的多芯片框架封装结构的设计，制备封装结构时，首先提供至少一个导电焊盘101，提供导热焊盘102，所述导电焊盘101可以分布于所述导热焊盘102四周，所述导热焊盘102位于所述导电焊盘101的中央。Referring to FIG. 1, a design of a multi-chip frame package structure having good heat dissipation characteristics is completed by using Candence SiP design software. When preparing a package structure, at least one conductive pad 101 is first provided, and a thermal pad 102 is provided. The conductive pads 101 may be distributed around the thermally conductive pads 102, and the thermally conductive pads 102 are located at the center of the conductive pads 101.
这里，使用合金42(Alloy42)作为所述导热焊盘102和所述导电焊盘101的材料，通过冲膜的方法制备出多芯片框架。Here, an alloy 42 (Alloy 42) is used as a material of the thermally conductive pad 102 and the conductive pad 101, and a multi-chip frame is prepared by a filming method.
参照图2，在所述导热焊盘102上表面平铺放置两个底层半导体芯片103、201，所述底层半导体芯片103、201通过导电银胶104与所述导热焊盘102进行粘结。Referring to FIG. 2, two underlying semiconductor chips 103, 201 are placed on the upper surface of the thermally conductive pad 102, and the underlying semiconductor chips 103, 201 are bonded to the thermally conductive pad 102 by a conductive silver paste 104.
在所述底层半导体芯片103和201上表面制备金属凸块105，所述金属凸块105材料为金。在所述底层半导体芯片103和201上表面的金属凸块105之间以及所述底层半导体芯片103、201上表面的金属凸块105与所述导电焊盘101之间通过热压键合技术，按照金属打线的形式完成电性互连线106的制备。所述金属互连线106的材料为金。Metal bumps 105 are formed on the upper surfaces of the underlying semiconductor chips 103 and 201, and the metal bumps 105 are made of gold. A thermocompression bonding technique is performed between the metal bumps 105 on the upper surface of the underlying semiconductor chips 103 and 201 and between the metal bumps 105 on the upper surface of the underlying semiconductor chips 103, 201 and the conductive pads 101, The preparation of the electrical interconnects 106 is completed in the form of metal wires. The material of the metal interconnect 106 is gold.
在所述底层半导体芯片201上继续放置一个上层半导体芯片202，所述上层半导体芯片202通过芯片粘结薄膜107粘结在所述底层半导体芯片201的上方。在所述上层半导体芯片202上表面制备金属凸块105，在所述上层半导体芯片202上表面的金属凸块105与所述底层半导体芯片201上表面的金属凸块105之间以及所述上层半导体芯片202上表面的金属凸块105与所述导电焊盘101之间通过热压键合技术，按照金属打线的形式完成电性互连线106的制备。所述金属互连线的材料为金。An upper semiconductor chip 202 is further placed on the underlying semiconductor chip 201, and the upper semiconductor chip 202 is bonded over the underlying semiconductor chip 201 by a die attach film 107. Metal bumps 105 are formed on the upper surface of the upper semiconductor chip 202, between the metal bumps 105 on the upper surface of the upper semiconductor chip 202 and the metal bumps 105 on the upper surface of the underlying semiconductor chip 201, and the upper semiconductor The preparation of the electrical interconnections 106 is performed in the form of metal wires by a thermocompression bonding technique between the metal bumps 105 on the upper surface of the chip 202 and the conductive pads 101. The material of the metal interconnect is gold.
参照图3，在上层半导体芯片202以及未放置上层半导体芯片的底层半导体芯片103上设置锯齿形金属散热器109，所述锯齿形金属散热器109通过芯片粘结薄膜107与芯片进行粘结，根据不同高度的单芯片以及堆叠芯 片选择不同高度的散热器，从而使得设置锯齿形金属散热器109后，整体高度保持一致。Referring to FIG. 3, a zigzag metal heat sink 109 is disposed on the upper semiconductor chip 202 and the underlying semiconductor chip 103 on which the upper semiconductor chip is not disposed, and the zigzag metal heat sink 109 is bonded to the chip through the die bonding film 107, according to Single chip with different heights and stacked core The heat sinks of different heights are selected, so that the overall height is kept consistent after the zigzag metal heat sink 109 is disposed.
通过转移成型技术选用硅胶树脂作为塑封料108的材料对整个结构进行塑封，在塑封完成后，所述导电焊盘101、导热焊盘102、底层半导体芯片103、上层半导体芯片202以及锯齿形金属散热器109都位于所述塑封体108内部。The entire structure is molded by using a silicone resin as a material of the molding compound 108 by a transfer molding technique. After the molding is completed, the conductive pad 101, the thermal pad 102, the underlying semiconductor chip 103, the upper semiconductor chip 202, and the zigzag metal heat dissipation are formed. The devices 109 are all located inside the molded body 108.
参照图4，通过光化学刻蚀的方法将所述锯齿形金属散热器109上方的所述塑封体108去除，使得所述锯齿形金属散热器109的上表面裸露于空气之中。在所述锯齿形金属散热器109上表面涂布导热硅胶203至上表面与塑封体表面平齐。Referring to FIG. 4, the molding body 108 above the zigzag metal heat sink 109 is removed by photochemical etching so that the upper surface of the zigzag metal heat sink 109 is exposed to the air. The thermal conductive silica gel 203 is coated on the upper surface of the zigzag metal heat sink 109 to the upper surface and is flush with the surface of the molding body.
在整个框架结构上方制备金属散热盖110，所述金属散热盖110通过导热硅胶203与所述锯齿形金属散热器109的上表面相连接。A metal heat dissipating cover 110 is prepared over the entire frame structure, and the metal heat dissipating cover 110 is connected to the upper surface of the zigzag metal heat sink 109 via a thermally conductive silicone 203.
参照图5，在图3所示的封装结构的基础上，直接打磨封装上表面的塑封料108，使得封装内部的锯齿形金属散热器109裸露出来，直接添加散热盖110。Referring to FIG. 5, on the basis of the package structure shown in FIG. 3, the molding compound 108 on the upper surface of the package is directly polished, so that the zigzag metal heat sink 109 inside the package is exposed, and the heat dissipation cover 110 is directly added.
参照图6，在图2所示的封装结构的基础上，在所述底层半导体芯片103上方放置上层半导体芯片，然后在上层半导体芯片上再添加锯齿形金属散热器109。以适应更多的应用场景。Referring to FIG. 6, on the basis of the package structure shown in FIG. 2, an upper semiconductor chip is placed over the underlying semiconductor chip 103, and then a zigzag metal heat sink 109 is further added to the upper semiconductor chip. To adapt to more application scenarios.
参照图7，在图2所示的封装结构的基础上，在所述底层半导体芯片103上方放置上层半导体芯片，然后在上层半导体芯片上再添加直排式散热器204。以适应更多的应用场景。Referring to FIG. 7, on the basis of the package structure shown in FIG. 2, an upper semiconductor chip is placed over the underlying semiconductor chip 103, and then an in-line heat sink 204 is further added to the upper semiconductor chip. To adapt to more application scenarios.
本发明实施例的技术方案，具有很大的优势：The technical solution of the embodiment of the invention has great advantages:
首先，通常堆叠式封装中下层的半导体芯片可由导热焊盘传导将热向下传递到PCB上，而上方芯片由于自然对流散热效果较差，造成表面温度较高不易散热。本发明中的多芯片框架结构通过为每个最上层的半导体芯 片添加散热器的方法很好的解决了由于堆叠芯片数量增加，而导致的热传递问题。First, the semiconductor chip in the lower layer of the stacked package can be transferred from the thermal pad to transfer the heat down to the PCB, and the upper chip has a poor surface heat dissipation effect, resulting in a higher surface temperature and less heat dissipation. The multi-chip frame structure in the present invention passes through each of the uppermost semiconductor cores The method of adding a heat sink to the chip solves the heat transfer problem caused by the increase in the number of stacked chips.
其次，与现有技术相比，本发明实施例中的多芯片框架封装结构中，为每个最上层的半导体芯片添加一个散热器，所述散热器可以根据不同芯片的尺寸和散热要求分别设置不同的散热器结构，可以极大地提高多芯片框架封装散热结构设计的灵活性。而且对于堆叠后高度不一致的芯片分别设置不同高度的散热器，从而使得整体结构高度可控，也是本发明的一大亮点。Secondly, compared with the prior art, in the multi-chip frame package structure in the embodiment of the present invention, a heat sink is added for each uppermost semiconductor chip, and the heat sink can be separately set according to different chip size and heat dissipation requirements. Different heat sink structures can greatly improve the flexibility of the design of the heat dissipation structure of the multi-chip frame package. Moreover, it is also a great highlight of the present invention to provide heat sinks of different heights for the chips whose heights are inconsistent after stacking, so that the overall structure height is controllable.
最后在散热器的上表面添加金属散热盖，所述结构可以有效地增加各芯片的散热通道，提高整个封装系统的散热能力。Finally, a metal heat dissipation cover is added on the upper surface of the heat sink, and the structure can effectively increase the heat dissipation channel of each chip and improve the heat dissipation capability of the entire package system.
本发明实施例所记载的技术方案之间，在不冲突的情况下，可以任意组合。The technical solutions described in the embodiments of the present invention can be arbitrarily combined without conflict.
在本发明所提供的几个实施例中，应该理解到，所揭露的方法和智能设备，可以通过其它的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性的、机械的或其它形式的。In the several embodiments provided by the present invention, it should be understood that the disclosed method and smart device may be implemented in other manners. The device embodiments described above are merely illustrative. For example, the division of the unit is only a logical function division. In actual implementation, there may be another division manner, such as: multiple units or components may be combined, or Can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, or direct coupling, or communication connection of the components shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, and may be electrical, mechanical or other forms. of.
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元，即可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。The units described above as separate components may or may not be physically separated, and the components displayed as the unit may or may not be physical units, that is, may be located in one place or distributed to multiple network units; Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
另外，在本发明各实施例中的各功能单元可以全部集成在一个第二处理单元中，也可以是各单元分别单独作为一个单元，也可以两个或两个以 上单元集成在一个单元中；上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。In addition, each functional unit in each embodiment of the present invention may be integrated into one second processing unit, or each unit may be separately used as one unit, or two or two. The upper unit is integrated in one unit; the above integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。The above is only a specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope of the present invention. It should be covered by the scope of the present invention.
工业实用性Industrial applicability
本发明实施例的技术方案中，在多芯片框架封装结构中，为每个最上层的半导体芯片添加一个金属散热器，所述金属散热器可以根据不同半导体芯片的尺寸和散热要求分别设置不同的散热器结构，可以极大地提高多芯片框架封装结构设计的灵活性。对于堆叠后高度不一致的芯片分别设置不同高度的金属散热器，从而使得整体结构高度可控。最后在金属散热器的上表面添加金属散热盖，本发明实施例的封装结构可以有效地增加各半导体芯片的散热通道，提高整个封装系统的散热能力。 In the technical solution of the embodiment of the present invention, in the multi-chip frame package structure, a metal heat sink is added for each of the uppermost semiconductor chips, and the metal heat sinks may be respectively set according to different semiconductor chip sizes and heat dissipation requirements. The heat sink structure can greatly improve the flexibility of multi-chip frame package structure design. For the chips with different heights after stacking, different heights of metal heat sinks are set, so that the overall structure height is controllable. Finally, a metal heat dissipation cover is added to the upper surface of the metal heat sink. The package structure of the embodiment of the invention can effectively increase the heat dissipation channel of each semiconductor chip and improve the heat dissipation capability of the entire package system.

Claims (10)

  1. 一种散热的多芯片框架封装结构，所述封装结构包括：A heat dissipation multi-chip frame package structure, the package structure comprising:
    至少一个导电焊盘，所述导电焊盘用于提供芯片管脚与封装体外部管脚的电性连接路径；导热焊盘；放置在所述导热焊盘上方的至少两个底层半导体芯片；设置在最上层半导体芯片上方的金属散热器，所述金属散热器用于为下方的半导体芯片提供散热通道。At least one conductive pad for providing an electrical connection path between the chip pin and the external pin of the package; a thermal pad; at least two underlying semiconductor chips placed over the thermal pad; A metal heat sink over the uppermost semiconductor chip for providing a heat dissipation path for the underlying semiconductor chip.
  2. 根据权利要求1所述的多芯片框架封装结构，其中，所述封装结构还包括：The multi-chip frame package structure according to claim 1, wherein the package structure further comprises:
    放置在所述底层半导体芯片的上方的一个或者多个上层半导体芯片。One or more upper semiconductor chips placed over the underlying semiconductor chip.
  3. 根据权利要求2所述的多芯片框架封装结构，其中，所述封装结构还包括：The multi-chip frame package structure according to claim 2, wherein the package structure further comprises:
    塑封体，所述导电焊盘、导热焊盘、底层半导体芯片、上层半导体芯片以及金属散热器位于所述塑封体内部，所述塑封体上表面与所述金属散热器的上表面平齐，且所述金属散热器上表面裸露于所述塑封体。a molding body, the conductive pad, the thermal pad, the underlying semiconductor chip, the upper semiconductor chip, and the metal heat sink are located inside the molding body, and the upper surface of the molding body is flush with the upper surface of the metal heat sink, and The upper surface of the metal heat sink is exposed to the plastic body.
  4. 根据权利要求3所述的多芯片框架封装结构，其中，所述封装结构还包括：The multi-chip frame package structure according to claim 3, wherein the package structure further comprises:
    金属散热盖，所述金属散热盖位于所述塑封体的上表面且与所述金属散热器相接触。a metal heat dissipation cover, the metal heat dissipation cover being located on an upper surface of the molding body and in contact with the metal heat sink.
  5. 根据权利要求1所述的多芯片框架封装结构，其中，The multi-chip frame package structure according to claim 1, wherein
    所述底层半导体芯片通过金属打线的形式与所述导电焊盘电连接，所述上层半导体芯片通过金属打线的形式与所述底层半导体芯片以及所述导电焊盘电连接。The underlying semiconductor chip is electrically connected to the conductive pad in the form of a metal wire, and the upper semiconductor chip is electrically connected to the underlying semiconductor chip and the conductive pad by a metal wire.
  6. 一种散热的多芯片框架封装结构的制备方法，所述方法包括：A method for preparing a heat dissipation multi-chip frame package structure, the method comprising:
    设置导热焊盘；Setting the thermal pad;
    在所述导热焊盘的周围设置至少一个导电焊盘，所述导电焊盘用于提 供芯片管脚与封装体外部管脚的电性连接路径；Providing at least one conductive pad around the heat conductive pad, the conductive pad being used for lifting An electrical connection path between the chip pin and the external pin of the package;
    在所述导热焊盘的上方放置至少两个底层半导体芯片；Placing at least two underlying semiconductor chips over the thermally conductive pads;
    在最上层半导体芯片上方设置金属散热器，所述金属散热器用于为下方的半导体芯片提供散热通道。A metal heat sink is disposed over the uppermost semiconductor chip for providing a heat dissipation path for the underlying semiconductor chip.
  7. 根据权利要求6所述的散热的多芯片框架封装结构的制备方法，其中，所述方法还包括：The method of fabricating a heat-dissipating multi-chip frame package structure according to claim 6, wherein the method further comprises:
    在所述底层半导体芯片的上方放置一个或者多个上层半导体芯片。One or more upper semiconductor chips are placed over the underlying semiconductor chip.
  8. 根据权利要求7所述的散热的多芯片框架封装结构的制备方法，其中，所述方法还包括：The method of fabricating a heat-dissipating multi-chip frame package structure according to claim 7, wherein the method further comprises:
    将所述导电焊盘、导热焊盘、底层半导体芯片、上层半导体芯片以及金属散热器封装在塑封体内部；The conductive pad, the thermal pad, the underlying semiconductor chip, the upper semiconductor chip, and the metal heat sink are encapsulated inside the plastic package;
    在所述塑封体的上表面进行打磨，以使所述塑封体上表面与所述金属散热器的上表面平齐，且所述金属散热器上表面裸露于所述塑封体。Sanding is performed on an upper surface of the molding body such that an upper surface of the molding body is flush with an upper surface of the metal heat sink, and an upper surface of the metal heat sink is exposed to the molding body.
  9. 根据权利要求8所述的散热的多芯片框架封装结构的制备方法，其中，所述方法还包括：The method of fabricating a heat-dissipating multi-chip frame package structure according to claim 8, wherein the method further comprises:
    在所述塑封体的上表面设置金属散热盖，所设置的金属散热盖与所述金属散热器相接触。A metal heat dissipation cover is disposed on the upper surface of the molding body, and the metal heat dissipation cover is disposed in contact with the metal heat sink.
  10. 根据权利要求6所述的散热的多芯片框架封装结构的制备方法，其中，所述方法还包括：The method of fabricating a heat-dissipating multi-chip frame package structure according to claim 6, wherein the method further comprises:
    通过金属打线的形式电连接所述底层半导体芯片与所述导电焊盘；Electrically connecting the underlying semiconductor chip and the conductive pad by metal wire bonding;
    通过金属打线的形式电连接所述上层半导体芯片与所述底层半导体芯片以及所述导电焊盘。 The upper semiconductor chip and the underlying semiconductor chip and the conductive pad are electrically connected by a metal wire.
PCT/CN2016/097607 2015-12-21 2016-08-31 Heat dissipating multi-chip frame package structure and preparation method therefor WO2017107548A1 (en)

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