CN106898591A - A kind of multi-chip framework encapsulation structure of radiating and preparation method thereof - Google Patents
A kind of multi-chip framework encapsulation structure of radiating and preparation method thereof Download PDFInfo
- Publication number
- CN106898591A CN106898591A CN201510961240.2A CN201510961240A CN106898591A CN 106898591 A CN106898591 A CN 106898591A CN 201510961240 A CN201510961240 A CN 201510961240A CN 106898591 A CN106898591 A CN 106898591A
- Authority
- CN
- China
- Prior art keywords
- semiconductor chip
- metal
- chip
- welding disk
- plastic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005538 encapsulation Methods 0.000 title claims abstract description 37
- 238000002360 preparation method Methods 0.000 title claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 119
- 239000002184 metal Substances 0.000 claims abstract description 119
- 239000004065 semiconductor Substances 0.000 claims abstract description 116
- 238000003466 welding Methods 0.000 claims abstract description 51
- 230000017525 heat dissipation Effects 0.000 claims abstract description 35
- 238000004806 packaging method and process Methods 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 16
- 230000005611 electricity Effects 0.000 claims 1
- 230000008878 coupling Effects 0.000 description 18
- 238000010168 coupling process Methods 0.000 description 18
- 238000005859 coupling reaction Methods 0.000 description 18
- 239000000463 material Substances 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 7
- 239000010931 gold Substances 0.000 description 7
- 229910052737 gold Inorganic materials 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 239000002313 adhesive film Substances 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 239000000741 silica gel Substances 0.000 description 2
- 229910002027 silica gel Inorganic materials 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910017709 Ni Co Inorganic materials 0.000 description 1
- 229910003267 Ni-Co Inorganic materials 0.000 description 1
- 229910003262 Ni‐Co Inorganic materials 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007306 functionalization reaction Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 229910000648 terne Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Multi-chip framework encapsulation structure the invention discloses a kind of radiating and preparation method thereof, the encapsulating structure includes：At least one conductive welding disk, the conductive welding disk is used to provide the electrical connection path of chip pin and packaging body external terminal；Thermal land；It is placed at least two base semiconductor chips above the thermal land；The metal heat sink above the superiors' semiconductor chip is arranged on, the metal heat sink is used to provide heat dissipation channel for the semiconductor chip of lower section.
Description
Technical field
The present invention relates to the heat dissipation technology in semiconductor packages field, more particularly to a kind of multicore of radiating
Piece framework encapsulation structure and preparation method thereof.
Background technology
As the development of electronic engineering, the demand of miniaturization, lightweight and functionalization increasingly increase, cause half
Conductor packaging density is continuously increased.From an exploitation for component, having progressed into the multiple components of assembly turns into
One stage of system, under the drive of the frivolous requirement of the high-effect and outward appearance with product, difference in functionality
Chip is marched toward stage of integration.During this period, encapsulation technology is continued to develop and broken through, and is integrated as promoting
One of strength.One most important application-system in package (SiP, System of multi-chip package technology
In Package) concept is suggested immediately, the encapsulation form of diverse of SiP, different chip arrangement and interior
Portion's joining technique can be according to the applying restraint of demand or elasticity production of client or product, it is adaptable to various consumption
Property product market.SiP technologies have huge for the holistic cost of semiconductor die package, performance and reliability
Big contribution.
Quad flat non-pin package (QFN, Quad Flat No-lead Package), its outward appearance is generally rectangle,
Component base has horizontal welding end, has a pad for heat conduction in center, around the periphery four of big pad
There is the welding end for realizing being electrically connected week, heat is transmitted to PCB by chip by the thermal land of package bottom
On radiated.Existing framework SiP encapsulation, is integrated with multiple chips so that total power consumption drastically increases
Greatly, the heat dissipation channel of package bottom is not enough to the heat of chip to be all transmitted on PCB, so as to easily cause
Whole framework encapsulation system fails because of overheat.
The content of the invention
In order to solve the above technical problems, the embodiment of the invention provides a kind of multi-chip framework encapsulation knot of radiating
Structure and preparation method thereof.
The multi-chip framework encapsulation structure of radiating provided in an embodiment of the present invention, including：
At least one conductive welding disk, the conductive welding disk is used to provide chip pin with packaging body external terminal
Electrical connection path；Thermal land；It is placed at least two base semiconductor cores above the thermal land
Piece；The metal heat sink above the superiors' semiconductor chip is arranged on, the metal heat sink is used to be lower section
Semiconductor chip provide heat dissipation channel.
In the embodiment of the present invention, the encapsulating structure also includes：
It is placed on one or more upper strata semiconductor chip of the top of the base semiconductor chip.
In the embodiment of the present invention, the encapsulating structure also includes：
Plastic-sealed body, the conductive welding disk, thermal land, base semiconductor chip, upper strata semiconductor chip with
And metal heat sink is located inside the plastic-sealed body, the plastic-sealed body upper surface is upper with the metal heat sink
Flush, and the metal heat sink upper surface is exposed to the plastic-sealed body.
In the embodiment of the present invention, the encapsulating structure also includes：
Heat dissipation metal lid, the heat dissipation metal lid be located at the plastic-sealed body upper surface and with the heat dissipation metal
Device is in contact.
In the embodiment of the present invention, form and the conductive weldering of the base semiconductor chip by metal routing
Disk is electrically connected, the upper strata semiconductor chip by the form of metal routing and the base semiconductor chip with
And the conductive welding disk electrical connection.
The preparation method of the multi-chip framework encapsulation structure of radiating provided in an embodiment of the present invention, including：
Thermal land is set；
At least one conductive welding disk is set around the thermal land, and the conductive welding disk is used to provide core
The electrical connection path of piece pin and packaging body external terminal；
At least two base semiconductor chips are placed in the top of the thermal land；
Metal heat sink is set above the superiors' semiconductor chip, and the metal heat sink is used to be lower section
Semiconductor chip provides heat dissipation channel.
In the embodiment of the present invention, methods described also includes：
One or more upper strata semiconductor chip is placed in the top of the base semiconductor chip.
In the embodiment of the present invention, methods described also includes：
By the conductive welding disk, thermal land, base semiconductor chip, upper strata semiconductor chip and metal
Radiator is encapsulated in inside plastic-sealed body；
Polished in the upper surface of the plastic-sealed body, so that the plastic-sealed body upper surface and the heat dissipation metal
The upper surface of device is concordant, and the metal heat sink upper surface is exposed to the plastic-sealed body.
In the embodiment of the present invention, methods described also includes：
In the upper surface of the plastic-sealed body, heat dissipation metal lid, set heat dissipation metal lid and the metal are set
Radiator is in contact.
In the embodiment of the present invention, methods described also includes：
The base semiconductor chip and the conductive welding disk are electrically connected by the form of metal routing；
By the form of metal routing electrically connect the upper strata semiconductor chip and the base semiconductor chip with
And the conductive welding disk.
In the technical scheme of the embodiment of the present invention, the multi-chip framework encapsulation structure of radiating has good radiating
Characteristic, the encapsulating structure includes：At least one conductive welding disk, the conductive welding disk is used to provide chip pin
With the electrical connection path of packaging body external terminal；Thermal land；It is placed on above the thermal land extremely
Few two base semiconductor chips；It is arranged on the metal heat sink above the superiors' semiconductor chip, the gold
Category radiator is used to provide heat dissipation channel for the semiconductor chip of lower section.It can be seen that, it is many in the embodiment of the present invention
It is that the semiconductor chip of each the superiors adds a metal heat sink in chi frame encapsulating structure, it is described
Metal heat sink can be respectively provided with different radiators according to the size of different semiconductor chips and cooling requirements
Structure, can be greatly enhanced the flexibility of multi-chip framework encapsulation structure design.For heap poststack height not
Consistent chip is respectively provided with the metal heat sink of different height, so that overall structure is highly controllable.Most
Heat dissipation metal lid is added in the upper surface of metal heat sink afterwards, the encapsulating structure of the embodiment of the present invention can be effective
Ground increases the heat dissipation channel of each semiconductor chip, improves the heat-sinking capability of whole package system.
Brief description of the drawings
The circuit theory schematic diagram that Fig. 1 is formed by conductive welding disk in the embodiment of the present invention with thermal land；
Fig. 2 is the encapsulating structure schematic diagram after the multiple chips of placement on thermal land in the embodiment of the present invention；
Fig. 3 is addition radiator post package structural representation in the embodiment of the present invention；
Fig. 4 is the encapsulating structure schematic diagram one completed in the embodiment of the present invention；
Fig. 5 is encapsulating structure schematic diagram two in the embodiment of the present invention；
Fig. 6 is encapsulating structure schematic diagram three in the embodiment of the present invention；
Fig. 7 is encapsulating structure schematic diagram four in the embodiment of the present invention；
Fig. 8 illustrates for the flow of the preparation method of the multi-chip framework encapsulation structure of the radiating of the embodiment of the present invention
Figure.
Specific embodiment
The characteristics of in order to more fully hereinafter understand the embodiment of the present invention and technology contents, below in conjunction with the accompanying drawings
Realization to the embodiment of the present invention is described in detail, appended accompanying drawing purposes of discussion only for reference, is not used for
Limit the embodiment of the present invention.
It is not enough in order to solve existing SiP framework encapsulations structure heat-sinking capability, it is easily caused whole SiP frameworks envelope
The problem of thrashing is filled, a kind of multi-chip framework with good heat radiating characteristic is the embodiment of the invention provides
Encapsulating structure and preparation method thereof, the encapsulating structure can be effectively increased framework SIP package cooling passages,
Improve encapsulating structure thermal conductivity.
The multi-chip framework encapsulation structure of the radiating of the embodiment of the present invention, including：
At least one conductive welding disk, the conductive welding disk is used to provide chip pin with packaging body external terminal
Electrical connection path；Thermal land；It is placed at least two base semiconductor cores above the thermal land
Piece；The metal heat sink above the superiors' semiconductor chip is arranged on, the metal heat sink is used to be lower section
Semiconductor chip provide heat dissipation channel.
In one embodiment, the encapsulating structure also includes：It is placed on the base semiconductor chip
One or more upper strata semiconductor chip of top.Certainly, the encapsulating structure can not also include upper strata
Semiconductor chip, can be configured according to actual conditions to the number of upper strata semiconductor chip.
The conductive welding disk, thermal land, base semiconductor chip, upper strata semiconductor chip and metal dissipate
Hot device is located inside plastic-sealed body, and the plastic-sealed body upper surface is concordant with the upper surface of the metal heat sink, and
The metal heat sink upper surface is exposed to the plastic-sealed body.
There is heat dissipation metal lid positioned at the upper surface of the plastic-sealed body, the heat dissipation metal lid dissipates with the metal
Hot device is in contact.
In one embodiment, the base semiconductor chip can by the form of metal routing with it is described
Conductive welding disk is electrically connected, and the upper strata semiconductor chip can be by the form of metal routing and the bottom half
Conductor chip and the conductive welding disk are electrically connected.
The multi-chip framework encapsulation structure of the radiating of the embodiment of the present invention is carried out with reference to concrete application scene
Detailed explanation.
Reference picture 4, encapsulating structure includes：At least one conductive welding disk 101, the conductive welding disk 101 is used for
The electrical connection path of chip pin and packaging body external terminal is provided；
Thermal land 102, the thermal land 102 is made up of metal material；
At least two base semiconductor chips 103, the base semiconductor chip tiling is positioned over the heat conduction
The top of pad 102, in may be placed on one or more for the base semiconductor chip 103
Layer semiconductor chip 202, the base semiconductor chip 103 can by the form of metal routing with it is described
Conductive welding disk 101 is electrically connected, and the upper strata semiconductor chip can be by the form of metal routing and institute
State base semiconductor chip 103 and the conductive welding disk 101 is electrically connected；
Metal heat sink 109, the metal heat sink 109 be located at the upper strata semiconductor chip 202 and
The top of base semiconductor chip 103 of upper strata semiconductor chip is not placed, for being provided for chip below
Heat dissipation channel；
Plastic-sealed body 108, the conductive welding disk 101, thermal land 102, base semiconductor chip 103, on
Layer semiconductor chip 202 and metal heat sink 109 are all located inside the plastic-sealed body 108, the plastic packaging
The upper surface of body 108 is concordant with the upper surface of the metal heat sink 109, and on the metal heat sink 109
Surface exposure is in the plastic-sealed body 108；
Heat dissipation metal lid 110, the heat dissipation metal lid 110 be located at the plastic-sealed body 108 upper surface and with
The metal heat sink 109 is in contact.
In such scheme, the metal heat sink 109 is serrated metal radiator 109, certainly, metal
Radiator 109 can also be other shapes, and the shape of metal heat sink 109 can be according to concrete application situation
It is prepared.
The embodiment of the present invention additionally provides a kind of preparation method of the multi-chip framework encapsulation structure of radiating, such as schemes
Shown in 8, the preparation method of the multi-chip framework encapsulation structure of the radiating is comprised the following steps：
Step 801：Thermal land is set.
Step 802：At least one conductive welding disk, the conductive welding disk are set around the thermal land
Electrical connection path for providing chip pin and packaging body external terminal.
In the embodiment of the present invention, the lead frame of multi-chip package is prepared, the framework includes a heat conduction weldering
Disk, and the thermal land surrounding provides at a conductive welding disk.
In the embodiment of the present invention, thermal land and conductive welding disk material are alloy 42 (Alloy42), copper alloy
And the one kind in Kovar alloy (Fe-Ni-Co).
Step 803：At least two base semiconductor chips are placed in the top of the thermal land.
In the embodiment of the present invention, the base semiconductor chip at least two and tiling place.
In the embodiment of the present invention, one or more upper strata half is placed in the top of the base semiconductor chip
Conductor chip.
In the embodiment of the present invention, by the form of metal routing electrically connect the base semiconductor chip with it is described
Conductive welding disk；The upper strata semiconductor chip and the base semiconductor are electrically connected by the form of metal routing
Chip and the conductive welding disk.
Specifically, metal coupling is prepared in the base semiconductor chip upper surface.In the base semiconductor
Electrical interconnection line is prepared between the metal coupling of chip upper surface and the conductive welding disk.Partly led on the upper strata
Body chip upper surface prepares metal coupling.Between the metal coupling of the upper strata semiconductor chip upper surface,
The metal coupling of the upper strata semiconductor chip upper surface and the base semiconductor chip upper surface metal coupling
Between and the upper surface metal coupling and the conductive welding disk of the upper strata semiconductor chip between prepare it is electrical
Interconnection line.
In the embodiment of the present invention, the preparation method of electrical interconnection line is in supersonic bonding, thermocompression bonding
Plant routing bonding techniques.The material of electrical interconnection line can be the one kind in aluminium, gold, silver, copper, palladium.
In the embodiment of the present invention, the material of metal coupling is the one kind in gold, terne metal.
Step 804：Metal heat sink is set above the superiors' semiconductor chip, and the metal heat sink is used
Heat dissipation channel is provided in the semiconductor chip for lower section.
In the embodiment of the present invention, the material of metal heat sink is copper.
In the embodiment of the present invention, the heap poststack of chip is completed, in the upper surface system of the superiors' semiconductor chip
Standby metal heat sink, and plastic packaging is carried out to packaging body.The conductive welding disk, thermal land, bottom are partly led
Body chip, upper strata semiconductor chip and metal heat sink are encapsulated in inside plastic-sealed body.In the plastic-sealed body
Upper surface is polished, so that the plastic-sealed body upper surface is concordant with the upper surface of the metal heat sink, and
The metal heat sink upper surface is exposed to the plastic-sealed body.
In the embodiment of the present invention, the preparation method of plastic-sealed body is transfer formation technology, injection molding technology, pre-
One kind in forming technique.The material of plastic-sealed body is the one kind in phenolic resin, silica column.
In the embodiment of the present invention, heat dissipation metal lid, set metal are set in the upper surface of the plastic-sealed body
Dissipating cover is in contact with the metal heat sink.
In the embodiment of the present invention, the material of heat dissipation metal lid is the one kind in copper, gold, silver, aluminium.
With reference to concrete application scene to the system of the multi-chip framework encapsulation structure of the radiating of the embodiment of the present invention
Preparation Method carries out detailed explanation.
Reference picture 1, rises (Candence) SiP design software and completes a kind of with good scattered by using clang
The design of the multi-chip framework encapsulation structure of thermal characteristics, when preparing encapsulating structure, provides at least one and leads first
Electrical bonding pads 101, there is provided thermal land 102, the conductive welding disk 101 can be distributed in the thermal land
102 surroundings, the thermal land 102 is located at the center of the conductive welding disk 101.
Here, using alloy 42 (Alloy42) as the thermal land 102 and the conductive welding disk 101
Material, multi-chip framework is prepared by the method for rushing film.
Reference picture 2, in the upper surface of the thermal land 102 tiling place two base semiconductor chips 103,
201, the base semiconductor chip 103,201 is entered by conductive silver glue 104 with the thermal land 102
Row is bonded.
Metal coupling 105 is prepared in the upper surface of the base semiconductor chip 103 and 201, the metal is convex
The material of block 105 is gold.The upper surface of the base semiconductor chip 103 and 201 metal coupling 105 it
Between and the base semiconductor chip 103, the metal coupling 105 of 201 upper surfaces and the conductive welding disk
By thermocompression bonding technology between 101, the preparation of electrical interconnection line 106 is completed according to the form of metal routing.
The material of the metal interconnecting wires 106 is gold.
On the base semiconductor chip 201 continue place a upper strata semiconductor chip 202, it is described on
Layer semiconductor chip 202 is bonded in the upper of the base semiconductor chip 201 by chip adhesive film 107
Side.Metal coupling 105 is prepared in the upper surface of upper strata semiconductor chip 202, in the upper strata semiconductor
The metal coupling of the metal coupling 105 of the upper surface of chip 202 and the upper surface of base semiconductor chip 201
The metal coupling 105 and the conductive welding disk of between the 105 and upper surface of upper strata semiconductor chip 202
By thermocompression bonding technology between 101, the preparation of electrical interconnection line 106 is completed according to the form of metal routing.
The material of the metal interconnecting wires is gold.
Reference picture 3, semiconductor chip 202 and does not place the bottom of upper strata semiconductor chip and partly leads on upper strata
Serrated metal radiator 109 is set on body chip 103, and the serrated metal radiator 109 passes through core
Piece adhesive film 107 is bonded with chip, and single-chip and the stacked chips selection according to different height are not
Level radiator, so that after setting serrated metal radiator 109, whole height is consistent.
Total is moulded as the material of plastic packaging material 108 from silica column by transfer formation technology
Envelope, after the completion of plastic packaging, the conductive welding disk 101, thermal land 102, base semiconductor chip 103,
Upper strata semiconductor chip 202 and serrated metal radiator 109 are all located inside the plastic-sealed body 108.
Reference picture 4, the method etched by photochemistry is by the institute of the top of the serrated metal radiator 109
State plastic-sealed body 108 to remove so that the upper surface of the serrated metal radiator 109 is exposed among air.
Heat conductive silica gel 203 to upper surface and plastic-sealed body surface is coated with the upper surface of serrated metal radiator 109
Concordantly.
Heat dissipation metal lid 110 is prepared above whole frame structure, the heat dissipation metal lid 110 passes through heat conduction
Silica gel 203 is connected with the upper surface of the serrated metal radiator 109.
Reference picture 5, on the basis of the encapsulating structure shown in Fig. 3, directly polishing encapsulates the plastic packaging of upper surface
Material 108 so that the serrated metal radiator 109 inside encapsulation is exposed and, and directly adds dissipating cover 110.
Reference picture 6, on the basis of the encapsulating structure shown in Fig. 2, in the base semiconductor chip 103
Upper strata semiconductor chip is placed in top, then adds serrated metal radiator again on the semiconductor chip of upper strata
109.To adapt to more application scenarios.
Reference picture 7, on the basis of the encapsulating structure shown in Fig. 2, in the base semiconductor chip 103
Upper strata semiconductor chip is placed in top, then adds straight-line radiator 204 again on the semiconductor chip of upper strata.
To adapt to more application scenarios.
The technical scheme of the embodiment of the present invention, with very big advantage：
First, the semiconductor chip of lower floor can downwards be passed by thermal land conduction by hot in usual stacked package
It is delivered on PCB, and upper die is poor due to Natural Heat Convection effect, causes that surface temperature is higher to be difficult
Radiating.Multi-chip frame structure in the present invention adds radiator by the semiconductor chip for each the superiors
Method well solve due to stacked chips quantity increase, caused by heat transfer problem.
Secondly, it is every in the multi-chip framework encapsulation structure in the embodiment of the present invention compared with prior art
The semiconductor chip of the individual the superiors adds a radiator, and the radiator can be according to the size of different chips
Different heat spreader structures are respectively provided with cooling requirements, the radiating of multi-chip framework encapsulation can be greatly enhanced
The flexibility of structure design.And the chip highly inconsistent for heap poststack is respectively provided with dissipating for different height
Hot device, so that overall structure is highly controllable, it is also a spotlight of the invention.
Heat dissipation metal lid is added in the last upper surface in radiator, and the structure can effectively increase each chip
Heat dissipation channel, improve the heat-sinking capability of whole package system.
Between technical scheme described in the embodiment of the present invention, in the case where not conflicting, can be in any combination.
In several embodiments provided by the present invention, it should be understood that disclosed method and smart machine,
Can realize by another way.Apparatus embodiments described above are only schematical, for example,
The division of the unit, only a kind of division of logic function, can there is other division side when actually realizing
Formula, such as：Multiple units or component can be combined, or be desirably integrated into another system, or some features can
To ignore, or do not perform.In addition, the coupling or straight each other of shown or discussed each part
Connect coupling or communication connection can be the INDIRECT COUPLING or communication connection of equipment or unit by some interfaces,
Can be electrical, machinery or other forms.
It is above-mentioned as separating component illustrate unit can be or may not be it is physically separate, as
The part that unit shows can be or may not be physical location, you can positioned at a place, also may be used
To be distributed on multiple NEs；Part or all of unit therein can be according to the actual needs selected
Realize the purpose of this embodiment scheme.
In addition, each functional unit in various embodiments of the present invention can be fully integrated into a second processing list
In unit, or each unit is individually as a unit, it is also possible to two or more unit collection
Into in a unit；Above-mentioned integrated unit can both be realized in the form of hardware, it would however also be possible to employ hard
Part adds the form of SFU software functional unit to realize.
The above, specific embodiment only of the invention, but protection scope of the present invention is not limited to
This, any one skilled in the art the invention discloses technical scope in, can readily occur in
Change or replacement, should all be included within the scope of the present invention.
Claims (10)
1. the multi-chip framework encapsulation structure of a kind of radiating, it is characterised in that the encapsulating structure includes：
At least one conductive welding disk, the conductive welding disk is used to provide chip pin with packaging body external terminal
Electrical connection path；Thermal land；It is placed at least two base semiconductor cores above the thermal land
Piece；The metal heat sink above the superiors' semiconductor chip is arranged on, the metal heat sink is used to be lower section
Semiconductor chip provide heat dissipation channel.
2. multi-chip framework encapsulation structure according to claim 1, it is characterised in that the encapsulation knot
Structure also includes：
It is placed on one or more upper strata semiconductor chip of the top of the base semiconductor chip.
3. multi-chip framework encapsulation structure according to claim 2, it is characterised in that the encapsulation knot
Structure also includes：
Plastic-sealed body, the conductive welding disk, thermal land, base semiconductor chip, upper strata semiconductor chip with
And metal heat sink is located inside the plastic-sealed body, the plastic-sealed body upper surface is upper with the metal heat sink
Flush, and the metal heat sink upper surface is exposed to the plastic-sealed body.
4. multi-chip framework encapsulation structure according to claim 3, it is characterised in that the encapsulation knot
Structure also includes：
Heat dissipation metal lid, the heat dissipation metal lid be located at the plastic-sealed body upper surface and with the heat dissipation metal
Device is in contact.
5. multi-chip framework encapsulation structure according to claim 1, it is characterised in that
The base semiconductor chip is electrically connected by the form of metal routing with the conductive welding disk, it is described on
Form and the base semiconductor chip and conductive welding disk electricity that layer semiconductor chip passes through metal routing
Connection.
6. a kind of preparation method of the multi-chip framework encapsulation structure of radiating, it is characterised in that methods described bag
Include：
Thermal land is set；
At least one conductive welding disk is set around the thermal land, and the conductive welding disk is used to provide core
The electrical connection path of piece pin and packaging body external terminal；
At least two base semiconductor chips are placed in the top of the thermal land；
Metal heat sink is set above the superiors' semiconductor chip, and the metal heat sink is used to be lower section
Semiconductor chip provides heat dissipation channel.
7. the preparation method of the multi-chip framework encapsulation structure of radiating according to claim 6, its feature
It is that methods described also includes：
One or more upper strata semiconductor chip is placed in the top of the base semiconductor chip.
8. the preparation method of the multi-chip framework encapsulation structure of radiating according to claim 7, its feature
It is that methods described also includes：
By the conductive welding disk, thermal land, base semiconductor chip, upper strata semiconductor chip and metal
Radiator is encapsulated in inside plastic-sealed body；
Polished in the upper surface of the plastic-sealed body, so that the plastic-sealed body upper surface and the heat dissipation metal
The upper surface of device is concordant, and the metal heat sink upper surface is exposed to the plastic-sealed body.
9. the preparation method of the multi-chip framework encapsulation structure of radiating according to claim 8, its feature
It is that methods described also includes：
In the upper surface of the plastic-sealed body, heat dissipation metal lid, set heat dissipation metal lid and the metal are set
Radiator is in contact.
10. the preparation method of the multi-chip framework encapsulation structure of radiating according to claim 6, it is special
Levy and be, methods described also includes：
The base semiconductor chip and the conductive welding disk are electrically connected by the form of metal routing；
By the form of metal routing electrically connect the upper strata semiconductor chip and the base semiconductor chip with
And the conductive welding disk.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510961240.2A CN106898591A (en) | 2015-12-21 | 2015-12-21 | A kind of multi-chip framework encapsulation structure of radiating and preparation method thereof |
| PCT/CN2016/097607 WO2017107548A1 (en) | 2015-12-21 | 2016-08-31 | Heat dissipating multi-chip frame package structure and preparation method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510961240.2A CN106898591A (en) | 2015-12-21 | 2015-12-21 | A kind of multi-chip framework encapsulation structure of radiating and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106898591A true CN106898591A (en) | 2017-06-27 |
Family
ID=59089009
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510961240.2A Pending CN106898591A (en) | 2015-12-21 | 2015-12-21 | A kind of multi-chip framework encapsulation structure of radiating and preparation method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN106898591A (en) |
| WO (1) | WO2017107548A1 (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111370378A (en) * | 2020-03-17 | 2020-07-03 | 电子科技大学 | Chip radiator |
| CN112151469A (en) * | 2020-09-21 | 2020-12-29 | 青岛歌尔微电子研究院有限公司 | Heat dissipation packaging structure, preparation method thereof and electronic device |
| CN114023660A (en) * | 2021-11-03 | 2022-02-08 | 长江存储科技有限责任公司 | Chip packaging structure and preparation method thereof |
| CN114843194A (en) * | 2022-05-05 | 2022-08-02 | 盐城芯丰微电子有限公司 | High-precision etching packaging method capable of meeting requirements of large-scale integrated circuit |
| CN114937633A (en) * | 2022-07-25 | 2022-08-23 | 成都万应微电子有限公司 | Radio frequency chip system-in-package method and radio frequency chip system-in-package structure |
| CN116053239A (en) * | 2023-04-03 | 2023-05-02 | 中科华艺(天津)科技有限公司 | Packaging structure of multi-chip assembly |
| CN117423668A (en) * | 2023-10-24 | 2024-01-19 | 重庆平伟实业股份有限公司 | Double-sided heat dissipation structure of DrMOS and manufacturing method thereof |
| CN118231267A (en) * | 2024-03-23 | 2024-06-21 | 江苏晟驰微电子有限公司 | DFN (distributed feedback network) quick packaging technology applicable to power GPP (general purpose packet radio service) chip |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102019122382B3 (en) * | 2019-08-20 | 2020-09-10 | Infineon Technologies Ag | POWER SEMI-CONDUCTOR ENCLOSURE AND METHOD FOR MANUFACTURING A POWER SEMICONDUCTOR ENCLOSURE |
| CN116235298A (en) * | 2020-09-25 | 2023-06-06 | 华为技术有限公司 | Chip packaging structure, preparation method of chip packaging structure and equipment interconnection system |
| CN113035794B (en) * | 2021-02-01 | 2023-04-07 | 珠海越亚半导体股份有限公司 | Chip packaging structure manufacturing method and chip packaging structure |
| CN117393517A (en) * | 2023-12-08 | 2024-01-12 | 成都智多晶科技有限公司 | Wire bonding type packaging structure and substrate capable of effectively enhancing heat dissipation efficiency |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5525835A (en) * | 1991-08-08 | 1996-06-11 | Sumitomo Electric Industries, Ltd. | Semiconductor chip module having an electrically insulative thermally conductive thermal dissipator directly in contact with the semiconductor element |
| CN1957468A (en) * | 2004-06-25 | 2007-05-02 | 英特尔公司 | Bottom heat spreader |
| CN102074521A (en) * | 2010-01-30 | 2011-05-25 | 江苏长电科技股份有限公司 | Package structure of printed circuit board, flip-chip, radiating block and external radiator |
| CN104681525A (en) * | 2013-11-27 | 2015-06-03 | 万国半导体股份有限公司 | Multi-chip laminating type packaging structure and packaging method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102760724B (en) * | 2011-04-29 | 2015-02-11 | 万国半导体股份有限公司 | Integrally-packaged power semiconductor device |
| CN204257629U (en) * | 2014-07-02 | 2015-04-08 | 矽力杰半导体技术(杭州)有限公司 | For the multichip packaging structure of power inverter |
-
2015
- 2015-12-21 CN CN201510961240.2A patent/CN106898591A/en active Pending
-
2016
- 2016-08-31 WO PCT/CN2016/097607 patent/WO2017107548A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5525835A (en) * | 1991-08-08 | 1996-06-11 | Sumitomo Electric Industries, Ltd. | Semiconductor chip module having an electrically insulative thermally conductive thermal dissipator directly in contact with the semiconductor element |
| CN1957468A (en) * | 2004-06-25 | 2007-05-02 | 英特尔公司 | Bottom heat spreader |
| CN102074521A (en) * | 2010-01-30 | 2011-05-25 | 江苏长电科技股份有限公司 | Package structure of printed circuit board, flip-chip, radiating block and external radiator |
| CN104681525A (en) * | 2013-11-27 | 2015-06-03 | 万国半导体股份有限公司 | Multi-chip laminating type packaging structure and packaging method thereof |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111370378A (en) * | 2020-03-17 | 2020-07-03 | 电子科技大学 | Chip radiator |
| CN111370378B (en) * | 2020-03-17 | 2022-08-05 | 电子科技大学 | Chip radiator |
| CN112151469A (en) * | 2020-09-21 | 2020-12-29 | 青岛歌尔微电子研究院有限公司 | Heat dissipation packaging structure, preparation method thereof and electronic device |
| CN114023660A (en) * | 2021-11-03 | 2022-02-08 | 长江存储科技有限责任公司 | Chip packaging structure and preparation method thereof |
| CN114843194A (en) * | 2022-05-05 | 2022-08-02 | 盐城芯丰微电子有限公司 | High-precision etching packaging method capable of meeting requirements of large-scale integrated circuit |
| CN114937633A (en) * | 2022-07-25 | 2022-08-23 | 成都万应微电子有限公司 | Radio frequency chip system-in-package method and radio frequency chip system-in-package structure |
| CN116053239A (en) * | 2023-04-03 | 2023-05-02 | 中科华艺(天津)科技有限公司 | Packaging structure of multi-chip assembly |
| CN117423668A (en) * | 2023-10-24 | 2024-01-19 | 重庆平伟实业股份有限公司 | Double-sided heat dissipation structure of DrMOS and manufacturing method thereof |
| CN118231267A (en) * | 2024-03-23 | 2024-06-21 | 江苏晟驰微电子有限公司 | DFN (distributed feedback network) quick packaging technology applicable to power GPP (general purpose packet radio service) chip |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2017107548A1 (en) | 2017-06-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106898591A (en) | A kind of multi-chip framework encapsulation structure of radiating and preparation method thereof | |
| CN215220710U (en) | Semiconductor device with a plurality of semiconductor chips | |
| US6818980B1 (en) | Stacked semiconductor package and method of manufacturing the same | |
| TWI482261B (en) | Three-dimensional system-in-package package-on-package structure | |
| US7372151B1 (en) | Ball grid array package and process for manufacturing same | |
| US6781242B1 (en) | Thin ball grid array package | |
| CN101165866B (en) | Integrated circuit package and method of making same | |
| CN102891123B (en) | Stacked die semiconductor package body | |
| US20110244633A1 (en) | Package assembly for semiconductor devices | |
| US20130069218A1 (en) | High density package interconnect with copper heat spreader and method of making the same | |
| US7221055B2 (en) | System and method for die attach using a backside heat spreader | |
| CN102169863B (en) | Window ball grid array semiconductor packages | |
| CN104681525B (en) | A kind of encapsulating structure and its method for packing of multi-chip lamination | |
| CN110021591A (en) | Semiconductor packages | |
| US8368192B1 (en) | Multi-chip memory package with a small substrate | |
| US20140183711A1 (en) | Semiconductor Device and Method of Making a Semiconductor Device | |
| US6627990B1 (en) | Thermally enhanced stacked die package | |
| CN215377395U (en) | Packaging structure for semiconductor chip | |
| US7573141B2 (en) | Semiconductor package with a chip on a support plate | |
| CN108417499A (en) | Cavity package structure and its manufacturing method | |
| KR101685068B1 (en) | System in package and method for manufacturing the same | |
| CN201655787U (en) | Semiconductor encapsulation structure | |
| US9484320B2 (en) | Vertically packaged integrated circuit | |
| JP2015046626A (en) | Multi-die building block for stacked die package | |
| CN104701292A (en) | Method for collaboratively and optimally designing high-speed IC-QFN (integrated circuit-quad flat no-lead) packages |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170627 |