CN104701292A - Method for collaboratively and optimally designing high-speed IC-QFN (integrated circuit-quad flat no-lead) packages - Google Patents
Method for collaboratively and optimally designing high-speed IC-QFN (integrated circuit-quad flat no-lead) packages Download PDFInfo
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- CN104701292A CN104701292A CN201310650409.3A CN201310650409A CN104701292A CN 104701292 A CN104701292 A CN 104701292A CN 201310650409 A CN201310650409 A CN 201310650409A CN 104701292 A CN104701292 A CN 104701292A
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- chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
Abstract
The invention discloses a method for collaboratively and optimally designing high-speed IC-QFN (integrated circuit-quad flat no-lead) packages. The method has the advantages that each package structure designed by the aid of the method comprises a high-speed IC chip and relevant control chips, each high-speed IC chip is connected with the corresponding relevant control chips by through-silicon-vias (TSV), and accordingly parasitic effects of leads of RF (radiofrequency) chips can be reduced by the aid of three-dimensional package technologies; bonding pads with exposed centers are packaged for the QFN packages, so that residual heat can be effectively absorbed, and heat stress on bottom chips of three-dimensional packages can be effectively improved; three-dimensional subpackages are mainly applied to ball grid array packages under the consideration of the quantities of pins of the chips, and the performance of high-speed ICs can be greatly optimized if the QFN packages can be used in the three-dimensional packages with few pins owing to the low QFN cost and mature QFN package processes; heat stress generated in package procedures increasingly becomes an important factor which can affect the performance of the chips for the three-dimensional packages with high integration levels, the method for collaboratively and optimally designing the QFN packages is based on generation of the heat stress on chip packages and analysis on parasitism of the high-speed ICs, and the QFN packages are optimized from the aspects of reducing the parasitism and reducing the heat stress.
Description
Technical field
Integrated antenna package field of the present invention, the optimization particularly relating to High Speed ICs relates to method.
Background technology
In semiconductor packaging process, quad flat non-pin package (Quad Flat No-lead Package, QFN) have many good qualities, such as good heat dissipation characteristics, the cost of encapsulation is lower, Technical comparing is ripe, can provide remarkable electrical property etc., and this makes QFN encapsulation can be applied in RF circuit.But due to the technology of three-dimension packaging and cost, and the restriction of QFN pin, make three-dimensional packaging technology be mainly used in the packing forms of BGA, a lot of complicated chip still cannot adopt QFN to encapsulate when needs carry out three-dimension packaging.The present invention is when low pin number, chip is adopted to the three-dimension packaging of QFN, reduces the parasitism that chip interconnect is brought greatly.
Along with the raising of integrated level, the thermal stress of chip package inside more and more has influence on the reliability of chip.The present invention was studying chip package flow process and proposed a kind of new structure to the simulation of thermal stress in chip package and improved on the basis of untouched dress flow process.The method for packing improved makes optimization in reduction thermal stress, therefore can obtain better reliability.
In High Speed ICs encapsulation, the parasitism brought that goes between is the importance affecting IC operating rate all the time, and any effort reducing wiring parasitic is made all can receive good effect.
Traditional QFN packaging technology flow process is: a. wafer reverse side grinding b. wafer is installed c. wafer cutting d. wafer cleaning e. second light inspection f. point silver slurry g. die bonding h. silver slurry solidification i. wire bonds j. the 3rd road light inspection k. injection moulding l. laser typewriting m. hot setting n. and gone flash o. to electroplate the light inspection of annealing p. Trim Molding q. the 4th road.Can be used for reducing thermal stress for the plating annealing in step o, however due to hot setting different with the plating environment of annealing, hot setting will inevitably introducing portion physical stress cannot be eliminated.
Summary of the invention
Given this, the present invention realizes the cooperate optimization that High Speed ICs-QFN encapsulates from three aspects, a) reduce the wiring parasitic of High Speed ICs, b) propose a kind of new chip structure, c) to original QFN process modification.Realize reducing the parasitic time delay of chip and the thermal stress of chip internal by above 3.
QFN three-dimension packaging provided by the invention comprises a High Speed ICs chip, a relevant control chip QFN shell and QFN wiring.
In reduction is parasitic, for reducing the parasitism that bring of signal to ground, needs the signal being connected to ground to be directly connected on QFN bottom heat radiation plate, can well high frequency characteristics be improved.
For solving the problem, the present invention adopts chip thinning technology by substrate attenuation to 75um, has both decreased the requirement to equipment, and has turn increased the rate of finished products of chip thinning.
Through-hole diameter adopts 50um, and this diameter can adopt the technology of laser undercutting to realize, and speed is fast, and precision is general, eliminates the steps such as photoresist is coated with, exposes, develops and removes photoresist, and is easier to realize.
Reduce an encapsulating structure for thermal stress, bottom chip is thicker compared with top layer chip, effectively alleviates the maximum thermal stress that bottom chip is subject to.
Reduce an encapsulating structure for thermal stress, chip chamber adhesive film equals the thickness of two chip chamber scolding tin, should be as far as possible thin.
Reduce an encapsulating structure for thermal stress, bottom chip periphery does not adopt square, but adopts cylindrical structural.
Reduce an encapsulating structure for thermal stress, the Thickness Ratio of QFN radiating bottom plate thickness and bottom chip is 1:1
The QFN packaging technology flow process improved, before hot setting, paste the physical stress produced to chip dress discharge further, its concrete steps are: a. wafer reverse side grinding b. wafer is installed c. wafer cutting d. wafer cleaning e. second light inspection f. point silver slurry g. die bonding h. silver slurry solidification i. j. wire bonds k. the 3rd road light inspection l. injection moulding m. laser typewriting n. hot setting o. that anneals and gone flash p. to electroplate annealing q. Trim Molding r. the 4th road light to examine.
Accompanying drawing explanation
Attached Figure 1 shows that QFN encapsulate top view;
The attached concrete structure that Figure 2 shows that TSV;
Attachedly Figure 3 shows that the sectional view (current process chip structure) of two chips along the tangent plane of accompanying drawing 1;
The attached three-dimensional stacking structure that Figure 4 shows that improvement;
Attachedly Figure 5 shows that two chip-stacked top views.
Embodiment
Below in conjunction with accompanying drawing, High Speed ICs-QFN encapsulation of the present invention is described in further detail.
First the embodiment that QFN of the present invention encapsulates is introduced.QFN has outstanding high frequency characteristics, if can continue to keep QFN price advantage, the three-dimension packaging of QFN will obtain larger range of application.
Be illustrated in figure 1 the schematic diagram of the top view of QFN three-dimension packaging, 10 and 20 are respectively High Speed ICs chip and control chip, and the two realizes connecting by TSV technology.The salient point of three-dimension packaging with adopt QFN to connect up between QFN pad to be connected, compared with traditional bonding wire gold thread, less parasitism can be introduced, and reduce costs.
To High Speed ICs, any effort being reduced to path, ground all can optimize high frequency performance, and the superincumbent RF chip in the novel middle position of the innovation directly arrives QFN heating panel to the signal on ground by 22, and heating panel is ground connection.The path of other signals is chip-->TSV-->QFN wiring-->QFN PAD, shortens the length of RF chip signal to the lead-in wire on ground, optimizes the high frequency performance of RF chip.
The thickness of normal wafer is 300 ~ 400um, the chip thickness that current stacked package uses is at below 100um, the present invention adopts the wafer being thinned to 75um, reduce the problems such as warpage, surface damage and wafer breakage to a certain extent, improve the rate of finished products of wafer, also improve the performance of RF chip simultaneously.
The depth-to-width ratio of usual through hole is generally between 1:1 to 10:1, there is certain relation to through-hole diameter and equivalent stress, when depth-to-width ratio is less than 6, equivalent stress becomes increase tendency, when being greater than 6, tend to be steady, still follow the rule that the less stress of diameter is larger generally.This use novel employing depth-to-width ratio be 2 through hole technology, to reduce equivalent stress.
To the packing material of TSV, generally selectable have, copper and tungsten.The thermal coefficient of expansion of electro-coppering is 18.5ppm/ DEG C, tungsten be 4.4ppm/ DEG C, the thermal coefficient of expansion of silicon dioxide is 0.5ppm/ DEG C.Thus can find out, when silicon dioxide is the isolated material of through hole, when the packing material in corresponding through hole is tungsten, corresponding equivalent stress can be smaller.Therefore, the TSV packing material of the novel employing of the innovation is tungsten.
What bonding between two through hole adopted is tin is as welding material, and not only in technique, technology maturation is easy to realize, and thermal stress aspect is also more satisfactory.
The thermal-stress analysis of three-dimension packaging is shown that the diameter of reduction two chip bonding point place pad and the thickness of suitable increase pad can effectively reduce the stress of this position, thus reduces the heat stress value of whole model.
Accompanying drawing 2 contains separator, filling through hole material, as discussed above, separator use material be SiO2, minimum stress condition lower through-hole be filled to tungsten.Consider the electric conductivity of copper and tungsten, also can substitute with copper, corresponding isolated material will change ABF separator into.
As mentioned above, TSV through hole diameter is 50um, and depth-to-width ratio is 2, through-hole diameter is when below 10um, and laser ablation can face technical barrier, when through-hole diameter is 50um, the fire damage that laser ablation brings is in allowed band, and technique is simple, reduces technical costs.
The filler of chip and QFN heating panel is for fill glue, and increase the contact area between chip and heating panel, the bond strength of both raisings, plays a protective role to salient point.The thickness of filling glue should be as far as possible little according to the consideration thickness of less thermal stress, and underfill thickness is slightly thicker than the thickness of QFN wiring in this configuration.
During three-dimensional chip is stacking, the stress that bottom chip is born is maximum, and bottom chip thickness adopts and is thinned to 100um chip.The bending resistance of thick chip is better, and the chip that its thermal stress extreme value, peak stress difference is also thinner is low, more easily meets thermal stress requirement compared to thin chip.
Analyze can draw the ANSYS of chip thermal stress, to bottom chip, peel stress obtains maximum at chip edge place, and shear stress is also comparatively large at adjacent edges, and adopting the present invention that bottom chip surrounding is increased semi-cylindrical in configuration can; Effectively reduce the sudden change that chip rectangular structure is brought, thus effectively reduce the thermal stress at chip edge place.
In accompanying drawing 5, top layer chip is High Speed ICs, and bottom chip is control chip, and composition graphs 4 bottom chip designs for reducing thermal stress compared with the additional part of top layer chip.
Analyze the ANSYS of chip thermal stress and draw, QFN bottom heat radiation plate thickness is larger with bottom chip Thickness Ratio, and the maximum of equivalent heat stress is larger, and the Thickness Ratio of the present invention's employing is 1:1.
The above is specific implementation of the present invention, does not limit protection scope of the present invention, within the spirit and principles in the present invention all, and any amendment made, equivalent replacement and improvement etc. all should be included in protection scope of the present invention.
Claims (10)
1. a High Speed ICs-QFN encapsulates; it is characterized in that: adopt three-dimension packaging technique; comprise the encapsulation of two and two or more chip; the total number of pins of chip can use when not too high; connection between stacked chips adopts silicon via process; chip is directly connected to central heat sink pad to the connection on ground by silicon via process, and in QFN encapsulation, central pad is directly connected to the ground and connects; In reduction thermal stress, the present invention adopts the encapsulation flow process of improvement and the encapsulating structure of improvement to reduce the impact of thermal stress on chip reliability.
2. High Speed ICs-QFN as claimed in claim 1 encapsulates, and it is characterized in that adopting QFN wiring to replace traditional bonding wire.
3. High Speed ICs-QFN as claimed in claim 1 encapsulate, it is characterized in that the port that RF chip needs are connected to ground passes high-power chip by TSV through hole line, is connected to ground by bottom heat radiation plate.
4. three-dimensional TSV technology as claimed in claim 1, is characterized in that adopting laser ablation.
5. the material that the connection between chip as claimed in claim 1 and wiring uses is tin.
6. three-dimensional TSV technology as claimed in claim 1, is characterized in that lower layer chip is thinned to 100um, and through-hole diameter is 50um.
7. the novel encapsulated flow process adopted as claimed in claim 1, is characterized in that the technique increasing by a step flow process annealing before traditional injection moulding solidification.
8. the encapsulating structure improved as claimed in claim 1, is characterized in that orlop chip periphery increases the structure of annular.
9. the encapsulating structure improved as claimed in claim 1, is characterized in that the Thickness Ratio of bottom heating panel and bottom chip is 1:1.
10. High Speed ICs-QFN as claimed in claim 1 encapsulates, and it is characterized in that lower layer chip is thinned to 100um, through-hole diameter is 50um.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310650409.3A CN104701292A (en) | 2013-12-06 | 2013-12-06 | Method for collaboratively and optimally designing high-speed IC-QFN (integrated circuit-quad flat no-lead) packages |
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| CN201310650409.3A CN104701292A (en) | 2013-12-06 | 2013-12-06 | Method for collaboratively and optimally designing high-speed IC-QFN (integrated circuit-quad flat no-lead) packages |
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| CN104701292A true CN104701292A (en) | 2015-06-10 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108090250A (en) * | 2017-11-24 | 2018-05-29 | 温州大学 | A kind of method and system for assessing integrated antenna package thermal damage |
| CN108614941A (en) * | 2018-05-08 | 2018-10-02 | 湖南城市学院 | A kind of Board level packaging design optimization method for integrated QFN chips |
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| US6392292B1 (en) * | 1999-07-08 | 2002-05-21 | Nec Corporation | Multi-level stacked semiconductor bear chips with the same electrode pad patterns |
| CN101038908A (en) * | 2006-03-17 | 2007-09-19 | 海力士半导体有限公司 | Stack package utilizing through vias and re-distribution lines |
| CN101587875A (en) * | 2008-05-21 | 2009-11-25 | 财团法人工业技术研究院 | Vertically electrically connected three-dimensional stacked chip packaging structure and manufacturing method thereof |
| CN101937907A (en) * | 2009-06-29 | 2011-01-05 | 财团法人工业技术研究院 | Chip stacking package structure and manufacture method thereof |
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2013
- 2013-12-06 CN CN201310650409.3A patent/CN104701292A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6392292B1 (en) * | 1999-07-08 | 2002-05-21 | Nec Corporation | Multi-level stacked semiconductor bear chips with the same electrode pad patterns |
| CN101038908A (en) * | 2006-03-17 | 2007-09-19 | 海力士半导体有限公司 | Stack package utilizing through vias and re-distribution lines |
| CN101587875A (en) * | 2008-05-21 | 2009-11-25 | 财团法人工业技术研究院 | Vertically electrically connected three-dimensional stacked chip packaging structure and manufacturing method thereof |
| CN101937907A (en) * | 2009-06-29 | 2011-01-05 | 财团法人工业技术研究院 | Chip stacking package structure and manufacture method thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108090250A (en) * | 2017-11-24 | 2018-05-29 | 温州大学 | A kind of method and system for assessing integrated antenna package thermal damage |
| CN108090250B (en) * | 2017-11-24 | 2021-04-27 | 温州大学 | Method and system for evaluating heat damage of integrated circuit package |
| CN108614941A (en) * | 2018-05-08 | 2018-10-02 | 湖南城市学院 | A kind of Board level packaging design optimization method for integrated QFN chips |
| CN108614941B (en) * | 2018-05-08 | 2022-04-12 | 湖南城市学院 | Board-level packaging design optimization method for integrated QFN chip |
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