CN108614941B - Board-level packaging design optimization method for integrated QFN chip - Google Patents
Board-level packaging design optimization method for integrated QFN chip Download PDFInfo
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- G06F30/39—Circuit design at the physical level
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Abstract
The invention discloses a board level packaging design optimization method for an integrated QFN chip, which comprises the following steps: determining parameters of the integrated circuit board and establishing a thermal coupling simulation model; constructing a performance function of the thermal stress of the bonding pad and the warping of the wafer; constructing a limiting state equation of thermal stress of the bonding pad and warping of the wafer; constructing an approximate limit state equation of the thermal stress of the bonding pad and the warping of the wafer; checking the strength of the bonding pad and the warping of the wafer; and finishing and outputting the board-level packaging optimal design and the fixed point optimal error tolerance. According to the invention, the thermal coupling simulation model is constructed for the board level package of the integrated QFN chip, and the extreme state equation is established by adopting the interval analysis technology, so that the obtained optimal design scheme of the board level package can meet the design requirements of thermal stress and warpage, and has the lowest processing cost and process difficulty. In addition, the method provided by the invention has good comprehensive performance in the aspects of efficiency and convergence.
Description
Technical Field
The invention belongs to the field of integrated circuit package design, and particularly relates to a board level package design optimization method for an integrated QFN chip.
Background
The package not only provides the necessary electrical connections for the integrated circuit to external systems, but also provides mechanical or environmental protection to the integrated circuit. With the rapid development of microelectronic technology, high-level package design has become a challenging task. The package can be generally defined into 4 levels: wafer level, chip level, board level, and system level. Board level packaging refers to the process of mounting chips and passive devices together on a printed circuit board to form an integrated circuit board with specific functions. The board level package needs to provide a stable and reliable working environment for the integrated chip; therefore, the package characteristics of the chip itself have a crucial impact on board level package design. QFN, a leadless chip package (also called LCC), provides excellent electrical performance due to its low self-inductance and resistance due to the short conductive path between the leads and the pads. At present, QFN chips are widely used in mobile phones, flat panels and other portable small electronic devices.
Due to the different thermal expansion coefficients of the substrate of the integrated circuit board and the packaging material of the integrated device, local thermal stress and warpage are generated under the comprehensive action of self-heating of the chip and environmental temperature change, so that serious failures such as packaging cracks, electrical property distortion and the like can be caused. This problem is particularly acute when the QFN chip is integrated in a board level package. In most cases, the QFN chip is the core device of an electronic system, and its electrical performance can directly determine the overall performance of the system. Moreover, the QFN chip structure is very precise, and even local micron-scale warpage may cause large deviation of electrical properties. The traditional board level packaging design mainly depends on engineering experience, and due to the lack of necessary theoretical basis, the optimal design is difficult to realize; in the face of such complex problems (such as the warpage tolerance of the QFN chip is only micron level), the traditional method is often difficult to meet the design requirement. The more advanced design method organically combines a numerical simulation technology and an optimization theory, and realizes the optimized design of the board-level package by constructing an optimization model based on the numerical simulation. The research of the method is still in the preliminary stage, and a series of technical difficulties still exist and need to be solved urgently. Firstly, the effective optimization model is constructed by considering the electrical property, the thermal property and the mechanical property of the integrated circuit board comprehensively, and considering the manufacturing cost and the process difficulty, which is very challenging for the ordinary technical personnel. Secondly, an objective function or constraint in the optimization model is based on a time-consuming simulation model, design optimization and constraint analysis are nested with each other, and the solution of the optimization model containing numerical simulation may face serious efficiency problems and convergence barriers. Therefore, an effective board-level packaging design optimization method is provided for an integrated circuit board integrated with a high-performance QFN chip, and the method has very important engineering significance for realizing the packaging design of electronic equipment with high cost performance and high reliability.
Disclosure of Invention
The invention aims to provide a board-level packaging design optimization method for an integrated QFN chip. The invention is realized by the following technical scheme.
A board level packaging design optimization method for an integrated QFN chip comprises the following steps.
1) Determining parameters of the integrated circuit board and establishing a thermal coupling simulation model;
2) constructing a performance function of the thermal stress of the bonding pad and the warping of the wafer;
3) constructing a limiting state equation of thermal stress of the bonding pad and warping of the wafer;
4) constructing an approximate limit state equation of the thermal stress of the bonding pad and the warping of the wafer;
5) checking the strength of the bonding pad and the warping of the wafer;
6) and finishing and outputting the board-level packaging optimal design and the fixed point optimal error tolerance.
Further, the parameters of the integrated circuit board in the step 1) include: the structure size, the plane coordinate, the elastic modulus, the Poisson ratio, the thermal expansion coefficient and the working heat consumption of the substrate and each device, the plane coordinate of a fixed point and the working temperature interval of the integrated circuit board; the thermal coupling simulation model in the step 1) refers to: and establishing a thermal coupling simulation model of the integrated circuit board according to the determined parameters of the integrated circuit board.
Further, the performance function of the thermal stress of the bonding pad and the wafer warpage in the step 2) refers to: respectively constructing a pad thermal stress performance function by taking a fixed point normal coordinate as an independent variable and taking the peak thermal stress of a pad of the QFN chip and the warpage of a wafer inside the QFN chip as dependent variablesσ(X) And wafer warp performance functionδ(X)；σRepresenting the peak thermal stress of the bonding pad;δindicating wafer warpage, i.e., the normal deviation between the corner points and the center of the wafer;Xrepresenting a fixed point normal coordinate vector, writable toX =(X 1, X 2,…,X i ,…,X n )。
Further, the extreme state equation of the thermal stress of the bonding pad and the wafer warpage in the step 3) refers to: considering the existence of fixed point processing errors, respectively constructing a maximum state equation max of the peak thermal stress of the QFN chip bonding padσ(X)| e } -[σ]Great face of =0 and QFN chip internal wafer warpage limit state equation maxδ(X)| e } -[δ]= 0; max represents the peak calculation, maxσ(X)| eDenotes the peak value of thermal stress of the pad at the time of a fixed point error, maxδ(X)|eDenotes the wafer warp peak in the presence of fixed point error; [σ]Indicating allowable stress of the pad material; [δ]Indicating an allowable warpage of the wafer;eindicating a fixed point error margin for a certain pointX i Due to the existence ofe，X i No longer a certain value but belongs to an interval; the upper and lower bounds of this interval are:X i C - eandX i C + e，X i C is the midpoint of the interval.
Further, the approximate limit state equation of the thermal stress of the pad in the step 4) refers to: the extreme state equation of the thermal stress of the bonding pad isXOf (2) a midpoint vectorX C Establishing a linear approximation, and establishing an approximate limit state equation of the thermal stress of the bonding pad:
L σ (X) =σ(X C ) + e ∑ n i=1|∂σ(X C )/∂X i | -[σ] = 0
solving the above equation can obtain an optimal package design based on pad thermal stress: (X σ , e σ )。
Further, the approximate limit state equation of the wafer warpage in the step 4) refers to: the extreme equation of state for wafer warpage isXOf (2) a midpoint vectorX C Establishing a linear approximation, and constructing an approximate limit state equation of the wafer warping:
L δ (X) = δ(X C ) + e ∑ n i=1|∂δ(X C )/∂X i | -[δ] = 0
solving the above equation yields an optimal package design based on wafer warpage: (X δ , e δ )。
Further, checking the strength of the bonding pad in the step 5) includes: will (a) toX σ , e σ ) Substituted into the left side of the approximate limit equation of state of wafer warpage, if the obtained value is less than or equal to 0X σ , e σ ) Is a feasible solution, otherwise is an invalid solution; the step 5) of checking the wafer warpage is as follows: will (a) toX δ , e δ ) Substituted into the left side of the pad thermal stress approximate limit state equation, and the obtained value is (if the obtained value is less than or equal to 0X δ , e δ ) Is a feasible solution, otherwise is an invalid solution;
further, the board level package optimal design and the fixed point optimal error tolerance in step 6) refer to: the steps areThe feasible solution obtained in step 5) can be written as (X *, e * )；X *Indicating an optimal design of the board level package,e *representing a fixed point optimum error margin.
Compared with the prior art, the invention has the following characteristics:
1) by constructing a limit state equation, the local thermal stress of the QFN chip and the wafer warpage when processing errors exist are considered, and the obtained packaging design scheme has good engineering practicability.
2) By maximizing the error tolerance, the obtained board-level packaging design scheme can not only meet the design requirements of thermal stress and warpage, but also has the lowest processing cost and process difficulty;
3) solving the extreme state equation faces double-layer nested optimization, the outer layer is to optimize the design variable, and the inner layer is to analyze the error interval; by establishing linear approximation for the extreme state equation, the nested optimization process in the solving process is avoided, and the calculation efficiency is greatly improved;
4) the nested solution of design optimization and constraint analysis in a conventional optimization model is avoided, the design optimization and each constraint analysis are converted into a sequence solution process, and the efficiency and the convergence are further improved.
Drawings
FIG. 1 is a flow chart of the present invention for optimizing the design of a board level package of an integrated QFN chip;
FIG. 2 is a diagram of an integrated circuit board package;
FIG. 3 is a diagram of a thermal coupling simulation model of an integrated circuit board;
FIG. 4 is a thermal stress diagram of a QFN chip under an optimal design of board level packaging;
fig. 5 is a warp diagram of a QFN chip under an optimal design of board level package.
Detailed Description
The invention is further explained below with reference to the drawings and the embodiments.
Referring to fig. 1, the invention relates to a board level package design optimization method for an integrated QFN chip, which comprises the following steps.
1) Step one, determining parameters of an integrated circuit board and establishing a thermal coupling simulation model
Referring to fig. 2, determining parameters of the integrated circuit board according to the existing information includes: the structure size, the plane coordinate, the elastic modulus, the Poisson ratio, the thermal expansion coefficient and the working heat consumption of the substrate 01, each part 02-06 of the QFN chip and the devices 07-10, the plane coordinate of a fixed point 11-12 and the working temperature range of the integrated circuit board are [ -20 ℃ and 60 ℃; the specific information is listed in tables 1 and 2. From the above information, a thermal coupling simulation model of the circuit board as shown in fig. 3 was constructed by finite element analysis software ABAQUS.
TABLE 1 substrate and device parameters
TABLE 2 fixed Point parameters
2) Step two, constructing a performance function of thermal stress of the bonding pad and warping of the wafer
Respectively constructing a pad thermal stress performance function by taking a fixed point normal coordinate as an independent variable and taking the peak thermal stress of a pad of the QFN chip and the warpage of a wafer inside the QFN chip as dependent variablesσ(X) And wafer warp performance functionδ(X)；σRepresenting the peak thermal stress of the bonding pad;δindicating wafer warpage, i.e., the normal deviation between the corner points and the center of the wafer;Xrepresenting a fixed point normal coordinate vector, writable toX =(X 1, X 2, X 3, X 4)。
3) Step three, constructing a limiting state equation of thermal stress of the bonding pad and warping of the wafer
In the board level packaging design process, all parameters of the integrated circuit board can be regarded as design variables theoretically; however, the package design is usually limited in practical engineering,such as system architecture requirements, packaging material constraints, etc. In most cases, the normal coordinates of the fixed point can be determined by the designer; therefore, the fixed point normal coordinate is considered as a design variable in the proposed method. max represents the peak calculation, maxσ(X)| eDenotes the peak value of thermal stress of the pad at the time of a fixed point error, maxδ(X)| eDenotes the wafer warp peak in the presence of fixed point error; [σ]=56Mpa represents the allowable stress of the pad material; [δ]=0.04mm represents the allowable warpage of the wafer;eindicating a fixed point error margin for a certain pointX i Due to the existence ofe，X i No longer a certain value but belongs to an interval; the upper and lower bounds of this interval are:X i C - eandX i C + e，X i C is the midpoint of the interval.
4) Step four, establishing an approximate limit state equation of thermal stress of the bonding pad and warping of the wafer
The extreme state equation of the thermal stress of the bonding pad isXOf (2) a midpoint vectorX C Establishing a linear approximation, and establishing an approximate limit state equation of the thermal stress of the bonding pad:
L σ (X) =σ(X C ) + e ∑ n i=1|∂σ(X C )/∂X i | -[σ] = 0
solving the above equation can obtain an optimal package design based on pad thermal stress: (X σ , e σ ) = (0, 0.1mm, -0.1mm, 0.1mm, 0.05mm) 。
The extreme equation of state for wafer warpage isXOf (2) a midpoint vectorX C Establishing a linear approximation, and constructing an approximate limit state equation of the wafer warping:
L δ (X) = δ(X C ) + e ∑ n i=1|∂δ(X C )/∂X i | - [δ] = 0
solving the above equation yields an optimal package design based on wafer warpage: (X δ , e δ ) = (0, -0.1mm, -0.02mm, 0.1mm, 0.03mm ) 。
5) Fifthly, checking the strength of the bonding pad and the warping of the wafer
Will (a) toX σ , e σ ) Substituting the value into the left side of the wafer warping approximate limit state equation, wherein the obtained value of 0.011mm is larger than 0; indicates that the actual warpage value of the wafer has exceeded the allowable warpage value under the packaging design scheme, so (C:)X σ , e σ ) Is an invalid solution. Will (a) toX δ , e δ ) Substituting the obtained value into the left side of the pad thermal stress approximate limit state equation, wherein the obtained value of-1.0 Mpa is less than 0; shows that the packaging design scheme can simultaneously meet the design requirements of both wafer warpage and pad thermal stress, so (C)X δ , e δ ) Is a feasible solution.
6) And step six, ending, and outputting the optimal design of the board level packaging and the optimal error tolerance of the fixed point
(ii) the feasible solution obtained in step 5: (X δ , e δ ) Written as (X *, e *) And outputting;X *=[0, -0.1mm, -0.02mm, 0.1mm,]represents an optimal design of the integrated circuit board package,e *=0.02mm represents the fixed point optimum error tolerance.
To characterize the method of the present invention, the board level package design obtained by the conventional method can be analyzed in comparison with the optimal design obtained by the proposed method. In conventional approaches, board level package designs typically consider a fixed point normal coordinate asX (0)= (0, 0, 0, 0), and its error tolerance may be given according to existing process and design requirementse (0)=0.02 mm. Calculating the peak value max of the thermal stress of the bonding pad according to the extreme state equation in the step threeσ(X (0))|e (0)Greatδ(X (0))|e (0)=0.052 mm. It can be found that the peak value of the crystal warp has become larger than its allowable value [ 2 ]δ]And =0.04mm, which indicates that the board-level packaging design obtained by the conventional method cannot meet the design requirement of the integrated circuit board. Under the optimal design of the plate-level packaging obtained by the method, the peak value max of the thermal stress of the bonding pad isσ(X *)|e *Greatδ(X *)|e *=0.04 mm; the wafer warpage is reduced to a larger extent than the original scheme (from 0.052mm to 0.04mm, and reduced by 23.1%), and the thermal stress peak value and the warpage peak value are both smaller than the respective allowable values. And, optimized error margine *=0.03mm than given empiricallye (0) A major lift of =0.02mm (the former is 1.5 times the latter); the greater the tolerance, the lower the process difficulty and manufacturing cost. Therefore, the optimal design of the board level package obtained by the method provided by the invention can give consideration to high reliability and high cost performance, and has good comprehensive performance.
In addition, linear approximation is established by the extreme state equation in the fourth step, so that a nested optimization searching process of design variable optimization and error interval analysis in the solving process is eliminated, and the calculation efficiency is greatly improved. Different from the conventional optimization method, the method provided by the invention converts the nested solution of design optimization and constraint analysis into a sequence process consisting of two state equation solutions (such as step four) and two times of checking (such as step five), and further improves the efficiency and the convergence.
Claims (1)
1. A board level packaging design optimization method aiming at an integrated QFN chip comprises the following steps:
determining parameters of the integrated circuit board and establishing a thermal coupling simulation model;
the parameters of the integrated circuit board in the step 1) comprise: the structure size, the plane coordinate, the elastic modulus, the Poisson ratio, the thermal expansion coefficient and the working heat consumption of the substrate and each device, the plane coordinate of a fixed point and the working temperature interval of the integrated circuit board; the thermal coupling simulation model in the step 1) refers to: establishing a thermal coupling simulation model of the integrated circuit board according to the determined parameters of the integrated circuit board;
constructing a performance function of the thermal stress of the bonding pad and the warping of the wafer;
the performance function of the thermal stress of the bonding pad and the warping of the wafer in the step 2) refers to: respectively constructing a pad thermal stress performance function sigma (X) and a wafer warping performance function delta (X) by taking a fixed point normal coordinate as an independent variable and taking the QFN chip pad peak thermal stress and the QFN chip internal wafer warping as dependent variables; σ represents the pad peak thermal stress; delta represents wafer warp, i.e., the normal deviation between the corner points and the center of the wafer; x represents a fixed point normal coordinate vector, which may be written as X ═ X (X)1，X2，…，Xi，…，Xn)；
Constructing a limiting state equation of thermal stress of the bonding pad and warping of the wafer;
the extreme state equation of the thermal stress of the bonding pad and the warping of the wafer in the step 3) refers to: considering the existence of fixed point processing errors, respectively constructing a QFN chip bonding pad peak value thermal stress limit state equation max { sigma (X) | e } - [ sigma (X) | e) ]]0 and QFN chip internal wafer warpage limit state equation max { δ (X) | e } - [ δ (X) |]0; max represents the peak calculation, max { σ (X) | e } represents the pad thermal stress peak when there is a fixed point error, max { δ (X) | e } represents the wafer warp peak when there is a fixed point error; [ sigma ]]Indicating allowable stress of the pad material; [ delta ] is]Indicating an allowable warpage of the wafer; e denotes the fixed point error tolerance for a certain XiDue to the presence of e, XiNo longer a certain value but belongs to an interval; the upper and lower bounds of this interval are:
and
is the midpoint of the interval；
Constructing an approximate limit state equation of the thermal stress of the bonding pad and the warping of the wafer;
the approximate limit state equation of the thermal stress of the bonding pad in the step 4) refers to: establishing a linear approximation for the extreme state equation of the pad thermal stress at a midpoint vector XC of X, and constructing an approximate extreme state equation of the pad thermal stress:
solving the above equation can obtain an optimal package design based on pad thermal stress: (X)σ，eσ)；
The approximate limit state equation of the wafer warping in the step 4) refers to: establishing a linear approximation for the extreme state equation of wafer warpage at the midpoint vector XC of X, and constructing an approximate extreme state equation of wafer warpage:
solving the above equation yields an optimal package design based on wafer warpage: (X)δ，eδ)；
Checking the strength of the bonding pad and the warping of the wafer;
checking the strength of the bonding pad in the step 5) refers to: will (X)σ，eσ) Substituting into the left side of the approximate limit equation of state of wafer warpage to obtain a value (X) of 0 or lessσ，eσ) Is a feasible solution, otherwise is an invalid solution; the step 5) of checking the wafer warpage is as follows: will (X)δ，eδ) Substituting into the left side of the pad thermal stress approximate limit state equation to obtain a value (X) less than or equal to 0δ，eδ) Is a feasible solution, otherwise is an invalid solution;
finishing and outputting the optimal design of board level packaging and the optimal error tolerance of a fixed point;
the optimal design of board level packaging and the optimal error tolerance of the fixed point in the step 6) are as follows: what is needed isThe feasible solution obtained in the step 5) can be written as (X)*，e*)；X*Represents the board level package optimal design, e*Representing a fixed point optimum error margin.
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Inventor after: Huang Zhiliang Inventor after: Zeng Qi Inventor after: Zeng Xianchen Inventor after: Yang Tongguang Inventor after: Li Hangyang Inventor after: Zhao Zhiguo Inventor before: Huang Zhiliang Inventor before: Li Xiao Inventor before: Zhou Chaolun Inventor before: Zeng Xianchen |
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Application publication date: 20181002 Assignee: Hunan Hongyuyun Technology Co.,Ltd. Assignor: Hunan City University Contract record no.: X2022980020752 Denomination of invention: An Optimization Method of Board Level Packaging Design for Integrated QFN Chip Granted publication date: 20220412 License type: Exclusive License Record date: 20221110 |