CN108614941A - A kind of Board level packaging design optimization method for integrated QFN chips - Google Patents
A kind of Board level packaging design optimization method for integrated QFN chips Download PDFInfo
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- G06F30/39—Circuit design at the physical level
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Abstract
The present invention discloses a kind of Board level packaging design optimization method for integrated QFN chips, and step includes：It determines the parameter of integrated circuit board and establishes Thermal-mechanical Coupling simulation model；Build the performance function of pad thermal stress and chip warpage；Build the limit state equation of pad thermal stress and chip warpage；Build the approximate limit state equation of pad thermal stress and chip warpage；Check pad intensity and chip warpage；Terminate and export Board level packaging optimal design and fixed point Optimal error tolerance.The present invention to the Board level packaging for integrating QFN chips by building Thermal-mechanical Coupling simulation model, and limit state equation is established using interval analysis technology, gained Board level packaging optimization design scheme can not only meet the design requirement of thermal stress and warpage, while also have minimum processing cost and technology difficulty.Also, institute's extracting method of the present invention has good comprehensive performance in terms of efficiency and convergence.
Description
Technical field
The invention belongs to IC package design fields, and in particular to a kind of Board level packaging for integrated QFN chips
Design optimization method.
Background technology
Encapsulation not only can provide necessary electrical connection for integrated circuit and external system, also play machinery to integrated circuit
Or the effect of environmental protection.With the rapid development of microelectric technique, the high encapsulation design of high level, which has become one and has much, chooses
The work of war.Encapsulation generally may be defined to 4 ranks：Wafer scale, chip-scale, plate grade and system-level.Board level packaging refers to by core
Piece and passive device are installed on printed circuit board jointly, to constitute the integrated circuit board with specific function.Board level packaging needs
A stabilization, reliable working environment are provided for integrated chip；Therefore the encapsulation characteristic of chip itself sets Board level packaging
Meter has vital influence.QFN is encapsulated as a kind of leaderless chip carrier（Also referred to as LCC）, because its pin and pad it
Between conductive path it is short and there is very low electrodynamic capacity and resistance, so it can provide remarkable electrical property.Currently, QFN chips
It is widely used in mobile phone, tablet and other portable miniaturized electronics.
Since the substrate and institute integrated device encapsulating material coefficient of thermal expansion of integrated circuit board are different, in chip spontaneous heating and
Local thermal stress and warpage will be generated under the comprehensive function of variation of ambient temperature, be lost with electrical property so as to cause encapsulation crackle
It is very etc. of serious failure.When Board level packaging integrates QFN chips, this problem is then especially prominent.In most cases, QFN chips are electricity
The core devices of subsystem, electrical property can directly determine systematic entirety energy.Also, QFN chip structures are very accurate,
Even local micron order warpage all may cause its electrical property relatively large deviation occur.Traditional Board level packaging design relies primarily on work
Journey experience, due to lacking necessary theoretical foundation, it is difficult to realize optimal design；When facing such challenge（As QFN chips are stuck up
Bent tolerance is only micron order）, conventional method is often difficult to meet design requirement.Relatively advanced design method is by numerical simulation
Technology is organically combined with optimum theory, by building the Optimized model based on numerical simulation to realize that the optimization of Board level packaging is set
Meter.The research of such method is still in the elementary step, and there are still a series of technological difficulties urgent need to resolve.First, structure is effectively excellent
Change model not only to need to consider electrical property, hot property and the mechanical performance of integrated circuit board, also need to take into account manufacturing cost and
Technology difficulty, this is for the great challenge of those skilled in the art.Secondly, object function or constraint are emulated based on time-consuming in Optimized model
Model, design optimizing are nested with one another with about beam analysis, including the Optimized model solution of numerical simulation may face serious efficiency
Problem and convergence obstacle.Therefore, for the integrated circuit board of integrated high-performance QFN chips, a kind of effective Board level packaging is proposed
Design optimization method, for realizing that the rate electronics packages design of high performance-price ratio and high reliability has very important engineering meaning
Justice.
Invention content
The purpose of the present invention is to provide a kind of Board level packaging design optimization method for integrated QFN chips, this method
Based on circuit board Thermal-mechanical Coupling simulation model, pole is built one by one to not knowing QFN chips thermal stress under operating mode and Local warping
Limit state equation simultaneously solves, to obtain the Board level packaging design scheme of tool optimal cost.The present invention passes through following technical proposals
It realizes.
A kind of Board level packaging design optimization method for integrated QFN chips, this approach includes the following steps.
1）It determines the parameter of integrated circuit board and establishes Thermal-mechanical Coupling simulation model；
2）Build the performance function of pad thermal stress and chip warpage；
3）Build the limit state equation of pad thermal stress and chip warpage；
4）Build the approximate limit state equation of pad thermal stress and chip warpage；
5）Check pad intensity and chip warpage；
6）Terminate and export Board level packaging optimal design and fixed point Optimal error tolerance.
Further, the step 1）The parameter of middle integrated circuit board includes：The structure size of substrate and each device, plane
The work of coordinate, elasticity modulus, Poisson's ratio, coefficient of thermal expansion, work heat consumption and fixed point plane coordinates, integrated circuit board
Temperature range；The step 1）Middle Thermal-mechanical Coupling simulation model refers to：According to identified integrated circuit board parameter, establish integrated
Circuit board Thermal-mechanical Coupling simulation model.
Further, the step 2）The performance function of middle pad thermal stress and chip warpage refers to：With fixed point normal direction
Coordinate is independent variable, using QFN chip bonding pad peak value thermal stress and QFN chip interiors chip warpage as dependent variable, structure weldering respectively
Disk thermal stress performance functionσ(X) and chip warpage performance functionδ(X)；σIndicate pad peak value thermal stress；δIndicate chip warpage,
Norma l deviation i.e. between chip angle point and center；XIt indicates fixed point normal direction coordinate vector, can be write asX =(X 1, X 2,…,X i ,…,X n )。
Further, the step 3）The limit state equation of middle pad thermal stress and chip warpage refers to：Consider exist
Fixed point mismachining tolerance, build respectively QFN chip bonding pad peak heat limiting range of stress state equations maxσ(X)| e } -[σ] =
0 and QFN chip interior chip warpage limit state equations maxδ(X)| e } -[δ] = 0；Max indicates peak computational, max
{σ(X)| ePad thermal stress peak value when indicating to have fixed point tolerance, maxδ(X)|eIndicate there is fixed point tolerance
When chip warpage peak value；[σ] indicate bonding pad material allowable stress；[δ] indicate chip allowance for camber；eIndicate fixed point
Error margin, for a certainX i Due to existinge,X i No longer it is a determination value and belongs to a section；The bound in the section is：X i C
- eWithX i C + e,X i C For interval midpoint.
Further, the step 4）The approximate limit state equation of middle pad thermal stress refers to：To pad thermal stress
Limit state equation existsXMidpoint vectorX C Place establishes linear approximation, builds the approximate limit state equation of pad thermal stress：
L σ (X) =σ(X C ) + e ∑ n i=1|∂σ(X C )/∂X i | -[σ] = 0
The optimal encapsulation design based on pad thermal stress can be obtained by solving above formula：(X σ , e σ )。
Further, the step 4）The approximate limit state equation of middle chip warpage refers to：To the limit of chip warpage
State equation existsXMidpoint vectorX C Place establishes linear approximation, builds the approximate limit state equation of chip warpage：
L δ (X) = δ(X C ) + e ∑ n i=1|∂δ(X C )/∂X i | -[δ] = 0
The optimal encapsulation design based on chip warpage can be obtained by solving above formula：(X δ , e δ )。
Further, the step 5）Middle check pad intensity refers to：Will (X σ , e σ ) it is updated to chip warpage approximation pole
The left side of limit state equation, 0 such as less than or equal to of resulting value (X σ , e σ ) it is feasible solution, it is otherwise trivial solution；The step
5）Lieutenant colonel's nuclear crystalline film warpage refers to：Will (X δ , e δ ) it is updated to the left side of pad thermal stress approximate limit state equation, resulting value is such as
Less than or equal to 0 (X δ , e δ ) it is feasible solution, it is otherwise trivial solution；
Further, the step 6）Middle Board level packaging optimal design and fixed point Optimal error tolerance refer to：The step 5）
Obtained feasible solution, can be write as (X *, e *)；X *Indicate Board level packaging optimal design,e *Indicate fixed point Optimal error tolerance.
Compared with prior art, the present invention having the characteristics that：
1）Pass through and builds limit state equation, it is contemplated that there are the QFN chips part thermal stress and chip warpage when mismachining tolerance,
Thus obtained encapsulation design scheme can have good engineering practicability.
2）By maximizing error margin so that gained Board level packaging design scheme can not only meet thermal stress and warpage
Design requirement, while also have minimum processing cost and technology difficulty；
3）It solves limit state equation and faces double-layer nested optimization, outer layer is to design variable optimizing, and internal layer is error burst point
Analysis；By establishing linear approximation to limit state equation, the nested searching process in solution procedure is avoided, meter is greatly improved
Calculate efficiency；
4）It avoids and designs optimizing solution nested with about beam analysis in optimization routine model, by design optimization and Ge Yue beam analysis
It is changed into a sequence solution procedure, further improves efficiency and convergence.
Description of the drawings
Fig. 1 is Board level packaging design optimization flow chart of the institute's needle of the present invention to integrated QFN chips；
Fig. 2 is integrated circuit board encapsulation figure；
Fig. 3 is integrated circuit board Thermal-mechanical Coupling simulation model figure；
Fig. 4 is QFN chips thermal stress figure under Board level packaging optimal design；
Fig. 5 is QFN chips buckle pattern under Board level packaging optimal design.
Specific implementation mode
The present invention will be further described with reference to the accompanying drawings and embodiments.
Shown in referring to Fig.1, a kind of Board level packaging design optimization method for integrated QFN chips of the present invention, step
It is rapid as follows.
1）Step 1 determines the parameter of integrated circuit board and establishes Thermal-mechanical Coupling simulation model
With reference to shown in Fig. 2, according to existing information, the parameter of integrated circuit board is determined, including：Substrate 01, QFN chips each section 02
~ 06 and the structure size of device 07 ~ 10, plane coordinates, elasticity modulus, Poisson's ratio, coefficient of thermal expansion, work heat consumption, Yi Jigu
The plane coordinates of fixed point 11 ~ 12, the operating temperature section [- 20 DEG C, 60 DEG C] of integrated circuit board；Specifying information such as Tables 1 and 2 institute
Row.Circuit board Thermal-mechanical Coupling emulation mould as shown in Figure 3 is established by finite element analysis software ABAQUS according to above- mentioned information
Type.
1 substrate of table and device parameters
2 fixed point parameter of table
2）Step 2 builds the performance function of pad thermal stress and chip warpage
Using fixed point normal direction coordinate as independent variable, using QFN chip bonding pad peak value thermal stress and QFN chip interiors chip warpage as because
Variable builds pad thermal stress performance function respectivelyσ(X) and chip warpage performance functionδ(X)；σIndicate that pad peak heat is answered
Power；δIndicate chip warpage, i.e. Norma l deviation between chip angle point and center；XIndicate fixed point normal direction coordinate vector, it is writeable
AtX =(X 1, X 2, X 3, X 4)。
3）Step 3 builds the limit state equation of pad thermal stress and chip warpage
In Board level packaging design process, theoretically all parameters of said integrated circuit plate can be regarded as design variable；So
And encapsulating design would generally be subject to many limitations in Practical Project, for example system structure requires, encapsulating material limits etc..And
In most cases, the normal direction coordinate of fixed point can be determined by designer；So fixed point normal direction is sat in institute's extracting method
Mark is regarded as design variable.Max expression peak computationals, maxσ(X)| eIndicate the pad thermal stress for having when fixing point tolerance
Peak value, maxδ(X)| eIndicate the chip warpage peak value for having when fixing point tolerance；[σ]=56Mpa indicates bonding pad material
Allowable stress；[δ]=0.04mm indicates the allowance for camber of chip；eFixed point error margin is indicated, for a certainX i Due to existinge,X i No longer it is a determination value and belongs to a section；The bound in the section is：X i C - eWithX i C + e,X i C For interval midpoint.
4）Step 4 builds the approximate limit state equation of pad thermal stress and chip warpage
Exist to the limit state equation of pad thermal stressXMidpoint vectorX C Place establishes linear approximation, structure pad thermal stress
Approximate limit state equation：
L σ (X) =σ(X C ) + e ∑ n i=1|∂σ(X C )/∂X i | -[σ] = 0
The optimal encapsulation design based on pad thermal stress can be obtained by solving above formula：(X σ , e σ ) = (0, 0.1mm, -0.1mm,
0.1mm, 0.05mm) 。
Exist to the limit state equation of chip warpageXMidpoint vectorX C Place establishes linear approximation, builds chip warpage
Approximate limit state equation：
L δ (X) = δ(X C ) + e ∑ n i=1|∂δ(X C )/∂X i | - [δ] = 0
The optimal encapsulation design based on chip warpage can be obtained by solving above formula：(X δ , e δ ) = (0, -0.1mm, -0.02mm,
0.1mm, 0.03mm ) 。
5）Step 5 checks pad intensity and chip warpage
Will (X σ , e σ ) it is updated to the left side of chip warpage approximate limit state equation, resulting value 0.011mm is more than 0；It indicates
Under the encapsulation design scheme, the practical warp value of chip has been over allowance for camber value, so (X σ , e σ ) it is trivial solution.It will
(X δ , e δ ) it is updated to the left side of pad thermal stress approximate limit state equation, resulting value -1.0Mpa is less than 0；Indicate that the encapsulation is set
Meter scheme can meet design requirement of both chip warpage and pad thermal stress simultaneously, so (X δ , e δ ) it is feasible solution.
6）Step 6 terminates, and exports Board level packaging optimal design and fixed point Optimal error tolerance
By step 5）Obtain feasible solution (X δ , e δ ) write as (X *, e *) and export；X *=[0, -0.1mm, -0.02mm,
0.1mm ,] indicate that integrated circuit board encapsulates optimal design,e *=0.02mm indicates fixed point Optimal error tolerance.
To show the characteristic of institute's extracting method of the present invention, the Board level packaging obtained by conventional method can be designed and institute's extracting method obtains
To optimal design do comparative analysis.In conventional method, fixed point normal direction coordinate is usually thought of as by Board level packaging designX (0)
=(0,0,0,0), and its error margin can be given according to prior art and design requiremente (0)= 0.02mm.Pass through step
Three limit state equations calculate pad thermal stress peak value maxσ(X (0))|e (0)}=55.09Mpa and crystal warpage peak value max
{δ(X (0))|e (0)}=0.052mm.It can be found that crystal warpage peak value be more than its allowable value [δ]=0.04mm shows conventional side
Board level packaging design obtained by method cannot meet the design requirement of the integrated circuit board.And the plate grade envelope that institute's extracting method of the present invention obtains
It fills under optimal design, pad thermal stress peak value maxσ(X *)|e *}=55.0Mpa and crystal warpage peak value maxδ(X *)|e *}=
0.04mm；Chip warpage has compared with initial scheme and largely reduces（It is reduced to 0.04mm from 0.052mm, reduces 23.1%）,
And thermal stress peak value and warpage peak value are respectively less than respective allowable value.Also, the error margin after optimizinge *=0.03mm is compared with root
It is given according to experiencee (0) =0.02mm is largely promoted（The former is 1.5 times of the latter）；Tolerance is easy bigger, technique hardly possible
Degree and manufacturing cost are lower.It is indicated above that Board level packaging optimal design obtained by institute's extracting method of the present invention can take into account high reliability
And high performance-price ratio, there is good comprehensive performance.
In addition, eliminating by establishing linear approximation to limit state equation in step 4 and designing change in solution procedure
The nested searching process that amount optimizing is analyzed with error burst, greatly improves computational efficiency.It is different from classical algorithm, this hair
Bright institute's extracting method will design optimizing solution nested with about beam analysis and be changed by two Solving Equation of State（Such as step 4）With
It checks twice（Such as step 5）The sequence process of composition, further improves efficiency and convergence.
Claims (8)
1. a kind of Board level packaging design optimization method for integrated QFN chips, this approach includes the following steps：
It determines the parameter of integrated circuit board and establishes Thermal-mechanical Coupling simulation model；
Build the performance function of pad thermal stress and chip warpage；
Build the limit state equation of pad thermal stress and chip warpage；
Build the approximate limit state equation of pad thermal stress and chip warpage；
Check pad intensity and chip warpage；
Terminate and export Board level packaging optimal design and fixed point Optimal error tolerance.
2. the S type runner layout optimization design methods according to claim 1 for liquid cooling heat radiator, which is characterized in that
The step 1）The parameter of middle integrated circuit board includes：The structure size of substrate and each device, plane coordinates, elasticity modulus, pool
The operating temperature section of loose ratio, coefficient of thermal expansion, work heat consumption and fixed point plane coordinates, integrated circuit board；The step
1）Middle Thermal-mechanical Coupling simulation model refers to：According to identified integrated circuit board parameter, it is imitative to establish integrated circuit board Thermal-mechanical Coupling
True mode.
3. the S type runner layout optimization design methods according to claim 1 for liquid cooling heat radiator, which is characterized in that
The step 2）The performance function of middle pad thermal stress and chip warpage refers to：Using fixed point normal direction coordinate as independent variable, with QFN
Chip bonding pad peak value thermal stress and QFN chip interior chip warpages are dependent variable, build pad thermal stress performance function respectivelyσ
(X) and chip warpage performance functionδ(X)；σIndicate pad peak value thermal stress；δIndicate chip warpage, i.e. chip angle point and center
Between Norma l deviation；XIt indicates fixed point normal direction coordinate vector, can be write asX =(X 1, X 2,…,X i ,…,X n )。
4. the S type runner layout optimization design methods according to claim 1 for liquid cooling heat radiator, which is characterized in that
The step 3）The limit state equation of middle pad thermal stress and chip warpage refers to：Consider there are fixed point mismachining tolerance, point
Not Gou Jian QFN chip bonding pad peak heat limiting range of stress state equations maxσ(X)| e } -[σ]=0 and QFN chip interiors are brilliant
Piece buckle limit state equation maxδ(X)| e } -[δ] = 0；Max expression peak computationals, maxσ(X)| eIndicate to deposit
Pad thermal stress peak value in fixed point tolerance, maxδ(X)|eIndicate the chip warpage peak for having when fixing point tolerance
Value；[σ] indicate bonding pad material allowable stress；[δ] indicate chip allowance for camber；eFixed point error margin is indicated, to Mr. Yu
OneX i Due to existinge,X i No longer it is a determination value and belongs to a section；The bound in the section is：X i C - eWithX i C + e,X i C
For interval midpoint.
5. the S type runner layout optimization design methods according to claim 1 for liquid cooling heat radiator, which is characterized in that
The step 4）The approximate limit state equation of middle pad thermal stress refers to：Exist to the limit state equation of pad thermal stressX's
Midpoint vectorX C Place establishes linear approximation, builds the approximate limit state equation of pad thermal stress：
L σ (X) =σ(X C ) + e ∑ n i=1|∂σ(X C )/∂X i | -[σ] = 0
The optimal encapsulation design based on pad thermal stress can be obtained by solving above formula：(X σ , e σ )。
6. the S type runner layout optimization design methods according to claim 1 for liquid cooling heat radiator, which is characterized in that
The step 4）The approximate limit state equation of middle chip warpage refers to：Exist to the limit state equation of chip warpageXMidpoint
VectorX C Place establishes linear approximation, builds the approximate limit state equation of chip warpage：
L δ (X) = δ(X C ) + e ∑ n i=1|∂δ(X C )/∂X i | -[δ] = 0
The optimal encapsulation design based on chip warpage can be obtained by solving above formula：(X δ , e δ )。
7. the S type runner layout optimization design methods according to claim 1 for liquid cooling heat radiator, which is characterized in that
The step 5）Middle check pad intensity refers to：Will (X σ , e σ ) it is updated to the left side of chip warpage approximate limit state equation,
0 such as less than or equal to of resulting value (X σ , e σ ) it is feasible solution, it is otherwise trivial solution；The step 5）Lieutenant colonel's nuclear crystalline film warpage is
Refer to：Will (X δ , e δ ) it is updated to the left side of pad thermal stress approximate limit state equation, 0 such as less than or equal to of resulting value (X δ ,e δ ) it is feasible solution, it is otherwise trivial solution.
8. the S type runner layout optimization design methods according to claim 1 for liquid cooling heat radiator, which is characterized in that
The step 6）Middle Board level packaging optimal design and fixed point Optimal error tolerance refer to：The step 5）Obtained feasible solution,
Can be write as (X *, e *)；X *Indicate Board level packaging optimal design,e *Indicate fixed point Optimal error tolerance.
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| CN111985055A (en) * | 2020-08-28 | 2020-11-24 | 北京世冠金洋科技发展有限公司 | Model packaging method and device and electronic equipment |
| CN113068326A (en) * | 2021-03-29 | 2021-07-02 | 北京小米移动软件有限公司 | Welding quality processing method and device and circuit board |
| CN114417476A (en) * | 2022-01-24 | 2022-04-29 | 杭州朗迅科技有限公司 | Virtual simulation model and practical training system of integrated circuit packaging industrial line |
| CN116401803A (en) * | 2021-12-20 | 2023-07-07 | 本源量子计算科技（合肥）股份有限公司 | Thermodynamic simulation method, device and storage medium for quantum chip packaging structure |
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| CN111985055A (en) * | 2020-08-28 | 2020-11-24 | 北京世冠金洋科技发展有限公司 | Model packaging method and device and electronic equipment |
| CN111985055B (en) * | 2020-08-28 | 2023-08-08 | 北京世冠金洋科技发展有限公司 | Model packaging method and device and electronic equipment |
| CN113068326A (en) * | 2021-03-29 | 2021-07-02 | 北京小米移动软件有限公司 | Welding quality processing method and device and circuit board |
| CN116401803A (en) * | 2021-12-20 | 2023-07-07 | 本源量子计算科技（合肥）股份有限公司 | Thermodynamic simulation method, device and storage medium for quantum chip packaging structure |
| CN116401803B (en) * | 2021-12-20 | 2024-06-14 | 本源量子计算科技（合肥）股份有限公司 | Thermodynamic simulation method, device and storage medium for quantum chip packaging structure |
| CN114417476A (en) * | 2022-01-24 | 2022-04-29 | 杭州朗迅科技有限公司 | Virtual simulation model and practical training system of integrated circuit packaging industrial line |
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Inventor after: Huang Zhiliang Inventor after: Zeng Qi Inventor after: Zeng Xianchen Inventor after: Yang Tongguang Inventor after: Li Hangyang Inventor after: Zhao Zhiguo Inventor before: Huang Zhiliang Inventor before: Li Xiao Inventor before: Zhou Chaolun Inventor before: Zeng Xianchen |
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Application publication date: 20181002 Assignee: Hunan Hongyuyun Technology Co.,Ltd. Assignor: Hunan City University Contract record no.: X2022980020752 Denomination of invention: An Optimization Method of Board Level Packaging Design for Integrated QFN Chip Granted publication date: 20220412 License type: Exclusive License Record date: 20221110 |