WO2024066226A1 - Method for constructing storage chip packaging structure and packaging structure - Google Patents

Method for constructing storage chip packaging structure and packaging structure Download PDF

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Publication number
WO2024066226A1
WO2024066226A1 PCT/CN2023/081592 CN2023081592W WO2024066226A1 WO 2024066226 A1 WO2024066226 A1 WO 2024066226A1 CN 2023081592 W CN2023081592 W CN 2023081592W WO 2024066226 A1 WO2024066226 A1 WO 2024066226A1
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chip
packaging structure
present
constructing
packaging
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PCT/CN2023/081592
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French (fr)
Chinese (zh)
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刘欢
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华进半导体封装先导技术研发中心有限公司
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Publication of WO2024066226A1 publication Critical patent/WO2024066226A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings

Definitions

  • the present invention generally relates to the field of semiconductor packaging technology. Specifically, the present invention relates to a method for constructing a memory chip packaging structure and a packaging structure.
  • the memory chip and the control chip are usually arranged on the same side or different sides of a packaging carrier, and the memory chip and the control chip are plastic-sealed using a plastic packaging material.
  • the traditional packaging structure since the memory chip and the control chip are arranged on the surface of the packaging carrier, the volume of the packaging structure is too large; and since a large amount of plastic packaging material is used, the heat dissipation of the packaging carrier is affected, and it is also easy to cause the packaging carrier to warp, which affects the reliability of subsequent packaging; in addition, the traditional packaging structure usually uses a printed circuit board (PCB) as a packaging carrier, but due to the large process nodes and size of the printed circuit board, it is difficult to meet the current higher integration density packaging requirements.
  • PCB printed circuit board
  • the present invention provides a method for constructing a memory chip packaging structure, comprising the following steps:
  • the first side of the second chip is stacked on the second side of the first chip.
  • the method for constructing a memory chip packaging structure further includes:
  • the second through silicon via is connected to the first through silicon via when the second chip is stacked on the first chip.
  • the second chip includes one or more storage areas.
  • the number of the storage areas is greater than or equal to 4.
  • a plurality of the second chips are provided, wherein the plurality of the second chips are stacked on top of each other.
  • the present invention also provides a memory chip packaging structure, which is constructed according to the method for constructing a memory chip packaging structure, and the structure includes:
  • a first chip wherein a groove is provided on a first surface of the first chip, and a control chip is arranged at the groove;
  • the second chip comprises a memory chip, wherein a first side of the second chip is stacked on a second side of the first chip.
  • the first chip further includes a first through silicon via
  • the second chip further includes a second through silicon via, wherein the first through silicon via is connected to the second through silicon via.
  • the second chip includes one or more storage areas.
  • the number of the storage areas is greater than or equal to 4.
  • the memory chip packaging structure includes:
  • a plurality of second chips wherein the plurality of second chips are stacked on each other.
  • the present invention has at least the following beneficial effects:
  • the present invention provides a method and a packaging structure for constructing a memory chip packaging structure, wherein a TSV structure is constructed on the chip body, and the functional chip and the adapter board in the traditional packaging structure are combined into one, thereby improving the chip performance while reducing the packaging volume, and the present invention utilizes the back space of the functional chip to dig a cavity and bury the control chip, which can effectively improve the integration of the three-dimensional packaging.
  • FIG. 1 is a schematic flow chart showing a method for constructing a memory chip packaging structure in an embodiment of the present invention.
  • FIGS. 2 to 5 are structural diagrams showing the construction process of a memory chip packaging structure in one embodiment of the present invention.
  • FIG. 6 shows a top view of a second chip according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram showing a memory chip packaging structure in an embodiment of the present invention.
  • the quantifiers "a”, “an” and “an” do not exclude the presence of a plurality of elements.
  • the terms “same”, “equal”, “equal to” and the like do not mean that the values of the two are absolutely equal, but allow a certain reasonable error, that is, the terms also cover “substantially the same”, “substantially equal”, “substantially equal to”.
  • the terms “perpendicular to”, “parallel to” and the like indicating directions also cover the meanings of “substantially perpendicular to” and “substantially parallel to”.
  • the numbering of the steps of the methods of the present invention does not limit the execution order of the method steps. Unless otherwise specified, the method steps can be executed in different orders.
  • FIG1 is a schematic flow chart showing a method for constructing a memory chip packaging structure in an embodiment of the present invention. As shown in FIG1 , the method may include the following steps:
  • Step 101 Provide a first chip 201.
  • Step 102 constructing a groove 301 on the first surface of the first chip 201 .
  • Step 103 arranging a control chip 401 in the groove 301 .
  • Step 104 providing a second chip 501 , wherein a storage area 502 is provided on the second chip 501 .
  • Step 105 stacking the first surface of the second chip 501 on the second surface of the first chip 201 .
  • Figures 2 to 5 show the structural diagrams of the construction process of a memory chip packaging structure in one embodiment of the present invention. The steps of the construction method are described in detail below in conjunction with Figures 2 to 5.
  • a first chip 201 may be provided, wherein a first storage area (not shown in the figure) is provided on the second surface of the first chip 201 , and a first through silicon via 202 (TSV) may be provided around the first storage area, and the first through silicon via 202 may pass through the first surface and the second surface of the first chip 201 .
  • TSV through silicon via 202
  • a groove 301 may be formed on the first surface of the first chip 201 by photolithography or etching.
  • a control chip 401 may be arranged in the groove 301.
  • the integration of three-dimensional packaging can be effectively improved.
  • a second chip 501 may be provided in step 104, wherein a second storage area 503 is provided on the second chip 501, and a second through silicon via 502 is provided around the second storage area 503.
  • FIG6 shows a top view of a second chip 501 in an embodiment of the present invention, and as shown in FIG6 , the second chip 501 may include a plurality of second storage areas 503, and the number of the second storage areas 503 may be greater than or equal to 4.
  • FIG7 shows a schematic diagram of a memory chip packaging structure in an embodiment of the present invention.
  • the second chip 501 may be stacked on the first chip 201 to form the packaging structure shown in FIG7, wherein a plurality of the second chips 501 may be stacked on each other and then stacked on the first chip 201.
  • the first chip 201 and the second chip may be connected to each other through the first through silicon via 202 and the second through silicon via 502.
  • the memory chip packaging structure may include:
  • a first chip 201 wherein a groove 301 is provided on a first surface of the first chip 201, and a control chip 401 is arranged in the groove 301;

Abstract

The present invention relates to the technical field of semiconductor packaging, and proposes a method for constructing a storage chip packaging structure and a packaging structure. The method comprises the following steps: providing a first chip; constructing a groove on a first surface of the first chip; arranging a control chip at the groove; providing a second chip, wherein a storage area is provided on the second chip; and stacking a first surface of the second chip onto a second surface of the first chip. According to the present invention, a TSV structure is constructed on a chip body, a functional chip and an adapter plate in a traditional packaging structure are combined into one, thereby reducing the packaging volume while improving the chip performance. Moreover, according to the present invention, the back surface space of the functional chip is used for digging a cavity and embedding same into the control chip, and the integration level of three-dimensional direction packaging may be effectively improved.

Description

一种构造存储芯片封装结构的方法及封装结构A method for constructing a memory chip packaging structure and a packaging structure 技术领域Technical Field
本发明总的来说涉及半导体封装技术领域。具体而言，本发明涉及一种构造存储芯片封装结构的方法及封装结构。The present invention generally relates to the field of semiconductor packaging technology. Specifically, the present invention relates to a method for constructing a memory chip packaging structure and a packaging structure.
背景技术Background technique
传统上在对存储芯片以及控制芯片进行封装时通常在封装载体的同一侧或者不同侧布置存储芯片以及控制芯片，并且使用塑封材料将存储芯片以及控制芯片塑封。Conventionally, when packaging a memory chip and a control chip, the memory chip and the control chip are usually arranged on the same side or different sides of a packaging carrier, and the memory chip and the control chip are plastic-sealed using a plastic packaging material.
然而在传统的封装结构中，由于存储芯片以及控制芯片均布置在封装载体表面，使得封装结构的体积过大；并且由于使用大量的塑封材料，对封装载体的散热造成了影响，也容易造成封装载体的翘曲，对后续封装的可靠性造成影响；另外传统的封装结构通常使用印制电路板(PCB，Printed Circuit Board)作为封装载体，然而由于印制电路板的工艺节点和尺寸均较大，因此难以满足目前更高集成密度的封装要求。However, in the traditional packaging structure, since the memory chip and the control chip are arranged on the surface of the packaging carrier, the volume of the packaging structure is too large; and since a large amount of plastic packaging material is used, the heat dissipation of the packaging carrier is affected, and it is also easy to cause the packaging carrier to warp, which affects the reliability of subsequent packaging; in addition, the traditional packaging structure usually uses a printed circuit board (PCB) as a packaging carrier, but due to the large process nodes and size of the printed circuit board, it is difficult to meet the current higher integration density packaging requirements.
发明内容Summary of the invention
为至少部分解决现有技术中的上述问题，本发明提出一种构造存储芯片封装结构的方法，包括下列步骤：In order to at least partially solve the above problems in the prior art, the present invention provides a method for constructing a memory chip packaging structure, comprising the following steps:
提供第一芯片；providing a first chip;
在所述第一芯片的第一面上构造凹槽；constructing a groove on the first surface of the first chip;
在所述凹槽处布置控制芯片；Arranging a control chip in the groove;
提供第二芯片，其中所述第二芯片上设置有存储区域；以及providing a second chip, wherein a storage area is disposed on the second chip; and
将所述第二芯片的第一面堆叠在所述第一芯片的第二面上。The first side of the second chip is stacked on the second side of the first chip.
在本发明一个实施例中规定，所述构造存储芯片封装结构的方法还包括：In one embodiment of the present invention, the method for constructing a memory chip packaging structure further includes:
在所述第一芯片上构造第一硅通孔；constructing a first through silicon via on the first chip;
在所述第二芯片上构造第二硅通孔；以及constructing a second through silicon via on the second chip; and
在将所述第二芯片堆叠在所述第一芯片的上时将所述第二硅通孔与所述第一硅通孔连接。 The second through silicon via is connected to the first through silicon via when the second chip is stacked on the first chip.
在本发明一个实施例中规定，所述第二芯片包括一个或者多个存储区域。In one embodiment of the present invention, it is provided that the second chip includes one or more storage areas.
在本发明一个实施例中规定，所述存储区域的数量大于等于4。In one embodiment of the present invention, it is provided that the number of the storage areas is greater than or equal to 4.
在本发明一个实施例中规定，提供多个所述第二芯片，其中将多个所述第二芯片相互堆叠。In one embodiment of the present invention, it is provided that a plurality of the second chips are provided, wherein the plurality of the second chips are stacked on top of each other.
本发明还提出一种存储芯片封装结构，其根据所述构造存储芯片封装结构的方法进行构造，该结构包括：The present invention also provides a memory chip packaging structure, which is constructed according to the method for constructing a memory chip packaging structure, and the structure includes:
第一芯片，其中所述第一芯片的第一面上设置有凹槽，并且在所述凹槽处布置有控制芯片；A first chip, wherein a groove is provided on a first surface of the first chip, and a control chip is arranged at the groove;
第二芯片，其包括存储芯片，其中所述第二芯片的第一面堆叠在所述第一芯片的第二面上。The second chip comprises a memory chip, wherein a first side of the second chip is stacked on a second side of the first chip.
在本发明一个实施例中规定，所述第一芯片还包括第一硅通孔，所述第二芯片还包括第二硅通孔，其中所述第一硅通孔与所述第二硅通孔连接。In one embodiment of the present invention, it is provided that the first chip further includes a first through silicon via, and the second chip further includes a second through silicon via, wherein the first through silicon via is connected to the second through silicon via.
在本发明一个实施例中规定，所述第二芯片包括一个或者多个存储区域。In one embodiment of the present invention, it is provided that the second chip includes one or more storage areas.
在本发明一个实施例中规定，所述存储区域的数量大于等于4.In one embodiment of the present invention, it is provided that the number of the storage areas is greater than or equal to 4.
在本发明一个实施例中规定，所述存储芯片封装结构包括：In one embodiment of the present invention, the memory chip packaging structure includes:
多个第二芯片，其中多个所述第二芯片相互堆叠。A plurality of second chips, wherein the plurality of second chips are stacked on each other.
本发明至少具有如下有益效果：本发明提出一种构造存储芯片封装结构的方法及封装结构。其中在芯片本体上构造TSV结构，将传统封装结构中的功能芯片与转接板合二为一，提高芯片性能的同时减小了封装体积，并且本发明利用功能芯片的背面空间挖腔并埋入控制芯片，可以有效提高三维方向封装的集成度。The present invention has at least the following beneficial effects: The present invention provides a method and a packaging structure for constructing a memory chip packaging structure, wherein a TSV structure is constructed on the chip body, and the functional chip and the adapter board in the traditional packaging structure are combined into one, thereby improving the chip performance while reducing the packaging volume, and the present invention utilizes the back space of the functional chip to dig a cavity and bury the control chip, which can effectively improve the integration of the three-dimensional packaging.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
为进一步阐明本发明的各实施例中具有的及其它的优点和特征，将参考附图来呈现本发明的各实施例的更具体的描述。可以理解，这些附图只描绘本发明的典型实施例，因此将不被认为是对其范围的限制。在附图中，为了清楚明了，相同或相应的部件将用相同或类似的标记表示。To further illustrate the advantages and features of various embodiments of the present invention, a more detailed description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings only depict typical embodiments of the present invention and are therefore not to be considered as limiting the scope thereof. In the accompanying drawings, for clarity, identical or corresponding parts will be represented by identical or similar reference numerals.
图1示出了本发明一个实施例中一个构造存储芯片封装结构的方法的流程示意图。 FIG. 1 is a schematic flow chart showing a method for constructing a memory chip packaging structure in an embodiment of the present invention.
图2-图5示出了本发明一个实施例中一个存储芯片封装结构的构造过程结构图。2 to 5 are structural diagrams showing the construction process of a memory chip packaging structure in one embodiment of the present invention.
图6示出了本发明一个实施例中一个第二芯片的俯视图。FIG. 6 shows a top view of a second chip according to an embodiment of the present invention.
图7示出了本发明一个实施例中一个存储芯片封装结构的示意图。FIG. 7 is a schematic diagram showing a memory chip packaging structure in an embodiment of the present invention.
具体实施方式Detailed ways
应当指出，各附图中的各组件可能为了图解说明而被夸大地示出，而不一定是比例正确的。在各附图中，给相同或功能相同的组件配备了相同的附图标记。It should be noted that the components in the figures may be shown exaggeratedly for the sake of illustration and are not necessarily true to scale. In the figures, identical or functionally identical components are provided with the same reference numerals.
在本发明中，除非特别指出，“布置在…上”、“布置在…上方”以及“布置在…之上”并未排除二者之间存在中间物的情况。此外，“布置在…上或上方”仅仅表示两个部件之间的相对位置关系，而在一定情况下、如在颠倒产品方向后，也可以转换为“布置在…下或下方”，反之亦然。In the present invention, unless otherwise specified, "arranged on...", "arranged above..." and "arranged above..." do not exclude the presence of an intermediate between the two. In addition, "arranged on or above..." merely indicates the relative positional relationship between two components, and in certain circumstances, such as after reversing the product direction, it can also be converted into "arranged below or below...", and vice versa.
在本发明中，各实施例仅仅旨在说明本发明的方案，而不应被理解为限制性的。In the present invention, each embodiment is only intended to illustrate the aspects of the present invention and should not be construed as limiting.
在本发明中，除非特别指出，量词“一个”、“一”并未排除多个元素的场景。In the present invention, unless otherwise specified, the quantifiers "a", "an" and "an" do not exclude the presence of a plurality of elements.
在此还应当指出，在本发明的实施例中，为清楚、简单起见，可能示出了仅仅一部分部件或组件，但是本领域的普通技术人员能够理解，在本发明的教导下，可根据具体场景需要添加所需的部件或组件。另外，除非另行说明，本发明的不同实施例中的特征可以相互组合。例如，可以用第二实施例中的某特征替换第一实施例中相对应或功能相同或相似的特征，所得到的实施例同样落入本申请的公开范围或记载范围。It should also be noted that in the embodiments of the present invention, for the sake of clarity and simplicity, only a portion of the parts or components may be shown, but those of ordinary skill in the art will understand that under the teachings of the present invention, the required parts or components may be added according to the needs of the specific scenario. In addition, unless otherwise specified, the features in different embodiments of the present invention may be combined with each other. For example, a feature in the second embodiment may be used to replace a corresponding or functionally identical or similar feature in the first embodiment, and the resulting embodiment also falls within the disclosure scope or recorded scope of the present application.
在此还应当指出，在本发明的范围内，“相同”、“相等”、“等于”等措辞并不意味着二者数值绝对相等，而是允许一定的合理误差，也就是说，所述措辞也涵盖了“基本上相同”、“基本上相等”、“基本上等于”。以此类推，在本发明中，表方向的术语“垂直于”、“平行于”等等同样涵盖了“基本上垂直于”、“基本上平行于”的含义。It should also be noted that within the scope of the present invention, the terms "same", "equal", "equal to" and the like do not mean that the values of the two are absolutely equal, but allow a certain reasonable error, that is, the terms also cover "substantially the same", "substantially equal", "substantially equal to". By analogy, in the present invention, the terms "perpendicular to", "parallel to" and the like indicating directions also cover the meanings of "substantially perpendicular to" and "substantially parallel to".
另外，本发明的各方法的步骤的编号并未限定所述方法步骤的执行顺序。除非特别指出，各方法步骤可以以不同顺序执行。In addition, the numbering of the steps of the methods of the present invention does not limit the execution order of the method steps. Unless otherwise specified, the method steps can be executed in different orders.
下面结合具体实施方式参考附图进一步阐述本发明。 The present invention will be further described below in conjunction with specific embodiments with reference to the accompanying drawings.
图1示出了本发明一个实施例中一个存储芯片封装结构的构造方法的流程示意图。如图1所示，该方法可以包括下列步骤：FIG1 is a schematic flow chart showing a method for constructing a memory chip packaging structure in an embodiment of the present invention. As shown in FIG1 , the method may include the following steps:
步骤101、提供第一芯片201。Step 101: Provide a first chip 201.
步骤102、在所述第一芯片201的第一面上构造凹槽301。Step 102 : constructing a groove 301 on the first surface of the first chip 201 .
步骤103、在所述凹槽301处布置控制芯片401。Step 103 , arranging a control chip 401 in the groove 301 .
步骤104、提供第二芯片501，其中所述第二芯片501上设置有存储区域502。Step 104 : providing a second chip 501 , wherein a storage area 502 is provided on the second chip 501 .
步骤105、将所述第二芯片501的第一面堆叠在所述第一芯片201的第二面上。Step 105 : stacking the first surface of the second chip 501 on the second surface of the first chip 201 .
图2-图5示出了本发明一个实施例中一个存储芯片封装结构的构造过程结构图。下面结合图2-图5具体说明所述构造方法的步骤。Figures 2 to 5 show the structural diagrams of the construction process of a memory chip packaging structure in one embodiment of the present invention. The steps of the construction method are described in detail below in conjunction with Figures 2 to 5.
如图2所示，在步骤101中可以提供第一芯片201，其中所述第一芯片201的第二面上设置有第一存储区域(图中未示出)，在所述第一存储区域的周围可以设置有第一硅通孔202(TSV)，所述第一硅通孔202可以贯通所述第一芯片201的第一面和第二面。As shown in FIG. 2 , in step 101 , a first chip 201 may be provided, wherein a first storage area (not shown in the figure) is provided on the second surface of the first chip 201 , and a first through silicon via 202 (TSV) may be provided around the first storage area, and the first through silicon via 202 may pass through the first surface and the second surface of the first chip 201 .
如图3所示，在步骤102中可以通过光刻或者刻蚀等工艺在所述第一芯片201的第一面上构造凹槽301。As shown in FIG. 3 , in step 102 , a groove 301 may be formed on the first surface of the first chip 201 by photolithography or etching.
如图4所示，在步骤103中可以在所述凹槽301处布置控制芯片401。通过利用所述第一芯片201的背面空间挖腔埋入芯片401片，可以有效提高三维方向封装的集成度。As shown in Fig. 4, in step 103, a control chip 401 may be arranged in the groove 301. By utilizing the back space of the first chip 201 to dig a cavity and embed the chip 401, the integration of three-dimensional packaging can be effectively improved.
如图5所示，在步骤104中可以提供第二芯片501，其中所述第二芯片501上设置有第二存储区域503，并且在所述第二存储区域503的周围设置有第二硅通孔502。图6示出了本发明一个实施例中一个第二芯片501的俯视图，如图6所示，所述第二芯片501可以包括多个第二存储区域503，所述第二存储区域503的数量可以大于等于4。As shown in FIG5 , a second chip 501 may be provided in step 104, wherein a second storage area 503 is provided on the second chip 501, and a second through silicon via 502 is provided around the second storage area 503. FIG6 shows a top view of a second chip 501 in an embodiment of the present invention, and as shown in FIG6 , the second chip 501 may include a plurality of second storage areas 503, and the number of the second storage areas 503 may be greater than or equal to 4.
图7示出了本发明一个实施例中一个存储芯片封装结构的示意图。在步骤105中可以将所述第二芯片501堆叠在所述第一芯片201上以形成图7所示的封装结构，其中可以将多个所述第二芯片501相互堆叠后再堆叠至所述第一芯片201上，在堆叠的过程中，所述第一芯片201和所述第二芯片可以通过所述第一硅通孔202以及第二硅通孔502相互连接。FIG7 shows a schematic diagram of a memory chip packaging structure in an embodiment of the present invention. In step 105, the second chip 501 may be stacked on the first chip 201 to form the packaging structure shown in FIG7, wherein a plurality of the second chips 501 may be stacked on each other and then stacked on the first chip 201. During the stacking process, the first chip 201 and the second chip may be connected to each other through the first through silicon via 202 and the second through silicon via 502.
如图7所示，所述存储芯片封装结构可以包括： As shown in FIG. 7 , the memory chip packaging structure may include:
第一芯片201，其中所述第一芯片201的第一面上设置有凹槽301，并且在所述凹槽301处布置有控制芯片401；A first chip 201, wherein a groove 301 is provided on a first surface of the first chip 201, and a control chip 401 is arranged in the groove 301;
多个第二芯片501，其包括存储区域，其中多个所述第二芯片501相互堆叠并且堆叠在所述第一芯片201上，其中所述第一芯片201与所述多个第二芯片501通过第一硅通孔202和第二硅通孔502相互连接。A plurality of second chips 501 including a storage area, wherein the plurality of second chips 501 are stacked on each other and on the first chip 201 , wherein the first chip 201 and the plurality of second chips 501 are connected to each other via first through silicon vias 202 and second through silicon vias 502 .
尽管上文描述了本发明的各实施例，但是，应该理解，它们只是作为示例来呈现的，而不作为限制。对于相关领域的技术人员显而易见的是，可以对其做出各种组合、变型和改变而不背离本发明的精神和范围。因此，此处所公开的本发明的宽度和范围不应被上述所公开的示例性实施例所限制，而应当仅根据所附权利要求书及其等同替换来定义。 Although various embodiments of the present invention are described above, it should be understood that they are presented as examples only and not as limitations. It is obvious to those skilled in the relevant art that various combinations, modifications and changes can be made thereto without departing from the spirit and scope of the present invention. Therefore, the breadth and scope of the present invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should only be defined according to the attached claims and their equivalents.

Claims (10)

  1. 一种构造存储芯片封装结构的方法，其特征在于，包括下列步骤：A method for constructing a memory chip packaging structure, characterized in that it includes the following steps:
    提供第一芯片；providing a first chip;
    在所述第一芯片的第一面上构造凹槽；constructing a groove on the first surface of the first chip;
    在所述凹槽处布置控制芯片；Arranging a control chip in the groove;
    提供第二芯片，其中所述第二芯片上设置有存储区域；以及providing a second chip, wherein a storage area is disposed on the second chip; and
    将所述第二芯片的第一面堆叠在所述第一芯片的第二面上。The first side of the second chip is stacked on the second side of the first chip.
  2. 根据权利要求1所述的构造存储芯片封装结构的方法，其特征在于，还包括：The method for constructing a memory chip packaging structure according to claim 1, further comprising:
    在所述第一芯片上构造第一硅通孔；constructing a first through silicon via on the first chip;
    在所述第二芯片上构造第二硅通孔；以及constructing a second through silicon via on the second chip; and
    在将所述第二芯片堆叠在所述第一芯片的上时将所述第二硅通孔与所述第一硅通孔连接。The second through silicon via is connected to the first through silicon via when the second chip is stacked on the first chip.
  3. 根据权利要求1所述的构造存储芯片封装结构的方法，其特征在于，所述第二芯片包括一个或者多个存储区域。The method for constructing a memory chip packaging structure according to claim 1, wherein the second chip includes one or more storage areas.
  4. 根据权利要求3所述的构造存储芯片封装结构的方法，其特征在于，所述存储区域的数量大于等于4。The method for constructing a memory chip packaging structure according to claim 3, wherein the number of the storage areas is greater than or equal to 4.
  5. 根据权利要求1所述的构造存储芯片封装结构的方法，其特征在于，提供多个所述第二芯片，其中将多个所述第二芯片相互堆叠。The method for constructing a memory chip packaging structure according to claim 1 is characterized in that a plurality of the second chips are provided, wherein the plurality of the second chips are stacked on each other.
  6. 一种存储芯片封装结构，其特征在于，根据权利要求1-5之一的方法进行构造，该结构包括：A memory chip packaging structure, characterized in that it is constructed according to the method of any one of claims 1 to 5, and comprises:
    第一芯片，其中所述第一芯片的第一面上设置有凹槽，并且在所述凹槽处布置有控制芯片；A first chip, wherein a groove is provided on a first surface of the first chip, and a control chip is arranged at the groove;
    第二芯片，其包括存储区域，其中所述第二芯片的第一面堆叠在所述第一芯片的第二面上。A second chip includes a storage area, wherein a first side of the second chip is stacked on a second side of the first chip.
  7. 根据权利要求6所述的存储芯片封装结构，其特征在于，所述第一芯片还包括第一硅通孔，所述第二芯片还包括第二硅通孔，其中所述第一硅通孔与所述第二硅通孔连接。The memory chip packaging structure according to claim 6 is characterized in that the first chip further includes a first through silicon via, and the second chip further includes a second through silicon via, wherein the first through silicon via is connected to the second through silicon via.
  8. 根据权利要求6所述的存储芯片封装结构，其特征在于，所述第二芯片包括一个或者多个存储区域。The memory chip packaging structure according to claim 6 is characterized in that the second chip includes one or more storage areas.
  9. 根据权利要求8所述的存储芯片封装结构，其特征在于，所述存 储区域的数量大于等于4.The memory chip packaging structure according to claim 8 is characterized in that The number of storage areas is greater than or equal to 4.
  10. 根据权利要求9所述的存储芯片封装结构，其特征在于，包括：The memory chip packaging structure according to claim 9, characterized in that it comprises:
    多个第二芯片，其中多个所述第二芯片相互堆叠。 A plurality of second chips, wherein the plurality of second chips are stacked on each other.
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