CN202384323U - Semiconductor packaging structure - Google Patents
Semiconductor packaging structure Download PDFInfo
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- CN202384323U CN202384323U CN2011205223281U CN201120522328U CN202384323U CN 202384323 U CN202384323 U CN 202384323U CN 2011205223281 U CN2011205223281 U CN 2011205223281U CN 201120522328 U CN201120522328 U CN 201120522328U CN 202384323 U CN202384323 U CN 202384323U
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
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- H—ELECTRICITY
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
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Abstract
The utility model discloses a semiconductor packaging structure, comprising a chip, an insulating layer, a first re-routing layer, an insulating basic layer and a second re-routing layer, wherein the insulating layer is located on the periphery of the chip and comprises a plurality of first electric conducting holes; the first re-routing layer comprises a plurality of first re-routing welding cushions connected with a plurality of connection cushions of the chip; the insulating basic layer comprises a plurality of radiation conducting holes and a plurality of second electric conducting holes; and the second re-routing layer is formed outside the insulating basic layer and has a radiation cushion and a plurality of second re-routing welding cushions. According to the utility model, the radiation conducting hole is directly contacted with the back face of the chip so as to increase radiation efficiency of the chip; in addition, another packaging structure can be also stacked by the second re-routing layer outside of the insulating basic layer so as to improve stacking applicability of a wafer-grade packaging structure.
Description
Technical field
The utility model relates to a kind of semiconductor packaging structure, particularly relevant for the reroute semiconductor packaging structure of layer of a kind of via and two-sided of dispelling the heat.
Background technology
Now; The semiconductor packages industry is in order to satisfy the demand of various high-density packages; Develop the packaging structure that various different types gradually, and wherein various system in package (system in package, SIP) design concept is usually used in framework high-density packages structure; The said system encapsulation can be further divided into multi-chip module (multi chip module again; MCM), stacked package body on the packaging body (package on package, stacked package body POP) and in the packaging body (package in package, PIP) etc.In addition; The design concept that produces in order to dwindle the packaging structure volume is also arranged; Wafer-grade packaging structure (wafer level package for example; WLP), chip size packages structure (chip scale package, CSP) and encapsulation constitution without external pin (quad-flat no-lead package, QFN) etc.
For instance; Please with reference to shown in Figure 1; It discloses a kind of existing wafer-grade packaging structure (WLP), its comprise a chip 11, an insulating barrier 12, reroute layer (re-distributed layer, RDL) 13, several projections (bumps) 14, an insulation basal layer 15 and a copper foil layer 16.Said insulating barrier 12 around be positioned at said chip 11 around, and process by insulating material such as epoxy resin usually.One surface (like the upper surface) alternated of said chip 11 and insulating barrier 12 has several layers insulating barrier and line layer, with the said layer 13 that reroutes of common formation.The said layer 13 that reroutes has several heavy distribution weld pads 131, and the purpose of said heavy distribution weld pad 131 is in order to several connection pad positions on an active surface of rearranging said chip 11 and enlarges its connection pad spacing.Said projection 14 is formed on the said heavy distribution weld pad 131, with the I/O end as signal, power supply or ground connection.Said insulation basal layer 15 is the semi-solid preparation pressing sheets (prepreg) that comprise insulating material such as epoxy resin and glass fiber.When assembling, said copper foil layer 16 is to be fitted in said insulation basal layer 15 outsides in advance, then through an adhesion coating 17 said insulation basal layer 15 and copper foil layer 16 is combined on another surface (like upper surface) of said chip 11 and insulating barrier 12 again.
In above-mentioned existing wafer-grade packaging structure, said insulation basal layer 15 reaches said copper foil layer 16 in order to being dispelled the heat in the back side of said chip 11 in order to increase the structural strength of said chip 11 and insulating barrier 12.Yet because said copper foil layer 16 is to dispel the heat through the said insulation basal layer 15 indirect back sides to said chip 11, therefore not only its radiating efficiency is not good, and said insulation basal layer 15 be heated for a long time after also warpage (warpage) distortion easily.The result; Possibly cause the gap that produces hollow between said insulation basal layer 15, adhesion coating 17 and the chip 11; Thereby cause the heat energy at said chip 11 back sides effectively outwards to get rid of, and then burn said chip 11, and significantly influence the reliability and the useful life of encapsulating products.In addition, said copper foil layer 16 only is used for heat radiation, makes said wafer-grade packaging structure can't pile up in this side with said copper foil layer 16 again and combines other packaging structures, to use as system in package (SIP).
So, be necessary to provide a kind of semiconductor packaging structure, to solve the existing in prior technology problem.
The utility model content
In view of this, the utility model provides a kind of semiconductor packaging structure, and is not good and can't pile up the technical problem of application to solve the existing radiating efficiency of existing wafer-grade packaging structure technology.
The main purpose of the utility model is to provide a kind of semiconductor packaging structure; Wherein during making insulation basal layer; Zone at the inner corresponding chip of insulation basal layer further makes the heat radiation via; And in the further hole that electrically conducts that makes, the zone of the inner corresponding insulating barrier of insulation basal layer; Make the hole that electrically conducts be electrically connected to second of the insulation basal layer outside layer that reroutes simultaneously; So not only can utilize the direct contact chip of the heat radiation via back side to come significantly to improve radiating efficiency and reliable operation degree thereof, and can utilize second of the insulation basal layer outside layer that reroutes to pile up other packaging structures of combination, with the application of piling up of increase wafer-grade packaging structure chip.
For reaching the aforementioned purpose of the utility model, the utility model provides a kind of semiconductor packaging structure, and wherein said semiconductor packaging structure comprises:
One chip has an active surface and a back side, and said active surface is provided with several connection pads;
One insulating barrier is positioned at the periphery of said chip, and has a first surface and a second surface, and has several first holes that electrically conducts in the said insulating barrier;
One first layer that reroutes is formed on the first surface of active surface and said insulating barrier of said chip, and has several first weld pads that heavily distribute and connect the connection pad of said chip;
One insulation basal layer; Be combined on the second surface of the back side and said insulating barrier of said chip; And has several heat radiation vias and several second hole that electrically conducts in the said insulation basal layer; Said heat radiation via contacts the back side of said chip, said second corresponding said first hole that electrically conducts that connects, hole that electrically conducts; And
One second layer that reroutes is formed on the outer surface of said insulation basal layer, and has a cooling pad and several second weld pad that heavily distributes, and said cooling pad connects said heat radiation via, and said second weld pad that heavily distributes connects said second hole that electrically conducts.
In an embodiment of the utility model, said first hole that electrically conducts is the several column-like projection blocks that are pre-formed on said insulation basal layer.
In an embodiment of the utility model, the back side of said chip and the second surface of said insulating barrier are to combine said insulation basal layer through an adhesion layer.
In an embodiment of the utility model, said insulating barrier is by forming behind semi-solid preparation pressing sheet (prepreg) baking-curing that comprises epoxy resin and glass fiber.
In an embodiment of the utility model, said insulation basal layer is by forming behind the semi-solid preparation pressing sheet baking-curing that comprises epoxy resin and glass fiber.
In an embodiment of the utility model, said first heavily distributes is combined with several projections on the weld pad in addition.
In an embodiment of the utility model, said second heavily distributes is combined with additional encapsulation structure on the weld pad, for example the wafer-level packaging body (wafer level package, WLP), routing chip packing-body or Flip-Chip Using body.
In an embodiment of the utility model, said second heavily distributes is combined with at least one additional chips on the weld pad, for example flip-chip (flip chip).
In an embodiment of the utility model, said second heavily distributes is combined with at least one additional passive element (passive element) on the weld pad, for example resistive element, inductance element or capacity cell etc.
In an embodiment of the utility model, said second heavily distributes is combined with at least one extra active element (active element) on the weld pad, for example transistor (transistor), diode (diode) or oscillator (oscillator) etc.
In addition, the utility model provides a kind of semiconductor packaging structure, and wherein said semiconductor packaging structure comprises:
One chip has an active surface and a back side, and said active surface is provided with several connection pads;
One insulating barrier is positioned at the periphery of said chip, and has a first surface and a second surface, and has several first holes that electrically conducts in the said insulating barrier;
One first layer that reroutes is formed on the first surface of active surface and said insulating barrier of said chip, and has several first weld pads that heavily distribute and connect the connection pad of said chip;
One insulation basal layer is combined on the second surface of the back side and said insulating barrier of said chip, and has several heat radiation vias in the said insulation basal layer, and said heat radiation via contacts the back side of said chip; And
One cooling pad is formed on the outer surface of said insulation basal layer, and said cooling pad connects said heat radiation via.
Description of drawings
Fig. 1 is the sketch map of an existing wafer-grade packaging structure (WLP).
Fig. 2 A, 2B, 2C and 2D are the schematic flow sheets of each step of manufacturing approach of the utility model first embodiment semiconductor packaging structure.
Fig. 3 A, 3B, 3C and 3D are the schematic flow sheets of each step of manufacturing approach of the utility model second embodiment semiconductor packaging structure.
Embodiment
For making the utility model above-mentioned purpose, characteristic and advantage more obviously understandable, hereinafter is special lifts the utility model preferred embodiment, and conjunction with figs., elaborates as follows.Moreover, the direction term that the utility model is mentioned, for example " on ", D score, " preceding ", " back ", " left side ", " right side ", " interior ", " outward ", " side " etc., only be direction with reference to annexed drawings.Therefore, the direction term of use is in order to explanation and understands the utility model, but not in order to restriction the utility model.
Please with reference to shown in Fig. 2 A, 2B, 2C and the 2D; The sketch map of each step of manufacturing approach of the semiconductor packaging structure of its announcement the utility model first embodiment; The utility model will utilize Fig. 2 A to 2D to specify the detailed processed process of first each step of embodiment one by one in hereinafter, and detail structure, assembled relation and the operation principles thereof of each element.
Please with reference to shown in Fig. 2 A; The manufacturing approach of the semiconductor packaging structure of the utility model first embodiment at first is: prefabricated respectively and prepare a chip 21, an insulating barrier 22, an insulation basal layer 23 and a passivation layer (passivation) 24, and then pile up assembling.In this step, said chip 21 is formed by Silicon Wafer cutting, and said chip 21 has up a back side down, active surface and, and said active surface also is provided with several connection pads 211.Said insulating barrier 22 is a semi-solid preparation pressing sheet (prepreg) or other organic dielectric materials layers that comprise epoxy resin and glass fiber, ABF for example, and in case of necessity, the upper and lower surface of said insulating barrier 22 can have Copper Foil.Said insulating barrier 22 is dug in advance has an opening 221 and several through holes 222, and said opening 221 is corresponding to the position of said chip 21.
Moreover; Said insulation basal layer 23 is by a standard copper foil substrate Copper Foil on its two surfaces to be carried out a kind of composite bed after etched pattern dissolves circuit, and it comprises several heat radiation vias 231, several second electrically conduct hole 232, a cooling pad 233, several second heavily distribute weld pad 234, several weld pads 235 and several column-like projection blocks 236.Said heat radiation via 231 and second hole 232 that electrically conducts is formed on said insulation basal layer 23 inside, and both can carry out machinery to said insulation basal layer 23 or laser drill is electroplated and is processed into boring more in advance its.The position of said heat radiation via 231 is corresponding to said chip 21, and said second electrically conducts the position in hole 232 corresponding to the through hole 222 of said insulating barrier 22.Said cooling pad 233 and second weld pad 234 that heavily distributes carries out etched patternization by the Copper Foil of the outer surface (lower surface) of said insulation basal layer 23 and is processed into; Said cooling pad 233 connects the bottom of said heat radiation via 231, said second heavily distribute weld pad 234 connect said second electrically conduct hole 232 the bottom.Said cooling pad 233 and second heavily distribute weld pad 234 can close be called one second reroute the layer (RDL) 237.
In addition; Said weld pad 235 carries out etched patternization by the Copper Foil of the inner surface (upper surface) of said insulation basal layer 23 and is processed into; Said insulation basal layer 23 can utilize resist exposure to develop and etch the exposed said weld pad 235 of window; Follow a thickness nickel dam and a bronze medal layer as thin as a wafer on the first vapor deposition, re-plating subsequently forms said column-like projection block 236, and said column-like projection block 236 can be copper post projection or nickel post projection.The position of said column-like projection block 236 is corresponding to the through hole 222 of said insulating barrier 22.During the Copper Foil of the inner surface (upper surface) of said insulation basal layer 23 carry out etched patternization; Also can form the top of said heat radiation via 231, therefore the top of said heat radiation via 231 also can protrude from the inner surface (upper surface) of said insulation basal layer 23.In addition, said passivation layer 24 can be selected from dry film (dry film) or other insulation material layers that photoresist (photo-resist) is processed.
When piling up the said chip of assembling 21, insulating barrier 22, insulation basal layer 23 and passivation layer 24; At first coat an adhesion coating 25 at the inner surface (upper surface) of said insulation basal layer 23; Then said chip 21 is placed on the top of said adhesion coating 25 and said heat radiation via 231 back side of the said chip 21 of the preferred directly contact in the top of said heat radiation via 231.Then, said insulating barrier 22 and passivation layer 24 are stacked on the inner surface (upper surface) of said insulation basal layer 23.At this moment, said chip 21 embeds in the opening 221 of said insulating barrier 22, and 236 of said column-like projection blocks insert in the through hole 222 of said insulating barriers 22, and wherein said column-like projection block and through hole 222 can close and be called first hole 223 (shown in Fig. 2 B) that electrically conducts.24 of said passivation layers are fitted on the active surface of upper surface and said chip 21 of said insulating barrier 22.In another embodiment, said passivation layer 24 also can be on the active surface of mode with liquid insulating material (like photoresist) the coating upper surface and the said chip 21 that are formed on said insulating barrier 22.
Please with reference to shown in Fig. 2 B and the 2C; The manufacturing approach of the semiconductor packaging structure of the utility model first embodiment then is: said passivation layer 24 is carried out laser or machine drilling; And increase layer and form heavily distribute a circuit 26 and a solder mask 27, then form several projections 28 again.In this step, said passivation layer 24 forms several windows 241 after laser or machine drilling, said window 241 exposed said first the electrically conduct top in hole 223 and the connection pad 211 of said chip 21.Said heavy distribution circuit 26 can be to utilize resist exposure to develop to etch window, removes photoresist after electroplating again and is processed to form.Said heavy distribution circuit 26 has several several first weld pad 261 that heavily distributes, said first connection pad 211 of weld pad 261 through the indirect said chip 21 of electric connection of said heavy distribution circuit 26 that heavily distribute.Said first heavily distribute weld pad 261 purpose be in order to the connection pad position of rearranging said chip 21 and enlarge its connection pad spacing.Said solder mask 27 can be photoresist or printing ink, and it has several openings 271, with exposed said first weld pad 261 that heavily distributes.28 of said projections can be tin projection, golden projection, copper post projection or nickel post projection, and said projection 28 is combined in said first and heavily distributes on the weld pad 261, with the I/O end as signal, power supply or ground connection.Said passivation layer 24, heavily distribute circuit 26 and solder mask 27 can close and be called one first layer (RDL) 29 that reroute.After accomplishing above-mentioned steps, can accomplish the semiconductor packaging structure 200 of a wafer scale basically.
Shown in Fig. 2 C, the semiconductor packaging structure 200 of said wafer scale comprises: a chip 21, an insulating barrier 22, one first layer 29, several projections 28, insulation basal layers 23, one second layer 237 that reroutes that reroutes.Said chip 21 has up a back side down, active surface and, and said active surface is provided with several connection pads 211.Said insulating barrier 22 is positioned at the periphery of said chip 21, and has up first surface and a second surface down, and has several first holes 223 that electrically conducts in the said insulating barrier 22.Said first layer 29 that reroutes is formed on the first surface of active surface and said insulating barrier 22 of said chip 21, and has several first connection pad 211 of weld pad 261 through the said chip 21 of said heavy distribution circuit 26 connections that heavily distribute.Said first heavily distributes is combined with said projection 28 on the weld pad 261 in addition.Said insulation basal layer 23 is combined on the second surface of the back side and said insulating barrier 22 of said chip 21; And has several heat radiation vias 231 and several second hole 232 that electrically conducts in the said insulation basal layer 23; The top of said heat radiation via 231 contacts the back side of said chip 21, said second corresponding said first hole 223 that electrically conducts that connects, hole 232 that electrically conducts.Said second layer 237 that reroutes is formed on down the outer surface of said insulation basal layer 23; And has a cooling pad 233 and several second weld pad 234 that heavily distributes; Said cooling pad 233 connects said heat radiation via 231, and said second weld pad 234 that heavily distributes connects said second hole 232 that electrically conducts.
Please with reference to shown in Fig. 2 D; The manufacturing approach of the semiconductor packaging structure of the utility model first embodiment then is: said semiconductor packaging structure 200 is inverted; And pile up and combine another additional encapsulation structure 300 by said second weld pad 234 that heavily distributes, to constitute the framework of a system in package (SIP).In this step, said additional encapsulation structure 300 for example is selected from another wafer-level packaging body, and (wafer level package WLP), routing chip packing-body or Flip-Chip Using body, but is not limited to this.Said additional encapsulation structure 300 itself has several projections 301, can supply solder bond in second of said semiconductor packaging structure 200 weld pad 234 that heavily distributes.When reality is used; Said projection 301, second heavily distribute weld pad 234, second electrically conduct hole 232, first electrically conduct hole 223, heavily the circuit 26, first that distributes distributes heavily that weld pad 261 and projection 28 are common to constitute the path that electrically conducts, and can transmit power supply, signal or as the ground connection purposes to said additional encapsulation structure 300.On the other hand, the chip 21 of said semiconductor packaging structure 200 also distributes heavily through said connection pad 211 and different heavily distribution circuits 26, first that weld pad 261 and projection 28 transmit power supply, signal or as the ground connection purposes.Moreover; The top of said heat radiation via 231 contacts the back side of said chip 21; And the bottom of said heat radiation via 231 connects said cooling pad 233, dispels the heat so the heat energy that can directly said chip 21 be produced is delivered to the outer surface (upper surface of Fig. 2 D) of said semiconductor packaging structure 200 fast.
Please with reference to shown in Fig. 3 A, 3B, 3C and the 3D; The semiconductor packaging structure of the utility model second embodiment and manufacturing approach are similar in appearance to the utility model first embodiment; And roughly continue to use similar elements title and figure number; But the difference characteristic of the manufacturing approach of the second embodiment semiconductor packaging structure is: said second embodiment is prefabricated respectively and prepare a chip 21, an insulating barrier 22, an insulation basal layer 23 and a passivation layer 24 in the step of Fig. 3 A; And then pile up assembling, but said insulation basal layer 23 does not form weld pad 235 and the column-like projection block 236 of Fig. 2 A, and said insulating barrier 22 does not form the through hole 222 of Fig. 2 A simultaneously.Moreover said second embodiment accomplishes at said chip 21, insulating barrier 22, insulation basal layer 23 and passivation layer 24 and just stacked structure to be carried out machine drilling in the lump after piling up assembling, to form a through hole 201 in the step of Fig. 3 B.Subsequently, said second embodiment just electroplates said through hole 201 in the step of Fig. 3 C, in said insulating barrier 22 and insulation basal layer 23, to form said first hole 232 that electrically conducts, hole 223 and second that electrically conducts respectively.Other processing and manufacturing flow process details that Fig. 3 A to 3C does not disclose are partly then basic identical in Fig. 2 A to 2C, so give detailed description no longer in addition in this.
Make the semiconductor packaging structure 200 of a wafer scale at Fig. 3 C after; At last; Said second embodiment can be inverted said semiconductor packaging structure 200 in the step of Fig. 3 D, and is piled up and combined at least one additional chips 400,500 by said second weld pad 234 that heavily distributes; Flip-chip (flip chip) for example is to constitute the framework of a system in package (SIP).In this step, said additional chips 400,500 for example is selected from flip-chip (flip chip), but is not limited to this.Said additional chips 400,500 itself has several projections 401,501, can supply solder bond in second of said semiconductor packaging structure 200 weld pad 234 that heavily distributes.When reality is used; Said projection 401 or 501, second heavily distribute weld pad 234, second electrically conduct hole 232, first electrically conduct hole 223, heavily the circuit 26, first that distributes distributes heavily that weld pad 261 and projection 28 are common to constitute the path that electrically conducts, and can transmit power supply, signal or as the ground connection purposes to said additional chips 400,500.On the other hand, the chip 21 of said semiconductor packaging structure 200 also distributes heavily through said connection pad 211 and different heavily distribution circuits 26, first that weld pad 261 and projection 28 transmit power supply, signal or as the ground connection purposes.Moreover; The top of said heat radiation via 231 contacts the back side of said chip 21; And the bottom of said heat radiation via 231 connects said cooling pad 233, dispels the heat so the heat energy that can directly said chip 21 be produced is delivered to the outer surface (upper surface of Fig. 3 D) of said semiconductor packaging structure 200 fast.
On the other hand, second of said semiconductor packaging structure 200 weld pad 234 that heavily distributes also can be used in addition piling up and combines at least one additional passive element (passive element) or at least one extra active element (active element).Said additional passive element for example is resistive element, inductance element or capacity cell etc.Said extra active element for example is transistor (transistor), diode (diode) or oscillator (oscillator) etc.In case of necessity; Second of said semiconductor packaging structure 200 weld pad 234 that heavily distributes also can be used for selecting piling up simultaneously at least two kinds that combine in said additional encapsulation structure 300, additional chips 400,500, additional passive element and the extra active element in addition, to constitute the framework of more complicated system in package (SIP).
As stated; Not good and can't pile up the technical problem of application compared to the existing radiating efficiency of existing wafer-grade packaging structure technology; The semiconductor packaging structure of the utility model of Fig. 2 C, 2D, 3C and 3D is through during making insulation basal layer; Zone at the inner corresponding chip of insulation basal layer further makes the heat radiation via; And in the further hole that electrically conducts that makes, the zone of the inner corresponding insulating barrier of insulation basal layer; Make the hole that electrically conducts be electrically connected to second of the insulation basal layer outside layer that reroutes simultaneously; So not only can utilize the direct contact chip of the heat radiation via back side to come significantly to improve radiating efficiency and reliable operation degree thereof, and can utilize second of the insulation basal layer outside layer that reroutes to pile up other packaging structures of combination, with the application of piling up of increase wafer-grade packaging structure chip.
The utility model is described by above-mentioned related embodiment, yet the foregoing description is merely the example of implementing the utility model.Must be pointed out that disclosed embodiment does not limit the scope of the utility model.On the contrary, being contained in the spirit of claims and the modification and impartial setting of scope includes in the scope of the utility model.
Claims (10)
1. semiconductor packaging structure, it is characterized in that: said semiconductor packaging structure comprises:
One chip has an active surface and a back side, and said active surface is provided with several connection pads;
One insulating barrier is positioned at the periphery of said chip, and has a first surface and a second surface, and has several first holes that electrically conducts in the said insulating barrier;
One first layer that reroutes is formed on the first surface of active surface and said insulating barrier of said chip, and has several first weld pads that heavily distribute and connect the connection pad of said chip;
One insulation basal layer; Be combined on the second surface of the back side and said insulating barrier of said chip; And has several heat radiation vias and several second hole that electrically conducts in the said insulation basal layer; Said heat radiation via contacts the back side of said chip, said second corresponding said first hole that electrically conducts that connects, hole that electrically conducts; And
One second layer that reroutes is formed on the outer surface of said insulation basal layer, and has a cooling pad and several second weld pad that heavily distributes, and said cooling pad connects said heat radiation via, and said second weld pad that heavily distributes connects said second hole that electrically conducts.
2. semiconductor packaging structure as claimed in claim 1 is characterized in that: said first hole that electrically conducts is the several column-like projection blocks that are pre-formed on said insulation basal layer.
3. semiconductor packaging structure as claimed in claim 1 is characterized in that: the back side of said chip and the second surface of said insulating barrier are to combine said insulation basal layer through an adhesion layer.
4. semiconductor packaging structure as claimed in claim 1 is characterized in that: said insulating barrier is a pressing sheet that comprises epoxy resin and glass fiber.
5. semiconductor packaging structure as claimed in claim 1 is characterized in that: said insulation basal layer is a pressing sheet that comprises epoxy resin and glass fiber.
6. semiconductor packaging structure as claimed in claim 1 is characterized in that: said first heavily distributes is combined with several projections on the weld pad in addition.
7. semiconductor packaging structure as claimed in claim 1 is characterized in that: said second heavily distributes is combined with additional encapsulation structure on the weld pad.
8. semiconductor packaging structure as claimed in claim 1 is characterized in that: said second heavily distributes is combined with at least one additional chips on the weld pad.
9. semiconductor packaging structure as claimed in claim 1 is characterized in that: said second heavily distributes is combined with at least one additional passive element or at least one extra active element on the weld pad.
10. semiconductor packaging structure, it is characterized in that: said semiconductor packaging structure comprises:
One chip has an active surface and a back side, and said active surface is provided with several connection pads;
One insulating barrier is positioned at the periphery of said chip, and has a first surface and a second surface, and has several first holes that electrically conducts in the said insulating barrier;
One first layer that reroutes is formed on the first surface of active surface and said insulating barrier of said chip, and has several first weld pads that heavily distribute and connect the connection pad of said chip;
One insulation basal layer is combined on the second surface of the back side and said insulating barrier of said chip, and has several heat radiation vias in the said insulation basal layer, and said heat radiation via contacts the back side of said chip; And
One cooling pad is formed on the outer surface of said insulation basal layer, and said cooling pad connects said heat radiation via.
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| CN2011205223281U CN202384323U (en) | 2011-12-14 | 2011-12-14 | Semiconductor packaging structure |
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| CN2011205223281U CN202384323U (en) | 2011-12-14 | 2011-12-14 | Semiconductor packaging structure |
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| CN202384323U true CN202384323U (en) | 2012-08-15 |
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Granted publication date: 20120815 |