JP5298762B2 - Stacked semiconductor device, manufacturing method of stacked semiconductor device, and semiconductor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem wherein a heat dissipating structure with high efficiency is necessary for stable operations of a multilayer type semiconductor device which has high three-dimensional packaging density. <P>SOLUTION: The multilayer type semiconductor device is constituted by laminating a plurality of semiconductor chips, each having a circuit region, a first bump group electrically connected to elements in the circuit region, and a second bump group forming a pattern enclosing the circuit region and not electrically connected to the elements in the circuit region, by joining at least opposing portions of the first bump group and at least opposing portions of the second bump group together. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a stacked semiconductor device and a method for manufacturing the stacked semiconductor device.

  There is a stacked semiconductor device in which a plurality of semiconductor chips each having an element and a circuit are stacked (see Patent Document 1). By adopting a three-dimensional structure, the stacked semiconductor device can improve the effective mounting density without increasing the mounting area. In addition, it is said that the wiring between the stacked semiconductor chips can be shortened, which contributes to an improvement in operation speed.

  FIG. 19 is a diagram illustrating a typical example of a wafer-to-wafer (W2W) process for stacking wafers. FIGS. 19A to 19F show the state of a partial cross section of the wafer, but all operations are performed simultaneously on the entire wafer.

A transistor circuit 1903 is formed in a Si substrate 1901 having an insulating layer 1902 made of SiO ₂ , Si ₂ N ₄ , polyimide or the like formed on the surface by a known method. Then, Al pads 1904 and 1905 are formed in the insulating layer 1902 (a). Next, holes are formed in the insulating layer 1902 and the Si substrate 1901 by RIE (Reactive-Ion-Etching), and a conductor (for example, Cu) is filled therein. This conductor is used for electrical connection between wafers to be stacked later, and is called TSV (Through Si Via). Note that an insulating film made of SiO ₂ or the like and a barrier metal made of TiN or the like are formed around the TSV 1906 so as to be insulated from the Si substrate 1901, but the illustration is omitted here. (B). Next, bumps 1907 are formed on the exposed portions of TSV 1906 (c). The bump 1907 is made of, for example, SnAgCu.

  Subsequently, the wafers formed as shown in (c) are faced to face each other, and the bumps 1907 are joined together (d). The thickness of the bonded bump 1907 should be twice the thickness of what is formed on one wafer, but since it is pressed during bonding, it is generally slightly thinner. Next, the back surface of one of the two wafers bonded in this way is polished by CMP or the like to expose the TSV 1906 (e). This process is called a thinning process. Three bumps 1907 are newly formed on the exposed surface of TSV 1906, and three wafers are bonded to each other by bonding the bump 1907 of the wafer having the same structure as (c).

Hereinafter, the back surface of the third wafer is polished to expose the TSV 1906, a bump 1907 is newly formed on the surface, and the bump 1907 of the wafer having the same structure as (c) is bonded thereto. Four wafers are bonded together. By repeating this, a stacked semiconductor device having a multi-layer stack is formed.
JP 11-261000 A

  When the three-dimensional mounting density is increased, the density of a circuit or element as a heat source is also increased. For this reason, heat distribution tends to occur inside the laminated structure, and distribution tends to occur in operation stability. In other words, a highly efficient heat dissipation structure is required for stable operation of the stacked semiconductor device.

  In order to solve the above problems, in the first aspect of the present invention, a circuit region, a first bump group electrically connected to an element in the circuit region, and a pattern surrounding the circuit region are formed. A plurality of semiconductor chips each including a second bump group that is not electrically connected to an element in the circuit region are arranged so that at least a part of the first bump group that faces each other and at least the second bump group faces each other. Provided is a stacked semiconductor device in which a part of each other is bonded and stacked.

  Further, in the second aspect, a first bump group electrically connected to the circuit region element and a circuit region element forming a pattern surrounding the circuit region on a semiconductor chip having the circuit region, Is a bump group forming step for providing a second bump group that is not electrically connected, and a plurality of semiconductor chips that have undergone the bump group forming step are stacked, and the first bump groups facing each other and the second bump group facing each other There is provided a manufacturing method of a stacked semiconductor device including a stacking step of bonding together.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

(First embodiment)
There are roughly three types of 3D-LSIs that develop a semiconductor chip on which elements and circuits are formed into a three-dimensional structure. One is “simple chip stack” in which only KGD (Known-Good-Die) is stacked with a low-accuracy die bonder and the semiconductor chips are connected by wire bonding. This is a “package type stacking”. The other is “through electrode side lamination (hereinafter referred to as TSV: Through Si Via lamination)” in which a through electrode between elements is provided on a Si wafer and the wafer or semiconductor chips are directly connected to each other.

  Furthermore, TSV lamination can be classified into the following three methods. That is, a chip-to-chip (C2C) for stacking KGDs, a chip-to-wafer (C2W) for mounting KGD on a wafer, and a wafer-to-wafer (W2W) for directly bonding wafers together.

  In the present embodiment, a process of TSV stacking by C2C is used and will be described below with reference to the drawings.

  FIG. 1 is a front view schematically showing stacked semiconductor chips 100. Inside the semiconductor chip 100 is provided with a circuit region 101 in which elements, wirings and the like constituting the circuit are substantially arranged. A plurality of circuit bumps 102 as first bump groups electrically connected to the elements are formed inside the circuit region 101. These circuit bumps are provided at the tip of the TSV 104 described later.

  A plurality of dummy bumps 103 as second bump groups that are not electrically connected to the elements formed in the circuit region 101 are formed outside the circuit region 101. In the present embodiment, the dummy bump 103 is also provided at the tip of the TSV 104 in the same manner as the circuit bump 102.

  In the illustrated example, both the circuit bumps 102 and the dummy bumps 103 are arranged in a regular matrix, but need not be arranged regularly. Since the circuit bumps formed in the circuit region 101 are formed according to the elements and wirings arranged according to the functions required for the circuit, the arrangement is not always regular. Further, since the dummy bumps 103 are arranged from the viewpoint of heat dissipation and the like as will be described later, they are not particularly required to be aligned. However, as can be seen from the illustrated example, when the distribution density per unit area of the circuit bumps 102 arranged inside the circuit region 101 and the distribution density per unit area of the dummy bumps 103 arranged outside are compared, It is preferable that the dummy bump 103 is larger. This is because such a configuration is preferable in order to efficiently release the heat generated in the circuit region 101 and to enhance the bonding force between the semiconductor chips.

  2 is a cross-sectional view of the semiconductor chip 100 in the vicinity of the end portion of AA shown in FIG. The TSV 104 formed in the circuit region 101 is connected to a transistor circuit 204 as an element through an aluminum thin film wiring 203 and plays a role of electrical connection of the circuit. The TSV 104 is formed by filling a hole (opened by RIE (Reactive-Ion-Etching)) with a conductor (for example, Cu). Around the TSV 104, an insulating film 201 made of SiO2 and a barrier metal 202 made of TiN or the like are formed so as to be insulated from the Si substrate. The insulating film 201 is also continuously formed on the surface of the Si substrate. The circuit bumps 102 are provided at both ends of the TSV 104 and are used for bonding with other stacked semiconductor chips and the like, and play a role as electrical connection wiring.

  The TSV 104 formed outside the circuit region 101 is not connected to the transistor circuit 204 as shown in the figure, and is electrically insulated from elements and wirings in the circuit region 101. Since the TSV 104 is formed in the same process regardless of the inside and outside of the circuit region 101, the TSV 104 outside the circuit region 101 is also formed with an insulating film 201 made of SiO2 and a barrier metal 202 made of TiN or the like around it. ing.

  The dummy bumps 103 are provided at both ends of the TSV 104 outside the circuit region 101 and are used for bonding with other stacked semiconductor chips and the like, and contribute to the heat conduction between the semiconductor chips and the strengthening of the bonding force.

  Both the circuit bump 102 and the dummy bump 103 are formed at the tip of the TSV 104 by the same process. Therefore, it is preferable that the diameter R1 of the circuit bump 102 and the diameter R2 of the dummy bump 103 are the same.

  In addition, since the circuit bumps 102 and the dummy bumps 103 are pressed and bonded to the respective bumps formed on other semiconductor chips facing each other, it is preferable that the contact surfaces are the same plane when contacting each other. If the heights are different, some bumps do not contact each other, and some bumps may be over-pressed. If the circuit bumps 102 are not in contact with each other, the signal will be cut off, and the function itself as a stacked semiconductor device cannot be performed. If the dummy bumps 103 are not in contact with each other, heat conduction is interrupted and heat dissipation is not performed efficiently, or semiconductor chips are peeled off due to insufficient bonding force in the manufacturing process. Conversely, if the bumps are over-pressed, there is a risk that the bumps will be destroyed. Therefore, the height of the tip of both the circuit bump 102 and the dummy bump 103 is H from the surface of the semiconductor chip 100 and is the same height. However, if it is difficult to achieve the same height, it is preferable to make the circuit bumps 102 slightly higher in order to obtain reliable conduction of the signal lines.

  The circuit bumps 102 and the dummy bumps 103 are made of the same material such as SnAgCu.

  Next, the process of stacking the semiconductor chips formed as described above will be described with reference to FIG. FIG. 3 is a conceptual diagram illustrating a semiconductor chip stacking process.

  The stacked semiconductor chip group 300 includes an uppermost semiconductor chip 301, an intermediate semiconductor chip 302, and a lowermost semiconductor chip 303. The number of semiconductor chips 302 on the intermediate surface is not limited to one, and two or more may be stacked. Further, the semiconductor chip 302 on the intermediate surface and the semiconductor chip 303 on the lowermost surface are configured in the same manner as the semiconductor chip 100 described with reference to FIGS.

  The uppermost semiconductor chip 301 is a surface opposite to the intermediate surface facing the semiconductor chip 302 and contacts a heat spreader 401 made of Cu, for example, as will be described later. In the case where the heat spreader 401 is a conductor, the circuit bump 102 serving as an electrical connection wiring cannot be provided on the surface in contact with the heat spreader 401. Therefore, the uppermost semiconductor chip 301 is formed such that the surface on which the transistor circuit 204 is formed faces the semiconductor chip 302 side of the intermediate surface, and the circuit bumps 102 are formed without using the TSV 104. Therefore, as shown in the figure, the circuit bump 102 does not exist on the surface in contact with the heat spreader 401. On the other hand, the dummy bump 103 is preferably formed by using the TSV 104 in the same manner as the dummy bump 103 of the semiconductor chip 100 because it is preferable to positively contact the heat spreader 401 to increase the heat dissipation efficiency.

  Then, the uppermost semiconductor chip 301, the intermediate semiconductor chip 302, and the lowermost semiconductor chip 303 thus prepared are pressed by bringing the circuit bumps 102 facing each other and the dummy bumps 103 contacting each other in the direction of the arrow. And joined together.

  Note that the circuit bumps 102 are joined to each other because electrical connection necessary for functioning as a stacked semiconductor device is performed, so that one circuit bump 102 faces the other circuit bump 102 and the other circuit bump 102 does not exist. It doesn't mean you don't have to. That is, circuit bumps 102 that need to be connected may be connected, and there may be circuit bumps 102 that are not connected. In that sense, it is only necessary that at least some of the circuit bumps 102 are bonded to each other among the plurality of circuit bumps formed on each of the opposing semiconductor chips.

  Similarly, the dummy bumps 103 may be bonded together as long as the expected heat dissipation effect and the effect of strengthening the bonding force can be obtained. In that sense, it is only necessary that at least some of the dummy bumps 103 are bonded to each other among the plurality of dummy bumps 103 formed on each of the opposing semiconductor chips.

  Further, the TSV 104 can be used if the TSV 104 is not directly in contact with the heat spreader 401 by providing an insulating layer on the surface side of the uppermost semiconductor chip 301 that is in contact with the heat spreader 401. With this configuration, the circuit bump 102 on the surface facing the semiconductor chip 302 on the intermediate surface can be formed at the tip of the TSV 104.

  FIG. 4 is a conceptual diagram illustrating a process of stacking the semiconductor chip group 300 formed as described above and other components.

  The heat spreader 401 radiates the heat transmitted through the dummy bumps 103 to the outside. Therefore, the heat spreader 401 is pressed and joined to the dummy bumps 103 provided on the uppermost semiconductor chip 301 formed as described above. The heat spreader 401 uses a material having good heat dissipation characteristics. For example, Cu is preferable.

  Then, the bonded heat spreader 401 and the semiconductor chip group 300 are bonded to the base 402. Specifically, circuit bumps 102 and dummy bumps 103 are provided on the joint surface of the lowermost semiconductor chip 303 constituting the semiconductor chip group 300 with the base 402, and these are pressed against the base 402 in the direction of the arrow. And join. Note that since the base 402 is formed of an insulator, there is no problem even if the circuit bumps 102 come into contact with each other.

  FIG. 5 is a cross-sectional view of the stacked semiconductor device stacked in this manner. A slight gap is generated between each of the heat spreader 401, the semiconductor chip group 300, and the base 402 bonded and laminated as described above. In order to seal such a gap, an underfill 501 made of an organic material is filled. Specifically, the liquid underfill 501 flows from the side of the gap and is solidified. Further, the side is sealed with a mold member 502.

  As shown in the drawing, the underfill 501 is filled in a gap generated when the heat spreader 401, the semiconductor chip group 300, and the base 402 are joined by the circuit bumps 102 and the dummy bumps 103. And the side is sealed with the mold member 502.

  FIG. 6 is a flowchart showing manufacturing steps of the stacked semiconductor device according to the present embodiment, which summarizes the steps described so far.

  First, in step S601, the TSV 104 is formed. More specifically, the hole formed by RIE is filled with a conductor. The TSV 104 is formed by the same process regardless of the inside or outside of the circuit region 101. Next, in step S602, circuit bumps 102 and dummy bumps 103 are formed. Each of these is formed as a plurality of bump groups according to the required number. Further, both the circuit bumps 102 and the dummy bumps 103 are simultaneously formed in a single process. In the present embodiment, a C2C TSV stack is described. However, TSV formation (step S601) and bump group formation (step S602) may be performed in units of wafers before being cut into semiconductor chips. .

  In step S603, the cut semiconductor chips are stacked and bonded together. Specifically, as described with reference to FIG. 3, this is realized by bonding corresponding circuit bumps 102 and corresponding dummy bumps 103 formed on the opposing surfaces. In step S604, the heat spreader 401 and the base 402 are bonded to the semiconductor chip group 300 stacked in this manner so as to be in contact with each of the end faces. Thereafter, in step S605, the gap between the layers is sealed by the underfill 501 and the side is sealed by the mold member 502, and the series of steps is completed.

  Note that the bonding between the semiconductor chip group 300 and the heat spreader 401 is described as being performed by pressing the heat spreader 401 against the dummy bump 103 provided on the uppermost semiconductor chip 301, but is not limited thereto. Since the Si substrate itself has high thermal conductivity, the bonding surface with the heat spreader 401 may be flat without forming the dummy bumps 103 and bonded by an adhesive having high thermal conductivity. In this case, since an underfill having a relatively low thermal conductivity is not interposed between the heat spreader 401 and the uppermost semiconductor chip 301, it can be said that it is preferable when the number of dummy bumps 103 cannot be secured.

  In the above embodiment, the semiconductor chip 100, the uppermost semiconductor chip 301, the intermediate semiconductor chip 302, and the lowermost semiconductor chip 303 are each formed with elements such as TSV104 on a relatively thin substrate. It was explained on the assumption that That is, the thinning process described with reference to FIG. 19 is not required for the semiconductor chip of this embodiment. However, the semiconductor chip group 300 may be stacked using a relatively thick substrate and incorporating a thinning process. In this case, the steps from step S601 to step S603 are slightly changed.

  Specifically, an element such as a transistor circuit 204 is formed on the back surface side of the uppermost semiconductor chip 301, a TSV 104 is formed, and a bump group is formed thereon. On the other hand, elements such as the transistor circuit 204, TSV 104, and bump group are formed on the surface side of the semiconductor chip 302 on the intermediate surface that is bonded to the uppermost semiconductor chip 301. Then, each bump group is bonded, and the uppermost semiconductor chip 301 and the intermediate semiconductor chip 302 are stacked. At this stage, the TSV 104 is not exposed and the bump group is not formed on each surface opposite to the surfaces bonded to each other.

  Then, after bonding, the back surface side of the semiconductor chip 302 on the intermediate surface is polished by CMP or the like to expose the TSV 104. That is, a thinning process is performed on the semiconductor chip 302 on the intermediate surface. Then, a bump group is formed on the exposed TSV 104.

  On the other hand, elements such as the transistor circuit 204, TSV 104, and bump group are formed on the surface side of the lowermost semiconductor chip 303 that is bonded to the intermediate semiconductor chip 302. Then, the bump groups are bonded to each other, and an intermediate semiconductor chip 302 that is already integrated with the uppermost semiconductor chip 301 and a lowermost semiconductor chip 303 are stacked. At this stage, the TSV 104 is not exposed and the bump group is not formed on the back surface of the lowermost semiconductor chip 303 which is the surface opposite to the surface bonded to the intermediate semiconductor chip 302. It is.

  After bonding, the back surface side of the lowermost semiconductor chip 303 is polished by CMP or the like to expose the TSV 104. That is, a thinning process is performed on the lowermost semiconductor chip 303. Then, a bump group is formed on the exposed TSV 104.

  Next, the surface side of the uppermost semiconductor chip 301 is polished by CMP or the like to expose the TSV 104. That is, a thinning process is performed on the uppermost semiconductor chip 301. Then, a bump group is formed on the exposed TSV 104.

  In this way, the semiconductor chip group 300 can be stacked using a relatively thick substrate. Of course, the semiconductor chip 302 on the intermediate surface can be laminated by repeating the thinning process as described above. Further, the above-described method of incorporating the thinning process is not limited to the C2C TSV stack, but may be a W2W TSV stack performed in units of wafers before being cut into semiconductor chips.

  As described above, according to the present embodiment, the heat generated in the stacked structure can be guided to the heat spreader 401 by using the TSV 104 and the dummy bump 103 as a heat dissipation path and released to the outside, so that stable operation of the stacked semiconductor device can be expected. . Further, since the dummy bump 103 is formed in a dot shape at the tip of the TSV, a gap is generated when viewed from the side after joining the layers. When this lateral gap is used, the underfill 501 can be filled by inflow which is relatively easy to work.

  Hereinafter, some embodiments will be described as modifications of the first embodiment. Since the common reference numerals are the same as those of the first embodiment, the description thereof will be omitted, and different parts that characterize the respective embodiments will be described.

(Second Embodiment)
FIG. 7 is a cross-sectional view of the vicinity of the end of the semiconductor chip 100 according to the second embodiment. The front view of the semiconductor chip 100 in the present embodiment is the same as the front view of the semiconductor chip 100 of the first embodiment described with reference to FIG.

  As shown in the figure, in this embodiment, the dummy bump 103 is not formed at the tip of the TSV, but is formed on the insulating film 201 or on the buffer metal 701 provided directly on the Si substrate. The By configuring in this way, the Si substrate itself has high thermal conductivity, so that heat dissipation characteristics according to TSV can be expected, and the effect of shortening the hole formation time by RIE can be obtained.

(Third embodiment)
FIG. 8 is a front view schematically showing a semiconductor chip 800 according to the third embodiment. The arrangement of the circuit area 101, the plurality of circuit bumps 102 (first bump group), and the plurality of dummy bumps 103 (second bump group) is the same as that of the first embodiment, but the metal pattern 801 is provided. Is different from the first embodiment. Specifically, a metal pattern 801 is arranged on the outside so as to close and surround the circuit region 101, and a dummy bump 103 is present thereon.

  FIG. 9 is a cross-sectional view of the semiconductor chip 800 in the vicinity of the end portion of BB shown in FIG. The point that the dummy bump 103 is provided at the tip of the TSV 104 is the same as that of the first embodiment described with reference to FIG. In the present embodiment, in addition to the configuration of FIG. 2, a metal pattern 801 is further provided on each of the upper and lower surfaces so that a plurality of dummy bumps 103 are placed together. The metal pattern is formed, for example, by depositing TiN by PVD (Physical Vapor Deposition).

  With this configuration, by controlling the size of the dummy bumps 103, not only the dummy bumps 103 facing each other but also the adjacent dummy bumps 103 can be bonded together by pressing during bonding. As a result, a plurality of dummy bumps are pressed to form an integral wall between the metal patterns 801 provided on each of the two semiconductor chips 800 facing each other. That is, it can be said that a bonding layer without a gap is formed on the metal pattern 801 after bonding. This bonding layer encloses the circuit region 101 and blocks it from the external space. Therefore, it can be said that it is preferable from the viewpoint of protection of the circuit region 101.

  In the present embodiment, the configuration in which all the dummy bumps 103 are arranged on the metal pattern 801 has been described. However, the present invention is not limited to this. That is, even if some of the dummy bumps 103 are not on the metal pattern 801, the circuit region 101 can be protected if the bonding layer is formed by the dummy bumps 103 on the metal pattern 801.

  In this case, the underfill 501 processed into a sheet shape in advance is arranged inside the metal pattern 801 so that filling can be performed at the time of bonding between layers. Alternatively, filling can be performed at the time of bonding between layers by dropping an underfill 501 into the metal pattern 801 in advance by an inkjet method.

  The metal pattern 801 in the present embodiment is arranged so as to be separated from the outer peripheral portion of the semiconductor chip 800, but by arranging in this way, the metal pattern 801 is obtained when the wafer state is cut from the wafer state to the semiconductor chip state. Not affected by cutting. Therefore, since a certain width of the bonding layer can always be ensured, it can be expected that the expected heat radiation effect is obtained with certainty.

(Fourth embodiment)
FIG. 10 is a cross-sectional view of the vicinity of the end portion of the semiconductor chip 800 according to the fourth embodiment. The front view of the semiconductor chip 800 in the present embodiment is the same as the front view of the semiconductor chip 800 of the third embodiment described with reference to FIG.

  As shown in the figure, in this embodiment, the dummy bump 103 is not formed at the tip of the TSV, but is formed on the insulating film 201 or on the metal pattern 801 provided directly on the Si substrate. The By configuring in this way, the Si substrate itself has high thermal conductivity, so that heat dissipation characteristics according to TSV can be expected, and the effect of shortening the hole formation time by RIE can be obtained.

(Fifth embodiment)
FIG. 11 is a front view schematically showing a semiconductor chip 1100 according to the fifth embodiment. The arrangement of the circuit area 101 and the circuit bump 102 (first bump group) is the same as that of the third embodiment, but the dummy bump layer is integrally formed on the metal pattern 1101 as a dummy bump group (second bump group). The difference from the third embodiment is that 1103 is provided. Similar to the metal pattern 801 in the third embodiment, the metal pattern 1101 is arranged outside so as to close and enclose the circuit region 101.

  FIG. 12 is a cross-sectional view of the semiconductor chip 1100 in the vicinity of the end portion of CC shown in FIG. As shown in the figure, in this embodiment, the dummy bump layer 1103 is formed on the insulating film 201 or on the metal pattern 1101 provided directly on the Si substrate without using TSV. With this configuration, it can be expected that a bonding layer without a gap is reliably formed on the metal pattern 1101 before bonding.

  In addition, the metal pattern 1101 in this embodiment is arranged so as to be separated from the outer peripheral portion of the semiconductor chip 1100. By arranging in this way, the metal pattern 1101 is cut from the wafer state to the semiconductor chip state. It is not affected by the cutting time. Therefore, since a certain width of the dummy bump layer 1103 can always be ensured, it can be expected that the expected heat dissipation effect is obtained with certainty.

(Sixth embodiment)
FIG. 13 is a front view schematically showing a semiconductor chip 1100 according to the sixth embodiment. The arrangement of the circuit region 101 and the circuit bump 102 (first bump group) is the same as that of the fifth embodiment. Further, the point that the dummy bump layer 1303 is integrally provided as a dummy bump group (second bump group) on the metal pattern 1301 is the same as that of the fifth embodiment, but the shape of the metal pattern 1301 in this embodiment is the same. Different from that of the fifth embodiment. Specifically, the circuit area 101 is not completely closed and surrounded, but the pattern is cut off at several places (four places in the figure). With this configuration, after joining the semiconductor chips, the cut portion becomes a gap communicating with the circuit region, and the underfill 501 can be filled by inflow which is relatively easy. At the same time, since most of the circuit area 101 is surrounded by the dummy bump layer 1303, protection of the circuit area 101 according to the completely surrounded structure can be expected.

(Seventh embodiment)
FIG. 14 is a front view schematically showing a semiconductor chip 1400 according to the seventh embodiment. The point that the dummy bump layer 1403 is integrally provided as a dummy bump group (second bump group) on the metal pattern 1401 is the same as that of the fifth embodiment, but the position of the metal pattern 1401 in this embodiment is the fifth. It differs from that of the embodiment. In the fifth embodiment, the metal pattern 1101 is disposed away from the outer periphery of the semiconductor chip 1100. In the present embodiment, the metal pattern 1101 is disposed in contact with the outer periphery.

  15 is a cross-sectional view of the semiconductor chip 1400 in the vicinity of the end portion of DD shown in FIG. As shown in the figure, in this embodiment, the dummy bump layer 1403 is formed on the tip of the TSV and the metal pattern 1401. With such a configuration, it can be expected that a bonding layer without a gap is reliably formed on the metal pattern 1401 before bonding, and at the same time, more efficient heat dissipation is possible. As shown in the figure, it is preferable that the TSV 104 is not in contact with the outer peripheral portion.

  In addition, the metal pattern 1401 in this embodiment is arranged in contact with the outer peripheral portion of the semiconductor chip 1400. By arranging in this way, the circuit region 101 can be secured widely, and as a result, the circuit bump 102 The degree of freedom of arrangement also increases.

(Eighth embodiment)
FIG. 16 is a front view schematically showing a semiconductor chip 1600 according to the eighth embodiment. The arrangement of the circuit area 101 is the same as that of the fifth embodiment. The point that the dummy bump layer 1603 is integrally provided as a dummy bump group (second bump group) on the metal pattern 1601 is also the same as that of the fifth embodiment, but the shape of the metal pattern 1601 in the present embodiment and The arrangement of the circuit bumps 1602 is different from that of the fifth embodiment.

  In the embodiments so far, the circuit bumps 102 have been described as being arranged in a regular matrix. However, in actuality, depending on the elements and wirings arranged depending on the functions required for the circuit, etc. Since it is formed, its arrangement is not always regular. In the present embodiment, a case where the circuit bumps 1602 are arranged in a biased manner in the circuit region 101 will be described.

  If the circuit bumps 1602 are arranged in a biased manner, the generation of heat and the subsequent distribution are also biased during the operation of the stacked semiconductor device. Therefore, in the present embodiment, the width of the metal pattern 1601 adjacent to the region where the heat generation is large in the circuit region 101 is made larger than the width of the metal pattern 1601 adjacent to the other region. Specifically, as shown in the drawing, an area where the density of the circuit bumps 1602 is high in the circuit area 101 is assumed to be an area where heat generation is large, and the width of the metal pattern 1601 in the vicinity of this area is increased. With this configuration, a more efficient heat dissipation path can be formed.

(Ninth embodiment)
Although the semiconductor chip stacking described with reference to FIG. 6 has been described as C2C, as described above, W2W is also conceivable as a manufacturing process of the stacked semiconductor device. In this embodiment, an example of the process of laminating by W2W will be described.

  FIG. 17 is a view showing an outline of one wafer 1701 in which a plurality of semiconductor chip regions 1700 are formed in the present embodiment. The semiconductor chip region 1700 becomes individual semiconductor chips after being cut by a cutting line of the wafer 1701, that is, a scribe line. In addition, a bump group which is a plurality of circuit bumps and a plurality of dummy bumps is already formed on the wafer 1701. In the present embodiment, it is assumed that the metal pattern is in contact with the outer peripheral portion of the semiconductor chip as described in the seventh embodiment.

  When attention is paid to an area E of the wafer 1701 formed in this way, the four semiconductor chip areas 1711, 1712, 1713 and 1714 as the semiconductor chip area 1700 are adjacent to each other.

  FIG. 18 is an enlarged view of a region E in FIG. In the present embodiment, since the metal pattern is in contact with the outer peripheral portion of the semiconductor chip, the boundary portion of each semiconductor chip region is a metal pattern. And it cut | disconnects by the scribe line 1721 and the scribe line 1722 assumed on this metal pattern, and is divided | segmented as each semiconductor chip. At the intersection, an alignment mark 1730 is provided as an index, which serves as a reference for alignment when the wafers are stacked. The wafer stacking apparatus joins the wafers facing each other using the alignment mark 1730 as a target. With this configuration, the metal pattern can be used as an alignment mark for alignment. The alignment mark 1730 is provided by being masked in a cross so that the metal pattern is not deposited. The alignment mark 1730 is not limited to a cross, but may be other figures.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

1 is a front view schematically showing a semiconductor chip 100 according to a first embodiment. 2 is a cross-sectional view of the vicinity of an end portion of the semiconductor chip 100 according to the first embodiment. FIG. It is a conceptual diagram explaining the lamination | stacking process of the semiconductor chip based on 1st Embodiment. It is a conceptual diagram explaining the lamination | stacking process which laminates | stacks the semiconductor chip group 300 and another component. 1 is a cross-sectional view of a stacked semiconductor device according to a first embodiment. It is a flowchart which shows the manufacturing process of the laminated semiconductor device based on 1st Embodiment. 6 is a cross-sectional view of the vicinity of an end portion of a semiconductor chip 100 according to a second embodiment. FIG. It is a front view which shows typically the semiconductor chip 800 based on 3rd Embodiment. It is sectional drawing of the edge part vicinity of the semiconductor chip 100 based on 3rd Embodiment. It is sectional drawing of the edge part vicinity of the semiconductor chip 800 based on 4th Embodiment. It is a front view showing typically semiconductor chip 1100 concerning a 5th embodiment. FIG. 10 is a cross-sectional view of the vicinity of an end portion of a semiconductor chip 1100 according to a fifth embodiment. It is a front view showing typically semiconductor chip 1100 concerning a 6th embodiment. It is a front view showing typically semiconductor chip 1400 concerning a 7th embodiment. It is sectional drawing of the edge part vicinity of the semiconductor chip 1400 based on 7th Embodiment. It is a front view showing typically semiconductor chip 1600 concerning an 8th embodiment. It is a figure which shows the outline | summary of the one wafer 1701 in which the semiconductor chip area | region 1700 was formed in multiple numbers based on 9th Embodiment. It is an enlarged view of the area | region E of FIG. It is a figure which shows the typical example of a W2W process.

Explanation of symbols

100 semiconductor chip, 101 circuit area, 102 circuit bump, 103 dummy bump, 104 TSV, 201 insulating film, 202 barrier metal, 203 aluminum thin film wiring, 204 transistor circuit, 300 semiconductor chip group, 301 uppermost semiconductor chip, 302 intermediate surface Semiconductor chip, 303 lowermost semiconductor chip, 401 heat spreader, 402 base, 501 underfill, 502 mold member, 701 buffer metal, 800 semiconductor chip, 801 metal pattern, 1100 semiconductor chip, 1101 metal pattern, 1103 dummy bump layer, 1301 Metal pattern, 1303 dummy bump layer, 1400 semiconductor chip, 1401 Metal pattern, 1403 dummy bump layer, 1600 semiconductor chip, 1601 Metal pattern, 1602 Circuit bump, 1603 Dummy bump layer, 1700 Semiconductor chip area, 1701 Wafer, 1711, 1712, 1713, 1714 Semiconductor chip area, 1721, 1722 Scribe line, 1730 Alignment mark, 1901 Si substrate, 1902 Insulating layer, 1903 Transistor circuit, 1904, 1905 Al pad, 1906 TSV, 1907 bump

Claims (50)

A stacked semiconductor device comprising a plurality of stacked semiconductor chips,
The plurality of semiconductor chips include a circuit region, a first bump electrically connected to an element in the circuit region, a second bump not electrically connected to an element in the circuit region, and a plurality of TSVs ( Through Si Via), a metal pattern provided on the plurality of semiconductor chips,
Each with
The first bumps facing each other between the plurality of semiconductor chips overlapping each other, and the second bumps facing each other between the plurality of semiconductor chips overlapping each other are bonded together,
The first bump is formed at the tip of the plurality of TSVs,
The second bump is formed on the tip of the plurality of TSVs and the metal pattern,
A heat spreader joined to at least one surface of the outermost semiconductor chip among the plurality of semiconductor chips;
The first bump of the outermost semiconductor chip does not contact the heat spreader, and the second bump is bonded to the heat spreader ,
A plurality of the second bumps are formed on the metal pattern,
The plurality of second bumps are integrated with each other at least after bonding to form a bonding layer having no gap on the metal pattern . A stacked semiconductor device comprising a plurality of stacked semiconductor chips,
The plurality of semiconductor chips include a circuit region, a first bump electrically connected to an element in the circuit region, a second bump not electrically connected to an element in the circuit region, and a plurality of TSVs ( Through Si Via), a metal pattern provided on the plurality of semiconductor chips,
Each with
The first bumps facing each other between the plurality of semiconductor chips overlapping each other, and the second bumps facing each other between the plurality of semiconductor chips overlapping each other are bonded together,
The first bump is formed at the tip of the plurality of TSVs,
One of the second bumps is formed on the metal pattern, and the other is formed at the tip of the plurality of TSVs,
A heat spreader joined to at least one surface of the outermost semiconductor chip among the plurality of semiconductor chips;
The first bump of the outermost semiconductor chip does not contact the heat spreader, and the second bump is bonded to the heat spreader ,
A plurality of the second bumps are formed on the metal pattern,
The plurality of second bumps are integrated with each other at least after bonding to form a bonding layer having no gap on the metal pattern . A stacked semiconductor device comprising a plurality of stacked semiconductor chips,
The plurality of semiconductor chips include a circuit region, a first bump electrically connected to an element in the circuit region, a second bump not electrically connected to an element in the circuit region, and a plurality of TSVs ( Through Si Via), a metal pattern provided on the plurality of semiconductor chips,
Each with
The first bumps facing each other between the plurality of semiconductor chips overlapping each other, and the second bumps facing each other between the plurality of semiconductor chips overlapping each other are bonded together,
The first bump is formed at the tip of the plurality of TSVs,
The metal pattern is formed on the plurality of TSVs, and the second bump is formed on the metal pattern.
A heat spreader joined to at least one surface of the outermost semiconductor chip among the plurality of semiconductor chips;
The first bump of the outermost semiconductor chip does not contact the heat spreader, and the second bump is bonded to the heat spreader ,
A plurality of the second bumps are formed on the metal pattern,
The plurality of second bumps are integrated with each other at least after bonding to form a bonding layer having no gap on the metal pattern . 4. The stacked semiconductor device according to claim 1 , wherein the metal pattern is a pattern that closes and surrounds the circuit region. 5. 5. The stacked semiconductor device according to claim 1 , wherein the metal pattern is a pattern in contact with an outer peripheral portion of the semiconductor chip. 5. The stacked semiconductor device according to claim 1 , wherein the metal pattern is a pattern separated from an outer peripheral portion of the semiconductor chip. 6. 7. The heat generation distribution of the circuit area according to claim 1, wherein a width of the metal pattern adjacent to a region where heat generation is large is larger than a width of the metal pattern adjacent to a region where heat generation is small. Stacked semiconductor device. The semiconductor chip has a plurality of the first bumps and a plurality of the second bumps, and the density per unit area of the second bumps is larger than the density per unit of the first bumps. The stacked semiconductor device according to claim 1 . The stacked semiconductor device according to claim 1, wherein the first bump and the second bump are made of the same material. The stacked semiconductor device according to claim 1, wherein the first bump and the second bump have the same size. The stacked semiconductor device according to claim 1 , wherein a diameter of the first bump and a diameter of the second bump are the same. The height of the bonding surface of the first bump from the semiconductor chip surface is any one of the second claims 1 to 11 is the same as the height of the bonding surfaces of the bump from the surface of the semiconductor chip The stacked semiconductor device according to the item. The height of the bonding surface of the first bump from the semiconductor chip surface is any one of the second billing higher than the height of the joint surface of the bumps to claim 1 to 11 from the surface of the semiconductor chip 2. A stacked semiconductor device according to 1. The stacked semiconductor device according to claim 1, wherein the first bump and the second bump are formed by the same process. The stacked semiconductor device according to claim 1 , wherein the second bump is formed outside the circuit region. The stacked semiconductor device according to claim 1, wherein an underfill is filled between stacked semiconductor chips. A bump forming step of forming, on a semiconductor chip having a circuit area, a first bump electrically connected to an element in the circuit area and a second bump not electrically connected to an element in the circuit area; ,
A TSV forming step for forming a plurality of TSVs (Through Si Vias);
A metal pattern forming step for forming a metal pattern on the semiconductor chip;
Stacking the plurality of semiconductor chips that have undergone the bump forming step, and laminating the first bumps facing each other, and the second bumps facing each other,
A heat spreader bonding step for bonding a heat spreader to at least one of the outermost surfaces of the laminated semiconductor chips,
In the bump forming step, the first bump is formed on the tip of the TSV, and the second bump is formed on the tip of the TSV and the metal pattern.
In the heat spreader bonding step, the first bump on the outermost surface is not brought into contact with the heat spreader, and the second bump is bonded to the heat spreader ,
In the bump forming step, a plurality of the second bumps are formed,
The manufacturing method of a stacked semiconductor device, wherein the plurality of second bumps are integrated by the stacking step and a bonding layer having no gap is formed on the metal pattern . A bump forming step of forming, on a semiconductor chip having a circuit area, a first bump electrically connected to an element in the circuit area and a second bump not electrically connected to an element in the circuit area; ,
A TSV forming step for forming a plurality of TSVs (Through Si Vias);
A metal pattern forming step for forming a metal pattern on the semiconductor chip;
Stacking the plurality of semiconductor chips that have undergone the bump forming step, and laminating the first bumps facing each other, and the second bumps facing each other,
A heat spreader bonding step for bonding a heat spreader to at least one of the outermost surfaces of the laminated semiconductor chips,
In the bump forming step, the first bump is formed on the tip of the TSV, one of the second bumps is formed on the metal pattern, and the other is formed on the tip of the plurality of TSVs.
In the heat spreader bonding step, the second bump is bonded to the heat spreader without bringing the first bump on the outermost surface into contact with the heat spreader ;
In the bump forming step, a plurality of the second bumps are formed,
The manufacturing method of a stacked semiconductor device, wherein the plurality of second bumps are integrated by the stacking step and a bonding layer having no gap is formed on the metal pattern . A bump forming step of forming, on a semiconductor chip having a circuit area, a first bump electrically connected to an element in the circuit area and a second bump not electrically connected to an element in the circuit area; ,
A TSV forming step for forming a plurality of TSVs (Through Si Vias);
A metal pattern forming step for forming a metal pattern on the semiconductor chip;
Stacking the plurality of semiconductor chips that have undergone the bump forming step, and laminating the first bumps facing each other, and the second bumps facing each other,
A heat spreader bonding step for bonding a heat spreader to at least one of the outermost surfaces of the laminated semiconductor chips,
In the bump forming step, the first bump is formed at a tip of the TSV, the metal pattern is formed on the plurality of TSVs, and the second bump is formed on the metal pattern,
In the heat spreader bonding step, the second bump is bonded to the heat spreader without bringing the first bump on the outermost surface into contact with the heat spreader ;
In the bump forming step, a plurality of the second bumps are formed,
The manufacturing method of a stacked semiconductor device, wherein the plurality of second bumps are integrated by the stacking step and a bonding layer having no gap is formed on the metal pattern . 20. The method for manufacturing a stacked semiconductor device according to claim 17, wherein the metal pattern formed by the metal pattern forming step is a pattern that closes and surrounds the circuit region. 21. The method for manufacturing a stacked semiconductor device according to claim 17, wherein the metal pattern formed by the metal pattern forming step is a pattern in contact with an outer peripheral portion of the semiconductor chip. 21. The method of manufacturing a stacked semiconductor device according to claim 17, wherein the metal pattern formed by the metal pattern forming step is a pattern that does not contact an outer peripheral portion of the semiconductor chip. In the heat generation distribution of the circuit region, claim the width of the metal pattern adjacent to a large area of the exotherm, the adjacent small area of heat generation to be larger than the width of the metal pattern, is formed by the bump forming step 23. The method for manufacturing a stacked semiconductor device according to any one of 17 to 22 . In the bump forming step, a plurality of the first bumps and a plurality of the second bumps are formed,
The lamination according to any one of claims 17 to 23 , wherein a density per unit area of the plurality of second bumps formed by the bump forming step is larger than a density per unit of the plurality of first bumps. Type semiconductor device manufacturing method. 25. The method for manufacturing a stacked semiconductor device according to claim 17 , wherein in the bump forming step, the first bump and the second bump are formed of the same material. 26. The method for manufacturing a stacked semiconductor device according to claim 17 , wherein, in the bump forming step, the first bump and the second bump are formed to have the same size. 27. The method for manufacturing a stacked semiconductor device according to any one of claims 17 to 26 , wherein in the bump forming step, the first bump is formed to have the same diameter as the second bump. In the bump forming step, the height of the bonding surface of the first bump from the surface of the semiconductor chip is the same as the height of the bonding surface of the second bump from the surface of the semiconductor chip. The method for manufacturing a stacked semiconductor device according to any one of claims 17 to 27 . In the bump forming step, the height of the bonding surface of the first bump from the surface of the semiconductor chip is higher than the height of the bonding surface of the second bump from the surface of the semiconductor chip. The method for manufacturing a stacked semiconductor device according to any one of claims 17 to 27 . 30. The method for manufacturing a stacked semiconductor device according to claim 17 , wherein, in the bump forming step, the first bump and the second bump are formed in the same process. 31. The method for manufacturing a stacked semiconductor device according to claim 17 , wherein in the bump forming step, the second bump is formed outside the circuit region. 32. The manufacturing of a stacked semiconductor device according to any one of claims 17 to 31 , wherein the stacking step stacks and joins semiconductor substrates on which a plurality of the semiconductor chips that have undergone the bump forming step are two-dimensionally arranged. Method. 33. The method of manufacturing a stacked semiconductor device according to claim 32 , wherein the stacking step performs alignment using an index provided at a boundary between a plurality of two-dimensionally arranged semiconductor chips as an alignment mark, and stacks a plurality of semiconductor substrates. . The method for manufacturing a stacked semiconductor device according to any one of claims 17 to 33 , further comprising an underfill filling step of filling a space between the stacked semiconductor chips with an underfill. Circuit area,
A first bump electrically connected to an element in the circuit area;
A second bump that is not electrically connected to an element in the circuit region;
Multiple TSV (Through Si Via),
A semiconductor substrate each having a metal pattern,
When stacked with another semiconductor substrate, the first bump is provided on the other semiconductor substrate and electrically connected to an element in the circuit region of the other semiconductor substrate. And the second bump is bonded to a second bump provided on the other semiconductor substrate and not electrically connected to an element in the circuit region of the other semiconductor substrate,
The first bump is formed at the tip of the plurality of TSVs,
The second bump is formed on the tip of the plurality of TSVs and the metal pattern,
The semiconductor substrate includes a plurality of semiconductor chips,
A heat spreader bonded to at least one surface of the outermost semiconductor chip among the plurality of stacked semiconductor chips;
The first bump of the outermost semiconductor chip does not contact the heat spreader, and the second bump is bonded to the heat spreader ,
A plurality of the second bumps are formed on the metal pattern,
The plurality of second bumps are integrated with each other at least after bonding to form a bonding layer having no gap on the metal pattern . Circuit area,
A first bump electrically connected to an element in the circuit area;
A second bump that is not electrically connected to an element in the circuit region;
Multiple TSV (Through Si Via),
A semiconductor substrate each having a metal pattern,
When stacked with another semiconductor substrate, the first bump is provided on the other semiconductor substrate and electrically connected to an element in the circuit region of the other semiconductor substrate. And the second bump is bonded to a second bump provided on the other semiconductor substrate and not electrically connected to an element in the circuit region of the other semiconductor substrate,
The first bump is formed at the tip of the plurality of TSVs,
One of the second bumps is formed on the metal pattern, and the other is formed at the tip of the plurality of TSVs,
The semiconductor substrate includes a plurality of semiconductor chips,
A heat spreader bonded to at least one surface of the outermost semiconductor chip among the plurality of stacked semiconductor chips;
The first bump of the outermost semiconductor chip does not contact the heat spreader, and the second bump is bonded to the heat spreader ,
A plurality of the second bumps are formed on the metal pattern,
The plurality of second bumps are integrated with each other at least after bonding to form a bonding layer having no gap on the metal pattern . Circuit area,
A first bump electrically connected to an element in the circuit area;
A second bump that is not electrically connected to an element in the circuit region;
Multiple TSV (Through Si Via),
A semiconductor substrate each having a metal pattern,
When stacked with another semiconductor substrate, the first bump is provided on the other semiconductor substrate and electrically connected to an element in the circuit region of the other semiconductor substrate. And the second bump is bonded to a second bump provided on the other semiconductor substrate and not electrically connected to an element in the circuit region of the other semiconductor substrate,
The first bump is formed at the tip of the plurality of TSVs,
The metal pattern is formed on the plurality of TSVs, and the second bump is formed on the metal pattern.
The semiconductor substrate includes a plurality of semiconductor chips,
A heat spreader bonded to at least one surface of the outermost semiconductor chip among the plurality of stacked semiconductor chips;
The first bump of the outermost semiconductor chip does not contact the heat spreader, and the second bump is bonded to the heat spreader ,
A plurality of the second bumps are formed on the metal pattern,
The plurality of second bumps are integrated with each other at least after bonding to form a bonding layer having no gap on the metal pattern . 38. The semiconductor substrate according to claim 35 , wherein the metal pattern is a pattern that closes and surrounds the circuit region. 39. The semiconductor substrate according to claim 35 , wherein the metal pattern is a pattern in contact with an outer peripheral portion of the semiconductor chip. The semiconductor substrate according to any one of claims 35 to 38 , wherein the metal pattern is a pattern separated from an outer peripheral portion of the semiconductor chip. In the heat generation distribution of the circuit region, the width of the metal pattern adjacent to a large area of heat generation, according to any one of the preceding claims 35 to 40 greater than the width of the metal pattern adjacent to a small area of heat generation Semiconductor substrate. The semiconductor chip has a plurality of the first bumps and a plurality of the second bumps, and the density per unit area of the second bumps is larger than the density per unit of the first bumps. The semiconductor substrate according to any one of claims 35 to 41 . 43. The semiconductor substrate according to claim 35, wherein the first bump and the second bump are made of the same material. 44. The semiconductor substrate according to claim 35, wherein the first bump and the second bump have the same size. 45. The semiconductor substrate according to claim 35 , wherein a diameter of the first bump and a diameter of the second bump are the same. The height of the bonding surface of the first bump from the semiconductor chip surface is any one of the second bump claims 35 to 45 is the same as the height of the bonding surface of the surface of the semiconductor chip The semiconductor substrate according to item. The height of the bonding surface of the first bump from the semiconductor chip surface is any one of the second bump bonding surface of the high from high claims 35 than of 46 from the surface of the semiconductor chip A semiconductor substrate according to 1. 48. The semiconductor substrate according to claim 35, wherein the first bump and the second bump are formed by the same process. 49. The semiconductor substrate according to claim 35 , wherein the second bump is formed outside the circuit region. 50. The semiconductor substrate according to claim 35, wherein an underfill is filled between the stacked semiconductor chips.

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