JP4011695B2 - Chip for multi-chip semiconductor device and method for forming the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multi-chip semiconductor device whose device area is small, whose constitution is simple and whose thickness is thin by providing a connection plug formed of metal in a through hole passing through a semiconductor substrate and an inter-layer insulating film and electrically connecting one chip with the other chip through the connection plug. SOLUTION: A metal plug 4 is formed on the outer side of an element forming area and the insulating films 5 are provided between the metal plug 4 and the silicon substrate 1/the first inter-layer insulating film so as to constitute the connection plug. The metal plug 4 of the chip 11 is electrically connected to the pad 6 provided for the multilayer wiring layer 3 of the chip 12 through a solder bump 8. The chip 11 is electrically connected to the chip 12 . The metal plug 4 of the chip 12 is electrically connected to the pad 6 provided for the multilayer wiring layer 3 of the chip 13 through the solder bump 8. Thus, the chips 11 , 12 and 13 are electrically connected. Since the chips 11 , 12 and 13 are stacked, the device area is prevented from increasing.

Description

[0001]
BACKGROUND OF THE INVENTION
  The present inventionMultichip semiconductor layer chip and method for forming the sameAbout.
[0002]
[Prior art]
In recent years, large-scale integrated circuits (chips) formed by integrating a large number of transistors, resistors, and the like so as to achieve an electric circuit and integrating them on a semiconductor substrate are frequently used in important parts of computers and communication devices. ing. For this reason, the performance of the entire device is greatly linked to the performance of a single chip.
[0003]
On the other hand, a so-called multi-chip semiconductor device that uses a plurality of chips to improve the performance of the entire device has also been proposed. 25 to 27 are sectional views of conventional multichip semiconductor devices.
[0004]
FIG. 25 shows a multi-chip semiconductor device of a type in which a plurality of chips 82 are arranged in a plane on a laminated wiring board 81, for example. In the figure, reference numeral 83 denotes a solder bump. FIG. 26 shows a multi-chip semiconductor device of a type in which chips are connected to each other with the surfaces facing each other (Face to Face). FIG. 27 shows a multi-chip semiconductor device of a type in which a plurality of chips 82 are stacked using a stacked plate 84.
[0005]
[Problems to be solved by the invention]
However, these conventional multichip semiconductor devices have the following problems.
[0006]
That is, the conventional multichip semiconductor device of FIG. 25 has a problem that the planar area of the device is large because a plurality of chips 82 are arranged in a plane.
[0007]
The conventional multichip semiconductor device of FIG. 26 has a problem that the planar area of the device does not increase because a plurality of chips 82 are stacked, but the number of stacked layers is limited to two. Also, it is difficult to electrically test each chip.
[0008]
In the conventional multichip semiconductor device of FIG. 27, since a plurality of chips 82 can be stacked, there is no problem that the plane area of the device becomes large or the number of stacked layers is limited to two. Since it is necessary to provide the laminated board 84, a structure becomes complicated and cost and thickness increase.
[0009]
  The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a multichip semiconductor device having a small planar area, a simple structure, and a small thickness.Realization ofIt is an object to provide a chip for a multichip semiconductor device and a method for forming the same.
[0016]
[Means for Solving the Problems]
[Constitution]
  To achieve the above object, according to the present invention.Multi-chip semiconductor device chip (claim)1) Is formed in a semiconductor substrate having elements integrated on the surface, an interlayer insulating film formed on the surface of the semiconductor substrate, and a through-hole penetrating the interlayer insulating film and the semiconductor substrate. A connection plug made of a metal for electrical connection with the connection plug, the connection plug being provided in the through hole, and having a hollow portion, and a side wall of the metal plug and the through hole And a low stress film provided in the hollow portion and having a difference in thermal expansion coefficient from that of the semiconductor substrate smaller than that of the metal plug.
[0018]
  Another chip for a multi-chip semiconductor device according to the present invention (claims)2) Is formed in a semiconductor substrate having elements integrated on the surface, an interlayer insulating film formed on the surface of the semiconductor substrate, and a through-hole penetrating the interlayer insulating film and the semiconductor substrate. A chip for a multichip semiconductor device comprising a connection plug made of a metal for electrical connection with the metal, wherein the connection plug is provided to a depth in the middle of the through hole on the semiconductor substrate surface side A plug and an insulating film provided between the metal plug and the side wall of the through hole are provided. A connection member for electrically connecting to another chip is provided in an unfilled portion of the through hole. It is characterized by being able to.
[0019]
Here, it is preferable that the back surface of the semiconductor substrate on the side where the connection member is provided is covered with an insulating film except for the portion of the connection member.
[0021]
  Further, according to the present inventionMethod for forming chip for multi-chip semiconductor device(Claims3), A step of forming elements on the surface of the semiconductor substrate, a step of forming an interlayer insulating film on the surface of the semiconductor substrate, etching the interlayer insulating film and the semiconductor substrate, penetrating the interlayer insulating film, And forming a hole not penetrating the semiconductor substrate, forming a first insulating film having a thickness not filling the hole on the side wall and bottom of the hole, and covering with the first insulating film. Filling the hole with metal as a metal plug, retreating the semiconductor substrate from the back of the semiconductor substrate until the first insulating film at the bottom of the hole is exposed, and the hole Selectively etching the semiconductor substrate on the bottom side of the hole until the first insulating film on the side wall of the hole is exposed above the first insulating film on the bottom of the hole; and The back side of the semiconductor substrate on the bottom side Forming a second insulating film on the surface, and retracting the first and second insulating films until the metal plug at the bottom of the hole is exposed, so that the back surface of the semiconductor substrate on the bottom side of the hole And a step of selectively leaving the second insulating film.
[0022]
  Further, another method for forming a chip for a multi-chip semiconductor device according to the present invention (claims)4) Is a method for forming a chip for a multi-chip semiconductor device (claim)3), The hole is formed before the wiring having the lowest melting point among the wirings formed on the semiconductor substrate is formed.
[0023]
Further, another method for forming a chip for a multi-chip semiconductor device according to the present invention (claims)5) Is a method for forming a chip for a multi-chip semiconductor device (claim)3), The semiconductor substrate is retracted after the semiconductor substrate is cut out from the wafer.
[0028]
  Further, the present invention (claims 1 to2The chip for a multi-chip semiconductor device is formed in a through hole penetrating the semiconductor substrate and the interlayer insulating film, and has a connection plug made of metal for electrically connecting to another chip.
[0029]
  Therefore, a multichip semiconductor device using such a chip for a multichip semiconductor device isTheThe plane area of the device is small, the structure is simple, and the thickness is thin.
[0030]
  Further, the present invention (claims 1 to2), The connection plug has an effect of promoting the heat dissipation of the chip. In addition, the device or the chip can be inspected by applying an inspection probe to the connection plug from the back surface of the chip.
[0036]
  Further, the present invention (claims)3), The through hole can be easily formed, and the exposed surface of the semiconductor substrate on the bottom side of the hole can be easily covered with the second insulating film.
[0037]
  Further, the recession of the semiconductor substrate is the present invention (claims).5It is preferable to carry out after the semiconductor substrate is cut out from the wafer as shown in FIG. This is because the wafer is generally large and has a low mechanical strength, so that it is difficult to perform the retreat uniformly by polishing or etching.
[0038]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.
[0039]
(First embodiment)
FIG. 1 is a cross-sectional view of a multichip semiconductor device according to the first embodiment of the present invention.
[0040]
This multi-chip semiconductor device has three chips 1₁, 1₂, 1_ThreeAre stacked. Each chip 1₁, 1₂, 1_ThreeAre roughly divided into a silicon substrate 2 on which elements are integrated on the surface, a multilayer wiring layer 3 for connecting the integrated elements in a predetermined relationship, and a first of the multilayer wiring layers 3. It is formed in a through hole penetrating the interlayer insulating film and the silicon substrate 1 and is composed of a connection plug (metal plug 4, insulating film 5) for electrically connecting the chips.
[0041]
The multilayer wiring layer 3 includes a first interlayer insulating film covering the element, a first wiring layer connected to the element via a contact hole (first connection hole) formed in the first interlayer insulating film, And a second interlayer insulating film formed on the first interlayer insulating film and covering the first wiring layer, and via holes (second connection holes) formed in the second interlayer insulating film. A second wiring layer connected to the first wiring layer; Three or more multilayer wiring layers may be used.
[0042]
The metal plug 4 is formed outside the element formation region. An insulating film 5 is provided between the metal plug 4 and the silicon substrate 1 and the first interlayer insulating film, in other words, between the metal plug 4 and the through hole. The insulating film 5 and the metal plug 4 constitute a connection plug.
[0043]
Each chip 1₁, 1₂, 1_ThreeEach of the multilayer wiring layers 3 is provided with a pad 6. Each chip 1₁, 1₂, 1_ThreeThe silicon region on the back surface of the silicon substrate 2 opposite to the pad 6, in other words, the region other than the connection plug (metal plug 4, insulating film 5) is covered with the insulating film 7.
[0044]
Chip 1₁The metal plug 4 is connected to the chip 1 via the solder bump 8.₂Are electrically connected to pads 6 provided in the multilayer wiring layer 3. As a result, chip 1₁Is chip 1₂Will be electrically connected. Note that bumps other than the solder bumps 8 may be used.
[0045]
Similarly, chip 1₂The metal plug 4 is connected to the chip 1 via the solder bump 8._ThreeThe chip 1 is electrically connected to the pad 6 provided on the multilayer wiring layer 3 of the chip 1.₂Is chip 1_ThreeAnd is electrically connected. In this way chip 1₁, 1₂, 1_ThreeThey are electrically connected.
[0046]
According to this embodiment, the chip 1₁, 1₂, 1_ThreeTherefore, unlike the conventional multi-chip semiconductor device in which a plurality of chips are positioned in a plane, there is no problem that the plane area of the device increases.
[0047]
Further, according to the present embodiment, since the chips are connected by the metal plug 4 penetrating the silicon substrate 2 and the first interlayer insulating film, the conventional multichip semiconductor in which the chips are connected by Face to Face. Unlike the device, there is no problem that the number of stacked chips is limited to two.
[0048]
Further, since a laminated plate is not used for connecting the chips, unlike the conventional multichip semiconductor device in which the chips are connected by the laminated plate, there is no problem that the structure becomes complicated or the thickness increases.
[0049]
Furthermore, the metal plug 4 has an effect of promoting heat dissipation.
[0050]
Therefore, according to the present embodiment, it is possible to realize a multichip semiconductor device having a small planar area, a simple structure, a thin thickness, and excellent heat dissipation.
[0051]
In the embodiment, the case where the number of chips is three has been described. However, if the chip structure of this embodiment is used, four or more chips can be similarly connected. Further, it is not always necessary that all the chips having the metal plug 4 be connected via the metal plug 4. That is, there may be a chip in which the metal plug 4 is formed only for the purpose of improving heat dissipation.
[0052]
(Second Embodiment)
FIG. 2 is a cross-sectional view of a multichip semiconductor device according to the second embodiment of the present invention. Parts corresponding to those of the multi-chip semiconductor device of FIG. 1 are denoted by the same reference numerals as those of FIG. 1, and detailed description thereof is omitted.
[0053]
In the present embodiment, the middle chip 1₂In this example, only the connection plug (metal plug 4 and insulating film 5) is provided.
[0054]
Chip₁The pads 6 provided on the multilayer wiring layer 3 are connected to the chip 1 via the solder bumps 8.₂Are electrically connected to pads 6 provided in the multilayer wiring layer 3. This makes the chip₁Is chip 1₂Will be electrically connected. Chip 1₂The metal plug 4 is connected to the chip 1 via the solder bump 8._ThreeThe chip 1 is electrically connected to the pad 6 provided on the multilayer wiring layer 3 of the chip 1.₂Is chip 1_ThreeAnd is electrically connected. In this way chip 1₁, 1₂, 1_ThreeThey are electrically connected.
[0055]
In the present embodiment, the same effect as in the first embodiment can be obtained. However, the middle chip 1₂Since only the connection plug (metal plug 4 and insulating film 5) is provided, four or more chips cannot be stacked. However, since only one connection plug is required, it is advantageous in terms of cost.
[0056]
(Third embodiment)
FIG. 3 is a cross-sectional view of a multichip semiconductor device according to the third embodiment of the present invention. Parts corresponding to those of the multi-chip semiconductor device of FIG. 1 are denoted by the same reference numerals as those of FIG. 1, and detailed description thereof is omitted.
[0057]
In this embodiment, two chips 1₁, 1₂Is an example of connection through a multilayer wiring board 9 made of ceramic.
[0058]
Chip₁The pads 6 provided on the multilayer wiring layer 3 are electrically connected to the pads 6 provided on the multilayer wiring board 9 via solder bumps 8. The other pads 6 provided on the laminated wiring board 9 electrically connected to the pads 6 are connected to the chip 1.₂Are electrically connected to pads 6 provided in the multilayer wiring layer 3. This makes the chip₁Is chip 1₂Will be electrically connected.
[0059]
In the present embodiment, the same effect as in the first embodiment can be obtained. Furthermore, according to this embodiment, the chip 1₂The inspection of the device can be performed by applying an inspection probe to the pad 6 provided in the multilayer wiring layer 3 of the semiconductor device.
[0060]
On the other hand, as shown in FIG. 2, the chip 1 having the metal plug 4.₂If there is a structure between the chips, the inspection probe cannot be applied, so such an inspection cannot be performed.
[0061]
(Fourth embodiment)
4 and 5 are process cross-sectional views illustrating a method for forming a chip for a multi-chip semiconductor device according to a fourth embodiment of the present invention.
[0062]
First, as shown in FIG. 4A, a silicon substrate 10 is prepared. The silicon substrate 10 is after element formation, and its surface is covered with a first interlayer insulating film 11. The material of the first interlayer insulating film 11 is SiO, like silicon nitride.₂Those having an etching selectivity ratio are selected.
[0063]
Next, as shown in FIG.₂1 μm thick mask pattern 12 is formed on first interlayer insulating film 11, and then, using mask pattern 12 as a mask, first interlayer insulating film 11 is etched by an RIE method using an F-based gas as an etching gas. Then, by etching the silicon substrate 10, a hole 13 that penetrates the first interlayer insulating film 11 and does not penetrate the silicon substrate 10 is formed. Thereafter, it is preferable to perform annealing for recovering the defects of the silicon substrate 10 generated when the holes 13 are formed.
[0064]
The depth of the hole in the silicon substrate 10 is 100 μm. The total depth of the hole 13 is obtained by adding the thickness of the first interlayer insulating film 11 to this. The hole 13 eventually becomes a through hole.
[0065]
Note that the silicon substrate 10 is etched by the RIE method to form a hole, then the first interlayer insulating film 11 is formed, and then the first interlayer insulating film 11 or the first interlayer insulating film 11 and It is also possible to form the hole 13 by etching the silicon substrate 10 by the RIE method.
[0066]
In this case, the mask pattern used in the first etching is SiO.₂Or Al or Al₂O_ThreeThose made of materials such as can be used.
[0067]
Further, the processing technique for forming the holes 13 (through holes) is not limited to RIE, and photo etching, wet etching, ultrasonic processing, and electric discharge processing can also be used. Furthermore, you may combine the said processing technique suitably. A method combining RIE or photoetching with wet etching will be described later.
[0068]
Next, as shown in FIG. 4 (c), a 100 nm-thick SiO2 film is formed on the entire surface.₂Film, 100 nm thick Si_ThreeN_FourFilms are sequentially deposited using LPCVD to produce SiO₂/ Si_ThreeN_FourThe laminated insulating film 14 (first insulating film) is formed. Note that a single-layer insulating film may be used instead of the laminated insulating film 14.
[0069]
Next, as shown in FIG. 4D, a metal film 15 to be a metal plug is formed on the entire surface so as to overflow from the hole 13, and the hole 13 is filled with the metal film 15.
[0070]
Here, examples of the metal film 15 include a W film, a Mo film, a Ni film, a Ti film, and a metal silicide film thereof. Examples of the method for forming the metal film 15 include a CVD method, a sputtering method, and a plating method.
[0071]
Next, as shown in FIG. 5E, the metal film 15 and the laminated insulating film 14 are retracted by using a method such as a CMP method or an etch back method until the surface of the first interlayer insulating film 11 is exposed. .
[0072]
As a result, a structure in which the metal film (metal plug) 15 is embedded in the hole 13 is formed. Such a structure can be formed by other forming methods. The formation method will be described later (FIGS. 14 and 15).
[0073]
Next, as shown in FIG. 5F, a multilayer wiring structure 16 constituting a multilayer wiring layer is formed on the silicon substrate 10 together with the first interlayer insulating film 11. The multilayer wiring structure 16 is composed of a metal wiring (wiring layer), an interlayer insulating film, a plug, and the like. Thereafter, a groove is formed on the surface of the multilayer wiring structure 16, and then a pad 17 is formed in the groove.
[0074]
6 and 7 show examples of specific structures of the multilayer wiring layer in the hole 13 region and the multilayer wiring layer in the element region, respectively.
[0075]
A MOS transistor is formed in the element region. In the figure, 11a is a second interlayer insulating film, 11b is a third interlayer insulating film, 11c is a fourth interlayer insulating film, 11n is an nth interlayer insulating film, and 19a and 20a are first metal wirings. , 19b and 20b are second metal wires, and 20c is a third metal wire.
[0076]
Next, as shown in FIG. 5G, the silicon substrate 10 is retracted from the back surface of the silicon substrate opposite to the surface on which the hole 13 is formed until the insulating film 14 at the bottom of the hole 13 is exposed.
[0077]
Here, the receding (thinning) of the silicon substrate 10 is performed by a method using a processing technique such as CMP, chemical polishing, mechanical polishing, wet etching, plasma etching or gas etching, or a combination of these processing techniques. . Of these, CMP is the most typical method and is preferred.
[0078]
The step of FIG. 5G is preferably performed under conditions that allow a selection ratio between the silicon substrate 10 and the insulating film 14 to be obtained. If the process is performed under such conditions, the process can be automatically terminated at the insulating film 14.
[0079]
Next, as shown in FIG. 5H, the back surface of the silicon substrate 10 on the bottom side of the hole 13 is selected until the insulating film 14 on the side wall of the hole 13 is exposed above the insulating film 14 on the bottom of the hole 13. Etch. For this etching, for example, dry etching such as CDE or RIE or wet etching is used. Note that CMP may be used instead of etching.
[0080]
Thereafter, the damaged layer caused by the etching or CMP is removed by, for example, wet etching. This removal step is unnecessary when no damage layer is formed. The reason for removing the damaged layer is that the damaged layer is made of the next SiO₂This is because the process of forming the film 18 is affected.
[0081]
Next, as shown in FIG. 6H, the plasma CVD method is used to form SiO on the entire back surface of the silicon substrate 10 on the bottom side of the hole 13.₂A film 18 (second insulating film) is formed. When a low temperature process is required, SiO₂Instead of the film 18, a coating film such as an SOG film may be used. When it is desired to reduce the stress applied to the silicon substrate 10, SiO 2₂Instead of the film 18, an organic film such as a polyimide film may be used.
[0082]
Next, as shown in FIG. 5 (i), until the metal plug 15 is exposed, the CMP method is used.₂The film 18 and the laminated insulating film 14 are polished.
[0083]
As a result, the connection plug comprising the insulating film 14 and the metal plug 15 is embedded in the through hole (hole 13), and the silicon region on the back surface of the silicon substrate 10 is SiO.₂The structure covered with the membrane 18 is completed.
[0084]
As described above, in this embodiment, after the hole 13 that does not penetrate the silicon substrate 10 is formed on the surface of the silicon substrate 10, the silicon substrate 10 and the like are polished from the back surface to thereby form the inside of the through hole (hole 13). Is embedded with a connection plug (insulating film 14, metal plug 15).
[0085]
Therefore, according to the present embodiment, even if the original silicon substrate 1 is thick (usually thick), it is not necessary to form a deep through-hole, so that the through-hole (hole 13) is connected to the connection plug (insulating film 14, A structure embedded with the metal plug 15) can be easily formed.
[0086]
In addition, unlike the method of etching from the back surface of a thick silicon substrate to form deep through holes, the method of this embodiment eliminates the need for photolithography that requires front / back pattern alignment. The connection plug formation process is simple and requires fewer steps.
[0087]
Note that the silicon region on the back surface is made of SiO.₂When it is not necessary to cover with the film 18, the through hole (hole 13) is connected by polishing the silicon substrate 10 and the laminated insulating film 14 until the metal plug 15 is exposed in the step of FIG. A structure embedded with plugs (insulating film 14, metal plug 15) is completed.
[0088]
Further, it is preferable to polish (retreat) the silicon substrate 10 after cutting the silicon substrate 10 from the wafer. This is because the wafer is generally large and has a low mechanical strength, so that it is difficult to polish (retreat) uniformly.
[0089]
Further, since the hole 13 is formed before the metal wiring is formed and the metal plug 15 is formed by embedding the metal film therein, the metal wiring is not affected by the thermal process when the metal plug 15 is formed. It will end. Further, the metal wiring is not affected by annealing for defect recovery performed after the hole 13 is formed by RIE.
[0090]
Thus, for example, when an Al wiring (the melting point of Al is 660 ° C.) is used as the metal wiring, the metal plug 15 can be formed of a conductive paste such as Au having a low resistance (sintering temperature is about 600 ° C.). It becomes.
[0091]
Further, since the metal plug 15 is formed after the element is formed, it is possible to prevent deterioration of element characteristics due to diffusion of the constituent metal of the metal plug 15.
[0092]
On the contrary, when the element is formed after the metal plug 15 is formed, the constituent metal of the metal plug 15 diffuses to the element region in a high-temperature heat process necessary for forming the element, and the element characteristics deteriorate. Occurs.
[0093]
FIG. 8 shows sectional views of connection plugs having various structures. This is a cross-sectional view corresponding to the step of FIG. In the figure, reference numeral 19 denotes a metal wiring.
[0094]
FIG. 8A shows the connection plug of this embodiment.
[0095]
FIG. 8B shows a connection plug having a low stress film 18.
[0096]
That is, in this connection plug, the metal plug 15 is formed so that an unfilled portion is formed in the through hole, and the difference in thermal expansion coefficient from the semiconductor substrate 10 a is smaller in the unfilled portion than the metal plug 15. Is formed and the through hole is filled.
[0097]
The low stress film 18 may be an insulating film, a semiconductor film, or a metal film. Specifically, conductive paste film, FOX film, SOG film, SiOD (High Density Plasma) -SiO formed by CVD method₂Examples include membranes.
[0098]
By using such a connection plug, a large stress is applied to the connection plug forming portion, and deterioration of element characteristics due to the occurrence of a defect in the silicon substrate 10 can be prevented.
[0099]
FIG. 8C shows a connection plug having a cap metal film 45.
[0100]
That is, the metal plug 15 is formed only to a depth in the middle of the through hole, and a cap metal film 45 filling the through hole is formed on the upper surface of the metal plug 15. FIG. 8D shows a connection plug using a cap insulating film 46 instead of the cap metal film 45.
[0101]
With the cap metal film 45 and the cap insulating film 46, the surface of the metal plug 15 can be flattened, whereby the fine metal wiring 19 can be easily formed on the metal plug 15.
[0102]
Further, by using the cap insulating film 46 that can be formed at a low temperature, problems such as oxidation of the surface of the metal plug 15 in a later step can be prevented.
[0103]
FIG. 9 is a process cross-sectional view illustrating another method for forming the hole 13. This is a formation method in which RIE or photoetching and wet etching are combined.
[0104]
First, as shown in FIG. 9A, a first interlayer insulating film 11 is formed on a silicon substrate 10 whose main surface is {100}. Next, as shown in FIG. 6A, after forming a mask pattern 12 on the first interlayer insulating film 11, the first interlayer insulating film 11 and the silicon substrate 10 are etched using the mask pattern 12 as a mask. Then, the hole 13 whose cross-sectional shape is rectangular₁Form.
[0105]
Here, as the etching, RIE or photoetching (photochemical etching, photoablation (photoablation) etching) is used. In particular, photoetching has the advantages of high-speed etching and low damage.₁Suitable for forming. In the case of photochemical etching, for example, Cl as an etching gas.₂Ultraviolet rays are used as gas and excitation light.
[0106]
Next, as shown in FIG. 9B, the silicon substrate 10 is wet etched using the mask pattern 12 as a mask to expose the {111} plane. As a result, the cross-sectional shape of the hole 13 is triangular.₂Is formed. As the etchant, for example, a KOH solution having a temperature of 60 to 90 ° C. is used.
[0107]
Next, as shown in FIG.₂Inside, for example, a metal 21 such as Ni, Ti, Zr, Hf, or V is disposed. Specifically, the metal 21 is inserted into the hole 13.₂Place in the bottom part of.
[0108]
Next, as shown in FIG. 9C, the metal 21 and the silicon substrate 10 are reacted by heat treatment to cause the holes 13 to react.₂A metal silicide film 22 is formed on the lower silicon substrate 10.
[0109]
Next, as shown in FIG. 9D, the metal silicide film 22 is selectively removed by etching to form a deeper hole 13._ThreeForm. Finally, after forming the insulating film and filling the metal, the back surface of the substrate is polished to obtain a deep through hole.
[0110]
By deepening the holes in steps as described above, it becomes possible to easily form deep holes, and thus it is possible to easily form through holes.
[0111]
FIG. 10 shows another method for forming the metal plug.
[0112]
FIG. 10A shows a method in which the conductive paste 23 is applied to the entire surface, then the conductive paste 23 is fluidized by heat treatment, and the conductive paste 23 is embedded in the holes. Excess conductive paste 23 outside the hole is removed using, for example, a CMP method.
[0113]
FIG. 10B shows a method in which the metal fine particles 24 are deposited on the entire surface, the inside of the hole is filled with the fine particles 24, and then the excess metal fine particles 24 outside the hole are removed using a CMP method or the like. .
[0114]
Instead of the metal fine particles 29, a solvent (suspension) in which metal particles are dispersed may be used.
[0115]
In FIG. 10C, a silicon film 25 is deposited on the entire surface, and then a refractory metal film (not shown) such as a Ti film is deposited on the silicon film 25, and then the refractory metal film and the silicon film 25 are subjected to heat treatment. The metal silicide film 26 is formed by reacting with the above. Excess metal silicide film 26 outside the hole is removed using, for example, a CMP method.
[0116]
The silicon film is conformally deposited on the insulating film. Further, the adhesion between the silicon film and the metal film is high. Therefore, in the case of the method of FIG. 10C, even if the hole is deep, the entire surface of the laminated insulating film 14 in the hole is covered with the silicon film 25. Therefore, the metal silicide film covering the entire surface of the laminated insulating film 14 in the hole. 31 is formed. In addition, when a cavity part remains in a hole, it is good to fill with a low stress film | membrane, for example.
[0117]
FIG. 11 shows still another method for forming a metal plug.
[0118]
First, as shown in FIG. 11A, a silicon film 27 having a cavity is formed by covering the entire side wall and bottom of the hole 13. Thereafter, as shown in FIG. 5A, Ni grains 28 (metal balls) having a diameter of about 10 μm are disposed in the holes 13.
[0119]
Next, as shown in FIG. 11B, the silicon film 27 and the Ni grains 28 are reacted by heat treatment to form a nickel silicide film 29 in the hole 13. Since there is not a sufficient amount of silicon film 27 and Ni grains 28 in the hole 13, a cavity portion remains above the nickel silicide film 29.
[0120]
Finally, as shown in FIG. 11C, after depositing an insulating film or a metal film to be the cap film 30 on the entire surface, the insulating film or the metal film is polished to form a cavity above the nickel silicide film 30. The portion is filled with the cap film 35.
[0121]
Note that the method for forming the metal plug is the method described so far (CVD method, sputtering method, plating method, method using conductive paste, method using metal fine particles, method using metal balls, suspension liquid) It is not limited to the method used), and various methods such as a method of appropriately combining these methods are possible.
[0122]
FIG. 12 shows another method for forming the connection plug. This method is different from the conventional methods in that the metal plug 15 is formed after the back surface of the silicon substrate 11 is polished to form a through hole.
[0123]
First, as shown in FIG. 12A, after a mask pattern 12a made of Al is formed on a silicon substrate 10 having elements formed on the surface, a first interlayer insulating film is formed using the mask pattern 12a as a mask. 11 and the silicon substrate 10 are etched to form holes 13. Thereafter, the mask pattern 12a is removed.
[0124]
Next, as shown in FIG. 12B, after the SOG film 31 is formed on the entire surface, the FOX film 32 is formed on the entire surface so that the hole 13 is completely buried.
[0125]
Next, as shown in FIG. 12C, the SOG film 31 and the FOX film 32 outside the hole 13 are removed by using, for example, a CMP method or an etch back method.
[0126]
Thereafter, the steps shown in FIGS. 5E to 5I are performed.
[0127]
Next, as shown in FIG. 12D, after the FOX film 32 in the hole 13 is removed by using, for example, the CDE method, the inside of the hole 13 is formed in the same manner as in the steps of FIGS. 4D and 5E. Then, a metal plug 15 made of a metal film is embedded and formed.
[0128]
In the case of the connection structure as shown in FIG. 13, the metal balls 34 such as the pads 33 and Au balls are formed after the metal plugs 15 are formed.
[0129]
14 and 15 show still another method for forming the connection plug. This method is different from the conventional methods in that a metal plug 15 previously formed in a place different from the silicon substrate 10 is embedded in the hole 13.
[0130]
First, a method for forming the metal plug 15 will be described.
[0131]
First, as shown in FIG.₂A groove 36 is formed on the surface of the substrate 35 made of the following.
[0132]
Next, as shown in FIG. 3A, a metal ball 37 is embedded in the groove 36.
[0133]
Finally, as shown in FIG. 14B, the metal plug 37 made of a metal film is formed in the groove 36 by melting the metal ball 37 by heat treatment.
[0134]
Next, a method for forming a connection plug using the metal plug 15 formed in advance will be described.
[0135]
First, as shown in FIG. 14C, the metal plug 15 is bonded to the adhesive film 38.
[0136]
Next, as shown in FIG. 15 (d), the metal plug 15 adhered to the adhesive film 38 is taken out from the groove 36.
[0137]
Next, as shown in FIG. 15E, the metal plug 15 bonded to the adhesive film 38 is embedded in the hole 13 of the silicon substrate 10 at the stage of the process of FIG. Thereafter, the adhesive film 38 is removed.
[0138]
Next, as shown in FIG. 15 (f), the metal plug 15 is fixed in the hole 13 by melting the metal plug 15 by heat treatment.
[0139]
In the case of the method using the metal plug 15 formed in advance on the substrate 15, a method of forming a metal film to be the metal plug 4 on the silicon substrate 10 by using a film forming method such as a sputtering method or a CVD method. Compared with the above case, the throughput is high and the process temperature is low.
[0140]
Here, the material of the substrate 35 is SiO.₂However, other materials may be used as long as the material does not react with the metal ball 37.
[0141]
Instead of the metal balls 37, a low-resistance conductive paste such as Au or Pd may be used. In this case, the conductive paste is embedded in the groove 36 by using a screen printing method, and then the conductive paste is sintered to form the metal plug 15.
[0142]
Here, although the conductive paste such as Au or Pd has a high sintering temperature, there is no problem because the conductive paste is sintered on the substrate 35 which is a separate melt from the silicon substrate 10. In addition, unlike a normal conductive paste, the conductive paste does not need to contain resin or glass.
[0143]
Moreover, although the metal plug 15 was taken out from the groove 36 using the adhesive film 38, it may be taken out by other means such as tweezers.
[0144]
Alternatively, the metal plug 15 may be fixed in the hole 13 by forming an adhesive layer in the hole 13 in advance. Specifically, for example, SOG or FOX is applied in the hole 13 to form an adhesive layer, and then the metal plug 15 is embedded in the hole 13. Thereafter, the adhesive layer is cured.
[0145]
(Fifth embodiment)
FIG. 16 is a cross-sectional view illustrating a method for forming a chip for a multichip semiconductor device according to a fifth embodiment of the present invention. 4 and FIG. 5 are assigned the same reference numerals as those in FIG. 4 and FIG. 5 and their detailed description is omitted.
[0146]
In this embodiment, after the step of FIG. 5 (i) of the fourth embodiment, as shown in FIG. 16 (a), the metal plug 15 is etched from the back surface of the silicon substrate 10 so that the through hole is not formed. Forming a filling portion;
[0147]
Next, as shown in FIG. 16B, after the metal plug 15 (the concave portion of the unfilled portion of the through hole) and the solder bump 8 are aligned, the metal plug 15 and the solder bump 8 are connected.
[0148]
Here, the alignment of the metal plug 15 and the solder bump 8 is preferably performed by image processing. This is because, on the screen, the difference in density between the concave portion of the unfilled portion and the non-filled portion becomes clear, so that accurate alignment can be easily performed.
[0149]
Further, when the side surfaces of the bumps 8 are in contact with the side surfaces of the through holes, the bumps 8 are more firmly fixed as compared with the case where there is no recess in the unfilled portion.
[0150]
Conversely, a convex structure in which the metal plug 15 protrudes from the through hole may be employed. In this case, since the bump 8 does not contact the silicon substrate 10, contamination of the silicon substrate 10 by the bump 8 can be effectively prevented.
[0151]
(Sixth embodiment)
FIG. 17 is a cross-sectional view of a multichip semiconductor device according to the sixth embodiment of the present invention. Parts corresponding to those of the multi-chip semiconductor device of FIG. 1 are denoted by the same reference numerals as in FIG. Chip 1₁, 1₂In FIG. 5, the multilayer wiring layer 3, the insulating films 5 and 7, the pad 6, and the like are omitted.
[0152]
The feature of this embodiment is the chip 1₁The heat dissipating fins 39 are provided on the top. The heat radiating fins 39 are connected to the chip 1 by an adhesive 40.₁It is fixed to. It should be noted that other fixing methods such as metallization on the insulating film may be used.
[0153]
According to the present embodiment, the metal plug 4 and the heat radiating fan 39 can sufficiently increase the heat dissipation of the device.
[0154]
(Seventh embodiment)
FIG. 18 is a cross-sectional view of a multichip semiconductor device according to the seventh embodiment of the present invention. Parts corresponding to those of the multi-chip semiconductor device of FIG. 1 are denoted by the same reference numerals as in FIG. In the figure, 7a indicates an insulating film, and 42 indicates a solder.
[0155]
The feature of this embodiment is the chip 1₁And chip 1₂Is provided with a dummy bump 8d for heat dissipation.
[0156]
Chip 1₁And chip 1₂Are mechanically connected via dummy bumps 8d but not electrically connected. The dummy bump 8d is formed on the chip 1 via a metal film (not shown), for example.₁And chip 1₂Connect with.
[0157]
Examples of the material of the dummy bump 8d include metals such as Au. Even if it is not a metal, a semiconductor or an insulator may be used as long as it has a good thermal conductivity. A filler may also be used. If the dummy bumps 8d and the wiring bumps 8 are formed of the same material, these bumps can be formed at the same time, and an increase in the number of steps can be prevented.
[0158]
Although the heat dissipation is improved only by the dummy bumps 8d, it is preferable to connect the dummy bumps 8d to the heat dissipation fins in order to effectively increase the heat dissipation.
[0159]
(Eighth embodiment)
FIG. 19 shows a method for manufacturing a multichip semiconductor device according to the eighth embodiment of the present invention.
[0160]
In the method shown in FIG. 16, the solder bumps 8 are formed on the metal plug 15, but in the present embodiment, conversely, the connection destination member 47 (for example, a chip having a metal plug, a chip having no metal plug, or a laminated wiring) A solder bump 8 is formed on the substrate), and the solder bump 8 is connected to the metal plug 4 protruding from the back surface of the silicon substrate 2.
[0161]
Also in this case, since the bumps 8 do not contact the silicon substrate 10, contamination of the silicon substrate 10 by the bumps 8 can be effectively prevented.
[0162]
(Ninth embodiment)
FIG. 20 is a schematic view showing a multichip semiconductor device according to the ninth embodiment of the present invention.
[0163]
Parts corresponding to those of the multi-chip semiconductor device of FIG. 1 are denoted by the same reference numerals as in FIG. Chip 1₁, 1₂, 1_ThreeIn FIG. 5, the multilayer wiring layer 3, the insulating films 5 and 7, the pad 6, and the like are omitted. Chip 1_ThreeMay or may not have the metal plug 4.
[0164]
This embodiment is an example using a TAB tape as a mounting member. In the figure, reference numeral 43 denotes a plastic tape, and 44 denotes a lead terminal. FIG. 21 is a schematic diagram of a conventional multichip semiconductor device using a TAB tape. From the figure, it can be seen that the planar area is larger than that of the present embodiment.
[0165]
According to the present embodiment, in addition to the effect that chips can be stacked and the planar area can be reduced, all chips, some chips, or each chip can be inspected using the metal plug 4.
[0166]
If the entire apparatus is inspected, the chip 1 in the state shown in FIG.₁An inspection probe is applied to a pad (not shown) provided on the multilayer wiring layer. Chip 1₁, 1₂If the inspection₁, 1₂After connecting the chip 1₂An inspection probe is applied to a pad (not shown) provided on the multilayer wiring layer.
[0167]
(Tenth embodiment)
22 to 24 are views showing a method of manufacturing a multichip semiconductor device according to the tenth embodiment of the present invention.
[0168]
First, according to a known method, as shown in FIG. 22A, a NAND type EEPROM memory cell and a peripheral element (not shown) are formed on a silicon substrate 50, and then a first interlayer insulating film 56 is formed.
[0169]
In the figure, 51 is a tunnel oxide film, 52_FIs a floating gate electrode, 53 is an insulating film between gate electrodes, 52_CDenotes a control gate electrode, 54 denotes a source diffusion layer, and 55 denotes a drain diffusion layer. Although a plurality of memory cells are actually formed, only one memory cell is shown in the figure for simplicity.
[0170]
Next, as shown in FIG. 6A, after forming a contact hole in the first interlayer insulating film 56, a Ti / TiN laminated film 57 and a W bit line plug 58 are formed.
[0171]
Specifically, first, a contact hole is formed, then a Ti film and a TiN film are sequentially formed on the entire surface, and then a W film is formed on the entire surface by using a blanket CVD method. Finally, the W film, the Ti film, and the TiN film outside the contact hole are removed using the CMP method.
[0172]
Next, as shown in FIG. 22B, a mask pattern 59 made of Al, for example, is formed on the first interlayer insulating film 56, and the mask pattern 59 is used as a mask to form a first region in a region where a connection plug is to be formed. By etching the interlayer insulating film 56 and the silicon substrate 50, a hole 60 having a depth of 150 to 200 μm and a square of 100 μm × 100 μm is formed. Thereafter, the mask pattern 59 is removed.
[0173]
Next, as shown in FIG. 22C, SiO covering the inside of the hole 60 is formed.₂A film 61 is formed, a polycrystalline silicon film 62 having a thickness of 500 nm as an adhesion film is formed thereon, and then a Ni film 63 as a metal plug is embedded in the hole 60.
[0174]
Specifically, a 500 nm thick SiO₂A film 61, a polycrystalline silicon film 62 having a thickness of 500 nm, and a Ni film 63 are sequentially formed on the entire surface, and then excess SiO outside the hole 60 is formed by CMP.₂The film 61, the polycrystalline silicon film 62, and the Ni film 63 are removed.
[0175]
The Ni film 63 is formed by, for example, embedding the Ni paste in the hole 60 using a screen printing method and then sintering the Ni paste by heat treatment at 600 ° C.
[0176]
Next, as shown in FIG. 23D, a bit line 64 and a first wiring layer 65 are formed according to a known method.
[0177]
Specifically, for example, a bit film 64, a Ti film having a thickness of 10 nm, a TiN film having a thickness of 10 nm, an AlCu film having a thickness of 400 nm, and a TiN film having a thickness of 40 nm are formed as the first wiring layer 65. After that, the laminated film is formed by processing using photolithography and etching.
[0178]
Next, as shown in FIG. 6D, a second interlayer insulating film 66 is formed, a via hole is formed in the second interlayer insulating film 66, and then the first wiring layer 65 is connected via a plug 67. A second wiring layer 68 connected to is formed.
[0179]
The formation method of the second wiring layer 68 is the same as that of the first wiring layer 65. As the plug 67, for example, a W film is used. Note that the second wiring layer in the memory cell region is omitted.
[0180]
Next, as shown in FIG. 4D, after forming a photosensitive polyimide film 69 having a thickness of 450 nm as a passivation film covering the second wiring layer 68 by using the plasma CVD method, photolithography and etching are performed. Using this, an opening (pad hole) is formed on the second wiring layer 68. Thereafter, it is desirable to apply a probe to a pad (not shown) to determine whether each chip formed on the wafer is non-defective or defective.
[0181]
Next, as shown in FIG. 23E, the back surface of the silicon substrate 50 is mechanically polished to expose the Ni film 63.
[0182]
This polishing step is preferably performed after the silicon substrate 50 is cut out from the wafer. This is because, as described above, uniform polishing is difficult in the wafer state. Thereafter, damage caused by polishing is removed by wet etching. It is preferable that a shallow scribe line is placed in advance on the front surface of the wafer so that chip division is automatically performed when the wafer is thinned by polishing the back surface.
[0183]
Next, as shown in FIG. 23F, after forming the Au ball bump 70 on the second wiring layer 68, the solder 71 is formed on the Au ball bump 70 by using a transfer method. At this time, when a good chip is known in advance by probe measurement, the yield and production efficiency can be improved by forming the Au ball bump 70 only on the good chip.
[0184]
Finally, as shown in FIG. 24, after positioning the solder 71 (Au ball bump 70) and the Ni film (metal plug) 63, the solder 71 and the Ni film (metal plug) 63 are connected, By connecting the silicon substrates 50 to each other, an EEPROM multi-chip semiconductor device is completed. Thereafter, the electrical characteristics are evaluated. If the stacked chips are defective, the solder 71 is heated to the melt temperature to disconnect the chips and replace the defective chips with non-defective chips.
[0185]
In the present embodiment, the NAND-type EEPROM multi-chip semiconductor device has been described. However, a NOR-type EEPROM multi-chip semiconductor device and a DRAM multi-chip semiconductor device can also be manufactured by the same method as the present embodiment. . Furthermore, a multi-chip semiconductor device of an information processing apparatus such as a personal computer constituted by an EEPROM, DRAM or other semiconductor memory or a combination thereof and a CPU can be manufactured.
[0186]
【The invention's effect】
As described in detail above, according to the present invention (Claims 1 and 2), at least one chip has a structure in which a connection plug made of metal is formed in a through hole that penetrates the semiconductor substrate and the interlayer insulating film. In addition, since the chip having the connection plug is electrically connected to another chip through the connection plug, the multi-chip semiconductor device having a small planar area, a simple structure, and a small thickness Can be realized.
[0187]
Further, in the present invention (claims 3 to 7), as a chip for a multi-chip semiconductor device, in a through-hole penetrating a semiconductor substrate on which an element is formed and the semiconductor substrate and an interlayer insulating film formed thereon. A structure having a connection plug formed of metal for electrically connecting to another chip is used.
[0188]
Therefore, by using the multi-chip semiconductor device chip having such a configuration, the multi-chip semiconductor device according to the present invention (claims 1 and 2) can be realized.
[0189]
Further, in the present invention (claims 8 to 12), after forming a hole that penetrates the interlayer insulating film but does not penetrate the semiconductor substrate, the semiconductor substrate is retreated from the back surface to form the through hole. Even if the original semiconductor substrate is thick, the through hole can be easily formed.
[0190]
Therefore, even if the semiconductor substrate is thick, the chip for a multichip semiconductor device according to the present invention (claims 3 to 7) can be easily formed.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a multichip semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view of a multichip semiconductor device according to a second embodiment of the present invention.
FIG. 3 is a cross-sectional view of a multichip semiconductor device according to a third embodiment of the present invention.
FIG. 4 is a process cross-sectional view of the first half showing a method for forming a chip for a multi-chip semiconductor device according to a fourth embodiment of the present invention;
FIG. 5 is a process cross-sectional view in the latter half showing a method for forming a chip for a multi-chip semiconductor device according to a fourth embodiment of the present invention;
FIG. 6 is a cross-sectional view showing a specific structure example of a multilayer wiring layer in a hole region
FIG. 7 is a cross-sectional view showing a specific structural example of a multilayer wiring layer in an element region.
FIG. 8 is a cross-sectional view showing a through plug
FIG. 9 is a process sectional view showing another method for forming holes.
FIG. 10 is a sectional view showing another method for forming a metal plug.
FIG. 11 is a cross-sectional view showing still another method for forming a metal plug.
FIG. 12 is a process cross-sectional view illustrating another method for forming a connection plug.
FIG. 13 is a cross-sectional view showing another connection structure of a multichip.
FIG. 14 is a process cross-sectional view of the first half showing still another method for connecting plugs.
FIG. 15 is a process cross-sectional view in the latter half showing still another method for connecting plugs.
FIG. 16 is a cross-sectional view showing a method for forming a chip for a multichip semiconductor device according to a fifth embodiment of the present invention;
FIG. 17 is a cross-sectional view of a multichip semiconductor device according to a sixth embodiment of the present invention.
FIG. 18 is a cross-sectional view of a multichip semiconductor device according to a seventh embodiment of the present invention.
FIG. 19 is a view showing the method for manufacturing the multichip semiconductor device according to the eighth embodiment of the invention.
FIG. 20 is a schematic view showing a multichip semiconductor device according to a ninth embodiment of the present invention.
FIG. 21 is a schematic diagram showing a conventional multichip semiconductor device using a TAB tape.
FIG. 22 is a process cross-sectional view of the first half showing a method for manufacturing a multichip semiconductor device according to a tenth embodiment of the present invention;
FIG. 23 is a process cross-sectional view in the latter half showing the method for manufacturing a multichip semiconductor device according to the tenth embodiment of the present invention;
FIG. 24 is a cross-sectional view showing the method for manufacturing the multichip semiconductor device according to the tenth embodiment of the invention.
FIG. 25 is a cross-sectional view of a conventional multichip semiconductor device.
FIG. 26 is a cross-sectional view of another conventional multichip semiconductor device.
FIG. 27 is a sectional view of still another conventional multi-chip semiconductor device.
[Explanation of symbols]
1₁, 1₂, 1_Three... chip
2 ... Silicon substrate
3 ... Multilayer wiring layer
4. Metal film (metal plug)
5 ... Insulating film
6 ... Pad
7 ... Insulating film
7a ... Insulating film
8 ... Solder bump (connection member)
8d ... Dummy bump
9 ... Laminated wiring board (mounting member)
10 ... Silicon substrate
11: First interlayer insulating film
11a: second interlayer insulating film
11b ... third interlayer insulating film
11c ... fourth interlayer insulating film
11n: nth interlayer insulating film
12 ... Mask pattern
12a ... Mask pattern
13, 13₁~ 13_Three... Hole (through hole)
14: Multilayer insulating film (first insulating film)
15 ... Metal film (metal plug)
16 ... Multilayer wiring structure
17 ... Pad
18 ... SiO₂Film (second insulating film)
19 ... Metal wiring
19a ... 1st metal wiring
19b ... second metal wiring
20a ... 1st metal wiring
20b ... second metal wiring
20c ... Third metal wiring
21 ... metal
22 ... Metal silicide film
23 ... Conductive paste
24 ... Metal particles
25 ... Silicon film
26. Metal silicide film
27 ... Silicon film
28 ... Ni grains
29 ... Nickel silicide film
30 ... Cap membrane
31 ... SOG film
32 ... FOX membrane
33 ... Pad
34 ... Metal balls
35 ... Board
36 ... Groove
37 ... Metal balls
38 ... Adhesive film
39 ... Radiating fins
40 ... Adhesive
41. Insulating film
42 ... Solder
43 ... plastic tape
44 ... Lead terminal
45 ... Cap metal film
46. Cap insulating film
47 ... Member of connection destination
50 ... Silicon substrate
51. Tunnel oxide film
52_F... Floating gate electrode
53_C... Control gate electrode
53. Insulating film between gate electrodes
54 ... Source diffusion layer
55 ... Drain diffusion layer
56... First interlayer insulating film
57 ... Ti / TiN laminated film
58 ... W bit line plug
59 ... Mask pattern
60 ... hole
61 ... SiO₂film
62 ... polycrystalline silicon film
63 ... Ni film
64: Bit line
65: First wiring layer
66. Second interlayer insulating film
67 ... Plug
68. Second wiring layer
69 ... Polyimide film
70 ... Au ball bump

Claims (5)

A semiconductor substrate with integrated elements formed on the surface;
An interlayer insulating film formed on the surface of the semiconductor substrate;
The interlayer insulating film and a through-hole penetrating the semiconductor substrate, and comprising a connection plug made of metal for electrically connecting to another chip,
The connection plug is provided in the through hole and has a metal plug having a hollow portion, an insulating film provided between the metal plug and a side wall of the through hole, and provided in the hollow portion. A chip for a multi-chip semiconductor device, comprising a low-stress film having a difference in thermal expansion coefficient from that of a substrate that is smaller than that of the metal plug. A semiconductor substrate with integrated elements formed on the surface;
An interlayer insulating film formed on the surface of the semiconductor substrate;
The interlayer insulating film and a through-hole penetrating the semiconductor substrate, and comprising a connection plug made of metal for electrically connecting to another chip,
The connection plug is composed of a metal plug provided up to an intermediate depth of the through hole on the semiconductor substrate surface side, and an insulating film provided between the metal plug and a side wall of the through hole, A chip for a multi-chip semiconductor device, wherein a connection member for electrically connecting to another chip is provided in an unfilled portion of the through hole. A step of integrally forming elements on a semiconductor substrate surface;
Forming an interlayer insulating film on the surface of the semiconductor substrate;
Etching the interlayer insulating film and the semiconductor substrate, forming a hole penetrating the interlayer insulating film and not penetrating the semiconductor substrate;
Forming a first insulating film having a thickness not filling the hole on the side wall and bottom of the hole;
Filling the hole covered with the first insulating film with a metal as a metal plug;
Retreating the semiconductor substrate from the backside of the semiconductor substrate until the first insulating film at the bottom of the hole is exposed;
Selectively etching the semiconductor substrate on the bottom side of the hole until the first insulating film on the sidewall of the hole is exposed above the first insulating film on the bottom of the hole;
Forming a second insulating film on the entire back surface of the semiconductor substrate on the bottom side of the hole;
The first and second insulating films are retracted until the metal plug at the bottom of the hole is exposed, and the second insulating film is selectively left on the back surface of the semiconductor substrate on the bottom of the hole. And a method of forming a chip for a multichip semiconductor device. 4. The method of forming a chip for a multi-chip semiconductor device according to claim 3, wherein the hole is formed before forming a wiring layer having the lowest melting point among wiring layers formed on the semiconductor substrate. . 4. The method of forming a chip for a multi-chip semiconductor device according to claim 3, wherein the semiconductor substrate is retracted after the semiconductor substrate is cut out from the wafer.

Images