JP5003067B2 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stably bridge electrodes provided on different semiconductor chips. <P>SOLUTION: The semiconductor device 100 comprises a first semiconductor chip 125 having a first semiconductor chip coat 196 on the surface thereof, a second semiconductor chip 131 having a second semiconductor chip coat 198 on the surface thereof and adhesive tape 181 provided so as to be contacted with the surfaces of these chips. The first semiconductor chip 125 and the second semiconductor chip 131 are provided respectively with a first recess 192 and a second recess 194 while the bottoms of the first recess 192 and the second recess 194 are constituted respectively of a first electrode 191 and a second electrode 193. A plurality of conductive particles 183 in the adhesive tape 181 comprise first conductive particles 183a contacted with the first electrode 191 as well as the second electrode 193 and second conductive particles 183b having substantially the same grain sizes as the first conductive particles 183a and fallen into the first semiconductor chip coat 196 as well as the second semiconductor chip coat 198. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  With recent demands for higher functionality and lighter, thinner and smaller electronic devices, electronic components have been increasingly integrated and densely packaged. Semiconductor packages used in these electronic devices have been reduced in size and increased in pin count, and mounting substrates on which electronic components including the semiconductor package are mounted have also been reduced in size.

  A package-on-package (POP) structure has been proposed as a semiconductor package that realizes high-density mounting (Patent Document 1). In Patent Document 1, a bump electrode is provided on a mounting substrate on which one semiconductor chip is mounted, and a substrate on which the other semiconductor chip is mounted is disposed on the bump electrode. Thereby, each of the two semiconductor chips is electrically connected to the mounting substrate.

On the other hand, as a technique for connecting between substrates provided with electrodes, there is a technique using an anisotropic conductive film (ACF) (Patent Document 2). In Patent Document 2, the electrodes that protrude from the bonding surface of the substrate are opposed to each other, and the electrodes are connected by conductive particles in the anisotropic conductive film.
JP-A-7-183426 JP-A-5-190014

  In the POP structure described above, when an electrode provided on one semiconductor chip is electrically connected to an electrode provided on the other semiconductor chip, the other semiconductor chip is connected to the other via a mounting substrate, a bump electrode, and the substrate. A configuration for connection to a semiconductor chip is conceivable.

  However, in this case, since many members are interposed in the conduction path and the conduction path becomes long, there is room for improvement in terms of connection reliability between chips.

  As will be described later, the electrode provided on the semiconductor chip is different in the premise of the configuration from the electrode provided on the substrate provided for adhesion by the anisotropic conductive film. For this reason, the connection method between the substrates using the anisotropic conductive film cannot be applied as it is to the connection between the semiconductor chips.

  The present invention has been made in view of the above circumstances, and provides a technique for reliably connecting electrodes provided on different semiconductor chips.

According to the present invention,
A first semiconductor chip having a first insulating film and a first electrode on the surface;
A second semiconductor chip having a second insulating film and a second electrode on the surface;
Including
The first insulating film covers a part of the surface of the first semiconductor chip, and in the uncovered region of the first insulating film, the surface of the first semiconductor chip is more than the surface of the first insulating film. Also retracted to the first semiconductor chip side and the first electrode is provided,
The second insulating film covers a part of the surface of the second semiconductor chip, and in the uncovered region of the second insulating film, on the surface of the second semiconductor chip, from the surface of the second insulating film Also retracted to the second semiconductor chip side and the second electrode is provided,
The first semiconductor chip and the second semiconductor chip are opposed to each other with the first insulating film and the second insulating film inside, and the first electrode and the second electrode are opposed to each other. It is bonded via an adhesive tape,
The adhesive tape includes a first resin and a plurality of conductive particles present in the first resin,
The plurality of conductive particles are
A first conductive particle in a region where the first and second electrodes face each other, and in contact with these electrodes;
The first conductive particles have substantially the same particle size, the first and second insulating films are in regions facing each other, and are indented into at least one of the first and second insulating films. Second conductive particles having,
A semiconductor device is provided.

  In the present invention, the adhesive tape includes first and second conductive particles having substantially the same particle size. And since the 2nd electroconductive particle is invaginated in the 1st or 2nd insulating film, it is the 1st electrode and the 1st electrode to such an extent that the 1st electrode and the 2nd electrode contact common 1st electroconductive particle. The distance from the second electrode is close. That is, in the present invention, each semiconductor is separated from the surface of the insulating film by the cooperative action of the intrusion of the second conductive particles into the insulating film and the contact of the first conductive particles with the first and second electrodes. A pair of electrodes provided so as to recede to the chip side is reliably electrically connected via one first conductive particle.

  In the present invention, the electrodes provided on the semiconductor chip are connected. For this reason, as described above, the premise of the configuration is different from the case where the electrodes provided on the substrate are connected. This point will be further described below with reference to FIGS. 8 (a) and 8 (b).

  FIG. 8A is a cross-sectional view showing a connection structure between electrodes provided on a substrate. In FIG. 8A, the electrode forming surfaces of the first substrate 201 and the second substrate 211 are bonded to each other with an adhesive tape 281. In the adhesive tape 281, a plurality of conductive particles 283 are dispersed in the resin layer 289. A first electrode 291 and a second electrode 293 are provided on the first substrate 201 and the second substrate 211, respectively, protruding toward the opposing substrates. The surface of the first electrode 291 is closer to the second semiconductor chip 231 than the surface of the first semiconductor chip 225, and the surface of the second electrode 293 is closer to the first semiconductor chip 225 than the surface of the second semiconductor chip 231. is doing.

  In FIG. 8A, the inter-substrate distance H is equal to the inter-electrode distance L. Therefore, the distance L between the electrodes is equal to the particle diameter d of the conductive particles 283, that is, one conductive particle 283 sandwiched between the first electrode 291 and the second electrode 293 is in contact with these electrodes. In the state, the electrodes are electrically connected.

  On the other hand, in the present invention, the first and second recesses are provided on the surfaces of the first and second semiconductor chips, respectively, and these recesses are constituted by the first and second electrodes, respectively. ing.

  FIG. 8B is a cross-sectional view showing the configuration of such a semiconductor chip. In FIG. 8B, the first semiconductor chip 225 and the second semiconductor chip 231 have a first insulating film 296 and a second insulating film 298 on their surfaces, respectively. A first recess 292 and a second recess 294 are provided on the surfaces of the first semiconductor chip 225 and the second semiconductor chip 231, respectively. Moreover, the bottom part of these recessed parts is comprised by the 1st electrode 291 and the 2nd electrode 293, respectively. The surface of the first electrode 291 is farther from the second semiconductor chip 231 than the surface of the first insulating film 296, and the surface of the second electrode 293 is farther from the first semiconductor chip 225 than the surface of the second insulating film 298. The arrangement of electrodes to be connected is different from that shown in FIG.

  In this case, the inter-chip distance h is equal to the distance between the insulating films, and the inter-electrode distance L is larger than the inter-chip distance h. For this reason, in FIG. 8B, when it is assumed that the semiconductor chips are bonded to each other using the adhesive tape 281 similarly to FIG. 8A, the conductive particles 283 have the first insulating film 296 and the first insulating film 296. It is considered that the two insulating films 298 are bonded in contact with each other. Even if the conductive particles 283 existing in the region facing the first insulating film 296 and the second insulating film 298 may unintentionally intrude into these insulating films, the first electrode 291 and The second electrode 293 is not in contact with the common conductive particles 283.

  In contrast, in the present invention, since the second conductive particles are intentionally intruded into the first and second insulating films, the first and second electrodes are outside the semiconductor device. Unlike the configuration shown in FIG. 8B, a configuration in which the electrodes are in contact with one first conductive particle is realized, although the configuration is retracted. Therefore, according to the present invention, the first and second electrodes can be reliably electrically connected via the single first conductive particle.

  By the way, the connection structure between the semiconductor chips found in the present invention, that is, the configuration in which the second conductive particles are indented into the first or second insulating film has been difficult to obtain by the conventional manufacturing method. In the present invention, when connecting the semiconductor chips, the material of the first and second insulating films and the material of the conductive particles are selected and the bonding is performed under predetermined conditions. It was found that a structure can be obtained. For example, by setting the elastic modulus relationship between the first and second insulating films and the conductive particles at the bonding temperature between the first semiconductor chip and the second semiconductor chip, the second conductive particles fall into the insulating film. It became possible to enter. This point will be described more specifically in the embodiments and examples described later.

  It should be noted that any combination of these components, or a conversion of the expression of the present invention between a method, an apparatus, and the like is also effective as an aspect of the present invention.

For example, according to the present invention,
A method for manufacturing the semiconductor device, comprising:
Preparing the first semiconductor chip, the second semiconductor chip and the adhesive tape;
With the surface of the first semiconductor chip in contact with one surface of the adhesive tape and the surface of the second semiconductor chip in contact with the other surface of the adhesive tape, A second semiconductor chip and the adhesive tape are pressure-bonded to bring the first conductive particles into contact with the first and second electrodes, and the second conductive particles are placed in the first and second insulating films. The invading process,
A method for manufacturing a semiconductor device is provided.

  As described above, according to the present invention, the plurality of conductive particles in the adhesive tape are in a region where the first and second electrodes face each other, and the first conductive particles in contact with these electrodes and The first conductive particles have substantially the same particle size, the first and second insulating films are in regions facing each other, and are indented into at least one of the first and second insulating films. Since the two conductive particles are included, the electrodes provided on different semiconductor chips can be reliably connected.

  Embodiments of the present invention will be described below with reference to the drawings. In all the drawings, common constituent elements are denoted by the same reference numerals, and description thereof is omitted as appropriate.

(First embodiment)
FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device of this embodiment.
The semiconductor device 100 illustrated in FIG. 1 includes a first semiconductor chip 125, a second semiconductor chip 131, and an adhesive tape 181.

  The first semiconductor chip 125 has a first insulating film (first semiconductor chip coat 196) and a first electrode 191 on the surface. The first semiconductor chip coat 196 is an insulating film that covers a part of the surface of the first semiconductor chip 125. A first recess 192 is provided in the first semiconductor chip 125, and the bottom of the first recess 192 is constituted by the first electrode 191. The first recess 192 is an uncovered region of the first semiconductor chip coat 196. In the first recess 192, the first semiconductor chip coat 196 is selectively removed and opened. Further, the side surface of the first recess 192 is constituted by the first semiconductor chip coat 196. The first semiconductor chip coat 196 is provided from a region where the first electrode 191 is not formed to a region where the first electrode 191 is formed.

  The first electrode 191 is provided on the surface of the first semiconductor chip 125 in the uncovered region of the first semiconductor chip coat 196. The surface of the first electrode 191 is provided so as to recede from the surface of the first semiconductor chip coat 196 to the first semiconductor chip 125 side.

  The second semiconductor chip 131 has a second insulating film (second semiconductor chip coat 198) and a second electrode 193 on the surface. The second semiconductor chip coat 198 is an insulating film that covers a part of the surface of the second semiconductor chip 131. A second recess 194 is provided in the second semiconductor chip 131, and the bottom of the second recess 194 is constituted by the second electrode 193. The second recess 194 is an uncovered region of the second semiconductor chip coat 198. In the second recess 194, the second semiconductor chip coat 198 is selectively removed and opened. Further, the side surface of the second recess 194 is constituted by the second semiconductor chip coat 198. The second semiconductor chip coat 198 is provided from a region where the second electrode 193 is not formed to a region where the second electrode 193 is formed.

  The second electrode 193 is provided on the surface of the second semiconductor chip 131 in the uncovered region of the second semiconductor chip coat 198. The surface of the second electrode 193 is provided so as to recede from the surface of the second semiconductor chip coat 198 to the second semiconductor chip 131 side.

  In addition, in FIG. 1, although the 1st electrode 191 comprised the whole bottom part of the 1st recessed part 192, and the 2nd electrode 193 illustrated the whole bottom part of the 2nd recessed part 194, these electrodes illustrated, What is necessary is just to comprise at least one part of a recessed part.

  1 illustrates a configuration in which one opposing region between the first concave portion 192 and the second concave portion 194 is provided in the semiconductor device 100, but the opposing region of the concave portion is a predetermined position of the semiconductor device 100. A predetermined number can be provided.

  The planar shape of the first recess 192 and the second recess 194 is not particularly limited, but is, for example, circular. At this time, the diameter of the first recess 192 and the second recess 194 in plan view, that is, the opening pad diameter of the first electrode 191 and the second electrode 193 is appropriately set according to the size of the conductive particles 183, For example, it is 0.5 μm or more and 100 μm or less. Further, the distance between the opening pads of the first electrode 191 and the second electrode 193 is, for example, 1 μm or more and 200 μm or less. Here, the opening pad interval refers to the distance between the centers of adjacent electrodes.

  The first semiconductor chip 125 and the second semiconductor chip 131 are opposed to each other with the first semiconductor chip coat 196 and the second semiconductor chip coat 198 inward, and the first electrode 191 constituting the bottom of the first recess 192. The second electrode 193 constituting the bottom of the second recess 194 is bonded to the second recess 194 via an adhesive tape 181. In the present embodiment, the surface of the first semiconductor chip 125 and the surface of the second semiconductor chip 131 are both element forming surfaces, and the semiconductor chips are bonded in a state where the element forming surfaces face each other inward. Yes.

  The first semiconductor chip coat 196 and the second semiconductor chip coat 198 function as, for example, a passivation film. The material of the first semiconductor chip coat 196 and the second semiconductor chip coat 198 can be used as a coating material in a semiconductor chip, for example. Here, both the first semiconductor chip coat 196 and the second semiconductor chip coat 198 are made of an organic resin material. Specific examples of the organic resin material include polyimide (PI), polybenzoxazole (PBO), polybenzocyclobutene (BCB), cyclic olefins such as norbornene, and the like, and at least one selected from these groups The above can be used.

  The thicknesses of the first semiconductor chip coat 196 and the second semiconductor chip coat 198 are set according to the conductive particles 183 and the like, for example, 3 μm or more and 15 μm or less.

Next, the adhesive tape 181 will be described.
The adhesive tape 181 is provided between the first electrode 191 and the second electrode 193, and is provided in contact with the surface of the first electrode 191 and the surface of the second electrode 193. The adhesive tape 181 includes a first resin (resin layer 189) and a plurality of conductive particles 183 present in the resin layer 189.

  The plurality of conductive particles 183 include first conductive particles 183a and second conductive particles 183b.

  The second conductive particles 183b have substantially the same particle size as the first conductive particles 183a. Here, the fact that the first conductive particles 183a and the second conductive particles 183b have substantially the same particle diameter means that a plurality of opposing regions of the first recess 192 and the second recess 194 are provided in the semiconductor device 100. Even in such a case, the first electrode 191 and the second electrode 193 have the same particle size so that the first conductive particles 183a can be stably connected in each facing region, and about plus or minus 5%. Variations in particle size are acceptable. For example, when the average particle size of the first conductive particles 183a and the second conductive particles 183b is 2 μm, the particle size may be about 1.9 to 2.1 μm.

  The particle diameters of the first conductive particles 183a and the second conductive particles 183b are larger than the sum of the depth of the first recess 192 and the depth of the second recess 194. As a result, the first conductive particles 183a constitute the first recesses 192 and the bottoms of the second recesses 194 in a state where the second conductive particles 183b are indented into the first semiconductor chip coat 196 or the second semiconductor chip coat 198. The first electrode 191 and the second electrode 193 can be further reliably brought into contact with each other.

  Moreover, although there is no restriction | limiting in particular in the upper limit of the particle size of the 1st electroconductive particle 183a and the 2nd electroconductive particle 183b, From a viewpoint of suppressing the short circuit defect between adjacent electrodes, it shall be 100 micrometers or less, for example.

  The first conductive particles 183a are in a region where the first electrode 191 and the second electrode 193 are opposed to each other (hereinafter also referred to as a first region), and are in contact with these electrodes.

  The second conductive particles 183b are in a region (hereinafter also referred to as a second region) where the first semiconductor chip coat 196 and the second semiconductor chip coat 198 are opposed to each other, and the first semiconductor chip coat 196 and the second semiconductor chip coat 196b. At least one of the semiconductor chip coats 198 is recessed.

Further, the plurality of conductive particles 183 are present in the first and second regions as follows.
That is, in the first region, a part of the plurality of conductive particles 183, that is, the first conductive particles 183 a are present in a form in contact with the first electrode 191 and the second electrode 193. Thereby, the first electrode 191 and the second electrode 193 are electrically connected. One first conductive particle 183a exists in one first region. Further, a pair of electrodes are connected by a single first conductive particle 183a in the stacking direction.

In the second region, a part of the plurality of conductive particles 183, that is, the second conductive particles 183b are present in the form (i) or (ii) below.
(I) Part of the particles is invaded in one of the first semiconductor chip coat 196 and the second semiconductor chip coat 198.
(Ii) Part of the particles is indented in both the first semiconductor chip coat 196 and the second semiconductor chip coat 198.
In addition, in FIG. 1, the structure of said (ii) is illustrated.

  The plurality of conductive particles 183 include core particles 185 made of the second resin and a conductive layer (metal layer 187) that covers the outside of the core particles 185.

  As a material of the second resin, for example, epoxy resin, urethane resin, melamine resin, phenol resin, divinylbenzene copolymer, styrene-divinylbenzene copolymer, (meth) acrylate-divinylbenzene copolymer, (meth) acrylate Examples thereof include organic substances such as copolymers, styrene resins, styrene-butadiene copolymers, and benzoguanamine resins, and inorganic substances such as silica. Among them, in consideration of the indentation to the insulating film and the elasticity that can follow the loosening of the adhesive resin, divinylbenzene copolymer, (meth) acrylate-divinylbenzene copolymer, (meth) acrylate copolymer, benzoguanamine Resins are preferred. The core particle 185 may be hollow or solid.

  The metal layer 187 covers the entire surface of the core particle 185. The metal layer 187 may be a plating layer, for example.

  In addition, in the adhesive tape 181, the blending ratio of the conductive particles 183 is 0.1% by volume or more, preferably 1% by volume or more with respect to components other than the conductive particles 183 from the viewpoint of improving connection reliability. . Further, from the viewpoint of improving the film formability of the adhesive tape, the content is 10% by volume or less, preferably 5% by volume or less, with respect to components other than the conductive particles 183 in the adhesive tape.

  The material of the resin layer 189 of the adhesive tape 181 is not particularly limited, and a thermoplastic resin, a thermosetting resin, or a mixed system of a thermoplastic resin and a thermosetting resin is used. Among these, a mixed system of a thermoplastic resin and a thermosetting resin is preferable from the viewpoint of film formability and melt viscosity of the resin. More specifically, the material of the resin layer 189 may include an epoxy resin and acrylic rubber.

  The thermoplastic resin is not particularly limited. For example, phenoxy resin, polyester resin, polyurethane resin, polyimide resin, siloxane-modified polyimide resin, polybutadiene, polypropylene, styrene-butadiene-styrene copolymer, styrene-ethylene- Butylene-styrene copolymer, polyacetal resin, polyvinyl butyral resin, polyvinyl acetal resin, butyl rubber, chloroprene rubber, polyamide resin, acrylonitrile-butadiene copolymer, acrylonitrile-butadiene-acrylic acid copolymer, acrylonitrile-butadiene-styrene copolymer Coalescence, polyvinyl acetate, nylon, acrylic rubber, etc. can be used. These can be used individually or in mixture of 2 or more types.

  The thermoplastic resin may be one having a nitrile group, an epoxy group, a hydroxyl group, or a carboxyl group for the purpose of improving adhesiveness or compatibility with other resins. As such a resin, for example, Acrylic rubber can be used.

  Although it does not restrict | limit especially as a thermosetting resin, An epoxy resin, oxetane resin, a phenol resin, (meth) acrylate resin, unsaturated polyester resin, diallyl phthalate resin, maleimide resin etc. are used. Among them, an epoxy resin excellent in curability and storage stability, heat resistance, moisture resistance, and chemical resistance of a cured product is preferably used.

  As the epoxy resin, any one of an epoxy resin solid at room temperature and an epoxy resin liquid at room temperature may be used. The resin may include an epoxy resin that is solid at room temperature and an epoxy resin that is liquid at room temperature. Thereby, the freedom degree of design of the melting behavior of resin which comprises the resin layer 189 can further be raised.

  The epoxy resin that is solid at room temperature is not particularly limited, and is not limited to bisphenol A type epoxy resin, bisphenol S type epoxy resin, phenol novolac type epoxy resin, cresol novolac type epoxy resin, glycidylamine type epoxy resin, glycidyl ester type. An epoxy resin, a trifunctional epoxy resin, a tetrafunctional epoxy resin, etc. are mentioned. More specifically, a solid trifunctional epoxy resin and a cresol novolac type epoxy resin may be included.

  The epoxy resin that is liquid at room temperature can be a bisphenol A type epoxy resin or a bisphenol F type epoxy resin. Moreover, you may use combining these.

  In addition, when the resin layer 189 includes acrylic rubber, film formation stability when a film-like adhesive tape is manufactured can be improved. In addition, since the elastic modulus of the adhesive tape can be reduced and the residual stress between the adherend and the adhesive tape can be reduced, the adhesion to the adherend can be improved.

  In the adhesive tape 181, the compounding ratio of the resin is, for example, 10% by weight to 50% by weight of acrylic rubber with respect to the total of the constituent components of the adhesive tape 181 excluding the conductive particles 183. By setting the blending ratio of the acrylic rubber to 10% by weight or more, the decrease in film formability is suppressed, and further, the increase in the elastic modulus after curing of the adhesive tape is suppressed, so that the adhesion to the adherend is improved. Further improvement can be achieved. In addition, when the blending ratio of the acrylic rubber is 50% by weight or less, an increase in the melt viscosity of the resin is suppressed, and the conductive particles 183 can be more reliably brought into contact with the surface of the conductive member.

  Moreover, the compounding ratio of the epoxy resin is, for example, 20 wt% or more and 80 wt% or less with respect to the total of the constituent components of the adhesive tape 181 excluding the conductive particles 183. By setting the blending ratio of the epoxy resin to 20% by weight or more, it is possible to further sufficiently secure the elastic modulus after bonding and improve the connection reliability. Moreover, since the melt viscosity can be further increased by setting the compounding ratio of the epoxy resin to 80% by weight or less, the first conductive particles 183a and the second conductive particles 183b are disposed in the first region and the second region, respectively. It can exist more reliably in the two regions.

  The adhesive tape 181 may further include a curing agent in the resin layer 189, and may include a resin that functions as a curing agent.

  The curing agent is not particularly limited, and examples thereof include phenols, amines, and thiols. In view of reactivity with the epoxy resin and physical properties after curing, phenols are preferably used.

  Although it does not specifically limit as phenols, When the physical property after hardening of an adhesive tape is considered, bifunctional or more is preferable. Examples include bisphenol A, tetramethylbisphenol A, diallyl bisphenol A, biphenol, bisphenol F, diallyl bisphenol F, trisphenol, tetrakisphenol, phenol novolacs, cresol novolacs, etc., but melt viscosity, reaction with epoxy resin When considering the properties and physical properties after curing, phenol novolacs and cresol novolacs can be preferably used.

  Further, the blending amount of the curing agent is, for example, 5% by weight or more, preferably 10% by weight from the viewpoint of surely curing the resin when the total of the constituent components of the adhesive tape 181 excluding the conductive particles 183 is 100. That's it. In addition, from the viewpoint of improving the fluidity of the resin during bonding, when the total of the constituent components of the adhesive tape 181 excluding the conductive particles 183 is 100, the amount of the curing agent is, for example, 40% by weight or less, preferably 30 wt% or less.

  The adhesive tape 181 may further include a curing catalyst in the resin layer 189. By setting it as the structure containing a curing catalyst, resin can be hardened more reliably at the time of preparation of an adhesive tape.

  Although a curing catalyst can be suitably selected according to the kind of resin, For example, an imidazole compound whose melting | fusing point is 150 degreeC or more can be used. If the melting point of the imidazole compound is too low, there is a concern that the resin of the adhesive tape 181 is cured before the conductive particles 183 come into contact with the electrode surface and the connection becomes unstable or the storage stability of the adhesive tape 181 is lowered. is there. Therefore, the melting point of imidazole is preferably 150 ° C. or higher. Examples of the imidazole compound having a melting point of 150 ° C. or higher include 2-phenylhydroxyimidazole and 2-phenyl-4-methylhydroxyimidazole. In addition, there is no restriction | limiting in particular in the upper limit of melting | fusing point of an imidazole compound, For example, it can set suitably according to the adhesion temperature of the adhesive tape 181.

  The blending ratio of the curing catalyst is, for example, 0.01% by weight or more and 5% by weight or less when the total of the constituent components of the adhesive tape 181 excluding the conductive particles 183 is 100. By setting the blending ratio of the curing catalyst to 0.01% by weight or more, the function of the epoxy resin as a curing catalyst can be exhibited more effectively, and the curability of the adhesive tape 181 can be improved. Moreover, the preservability of the adhesive tape 181 can be further improved by setting the blending ratio of the curing catalyst to 5% by weight or less.

  The adhesive tape 181 may further include a silane coupling agent in the resin layer 189. By setting it as the structure containing a silane coupling agent, the adhesiveness of the adhesive tape 181 with respect to the 1st semiconductor chip coat 196 and the 1st semiconductor chip coat 196 can further be improved. Examples of the silane coupling agent include an epoxy silane coupling agent and an aromatic-containing aminosilane coupling agent, and at least one of them may be included. For example, it can be set as the structure containing both of these. The compounding ratio of the silane coupling agent is, for example, 0.01 wt% or more and 5 wt% or less when the total of the constituent components of the adhesive tape 181 excluding the conductive particles 183 is 100.

  Furthermore, the adhesive tape 181 may contain components other than those described above in the resin layer 189. For example, various additives may be appropriately added in order to improve various properties such as resin compatibility, stability, and workability.

Next, a method for manufacturing the semiconductor device 100 will be described. Specifically, the manufacturing method of the semiconductor device 100 includes the following steps.
Step 11: preparing the first semiconductor chip 125, the second semiconductor chip 131 and the adhesive tape 181; and
Step 12: The surface (element forming surface) of the first semiconductor chip 125 is brought into contact with one surface of the adhesive tape 181, and the surface (element forming surface) of the second semiconductor chip 131 is contacted with the other surface of the adhesive tape 181. The first semiconductor chip 125 and the second semiconductor chip 131 and the adhesive tape 181 are pressure-bonded in the contact state, the first conductive particles 183a are brought into contact with the first electrode 191 and the second electrode 193, and the second A step of causing the conductive particles 183b to intrude into the first semiconductor chip coat 196 and the second semiconductor chip coat 198;

  In step 11, the film-like adhesive tape 181 mixes resin, conductive particles 183, and other additives as necessary, and disperses the conductive particles 183 in the resin. And it is obtained by apply | coating the obtained dispersion liquid on peeling base materials, such as a polyester sheet, and drying at predetermined temperature.

FIG. 2 is a diagram for explaining the bonding process in step 12. Figure 2 is a sectional view showing a state after the connection between the switch-up.

Incidentally, the first electrode 191 of FIG. 1 corresponds to a UBM (under bump metal) 141 definitive in FIG. The second electrode 193 of FIG. 1 corresponds to UBM143 the definitive in FIG. The UBM 141 and UBM 143 are, for example, a laminated film of Ti (base: chip contact surface side) / Cu (adhesive tape side). Alternatively, the UBM 141 and the UBM 143 may be a Cr / Ni laminated film or a Ni film.

  In step 12, the first semiconductor chip 125, the adhesive tape 181 and the second semiconductor chip 131 are laminated in this order from the bottom. At this time, the first electrode 191 provided on the surface of the first semiconductor chip 125 and the second electrode 193 provided on the surface of the second semiconductor chip 131 are opposed to each other. Then, the laminate is heated and bonded at a predetermined temperature.

  However, the structure in which the first conductive particles 183a are in contact with the first electrode 191 and the second electrode 193 and the second conductive particles 183b are recessed in the first semiconductor chip coat 196 or the second semiconductor chip coat 198 is as follows. It is difficult to obtain by the conventional method. Therefore, in this embodiment, predetermined materials are selected and used as the first semiconductor chip coat 196, the second semiconductor chip coat 198, and the resin layer 189.

Specifically, whether the conductive particles 183 intrude into the insulating film (the first semiconductor chip coat 196 or the second semiconductor chip coat 198) depends on the hardness of the conductive particles 183 at the time of thermocompression bonding. Depends on the hardness of the film,
(Hardness of conductive particles during thermocompression bonding)> (Hardness of insulating film during thermocompression bonding)
In such a case, such a condition is selected because a good connection can be obtained.

Further, as a result of further examination by the present inventors, the K value (unit: N / mm ² ) (A) of the conductive particles 183 at the press bonding temperature is used as an index indicating the hardness of the conductive particles 183 at the time of thermocompression bonding. As an index indicating the hardness of the semiconductor chip coat at the time of thermocompression bonding, the tensile elastic modulus (unit: MPa) (B) of the first semiconductor chip coat 196 or the second semiconductor chip coat 198 at the pressure bonding temperature is used.
3 <(K value of conductive particles at pressure bonding temperature (N / mm ² ): A) / (Tension elastic modulus (MPa) of semiconductor chip coat at pressure bonding temperature: B) <30,
More preferably,
5 <(A) / (B) <20,
It has been experimentally found that the first electrode 191 and the second electrode 193 are stably electrically connected with higher reliability by satisfying the condition.

  If the value of (A) / (B) is too small, there is a concern that the second conductive particles 183b may be destroyed between the opposing semiconductor chip coats. Further, there is a concern that the first semiconductor chip coat 196 and the second semiconductor chip coat 198 come into contact with each other. Thereby, the space | interval between electrodes becomes narrow, there exists a possibility that the 1st electroconductive particle 183a on an electrode may carry out plastic deformation, and connection reliability may fall.

  If the value of (A) / (B) is too large, the indentation property of the second conductive particles 183b with respect to the first semiconductor chip coat 196 or the second semiconductor chip coat 198 is too good. There is a concern of damaging the connection reliability.

  By setting the value of (A) / (B) within the above range, the second conductive particles 183b are surely intruded into the first semiconductor chip coat 196 or the second semiconductor chip coat 198, and the first electrode is between the electrodes. Connection can be ensured by the conductive particles 183a, and connection reliability can be improved.

  In addition, in the above, the definition of K value used as a parameter | index of the hardness of the electroconductive particle at the time of thermocompression bonding is as having described in patent document 2. FIG.

That is, the document describes the K value as follows.
According to the Landauri Fuschitz theory physics course "elastic theory" (Tokyo book 1972), page 42, the contact problem of two elastic spheres with radii R and R 'is given by the following equation.
h = F ^2/3 [D ² (1 / R + 1 / R ′)] ^1/3 (1)
D = (3/4) [(1-σ ² ) / E + (1-σ ′ ² ) / E ′] (2)
Here, h is the difference in distance between R + R ′ and the center of both spheres, F is the compressive force, E and E ′ are the elastic moduli of the two elastic spheres, and σ and σ ′ are the Poisson's ratio of the elastic spheres.

On the other hand, when the sphere is replaced with a rigid plate and compressed from both sides, when R ′ → ∞ (infinity), E >> E ′, the following equation is approximately obtained.
F = (2 ^1/2 / 3) (S ^3/2 ) (E · R ^1/2 ) (1-σ ² ) (3)
Here, S represents the amount of compressive deformation.

The compression hardness K is defined as follows.
K = E / (1-σ ² ) (4)

Therefore, (3) wherein represents a K value from equation K = (3 / √2) · F · S -3/2 · R -1/2 (5)
Is obtained.

This K value represents the hardness of the sphere universally and quantitatively. By using this K value, it is possible to quantitatively and uniquely represent the suitable hardness of the conductive microspheres used for the conductive connection between the fine electrodes.
In the above formula (5), R is the radius of the second conductive particle 183b. In the present embodiment, the radius of the first conductive particle 183a is equal to the radius of the second conductive particle 183b. Moreover, in this embodiment, F and S are the load value (N) and compression displacement (mm) in 10% compressive deformation of the 2nd electroconductive particle 183b, respectively.

Furthermore, the same document describes the following contents for the measurement method of the K value.
That is, the measurement of the K value is performed as follows. At room temperature, resin fine spheres are dispersed on a steel plate having a smooth surface, and one resin fine sphere is selected therefrom. Next, using a micro compression tester (for example, PCT-200 model, manufactured by Shimadzu Corporation), the resin microspheres are compressed with a smooth end surface of a diamond column having a diameter of 50 μm. At this time, the compression load is electrically detected as an electromagnetic force, and the compression displacement is electrically detected as a displacement by the operating transformer.

  And the relationship of compression displacement-load is calculated | required. From this relationship, the load value (F) and compression displacement (S) in 10% compression deformation of the resin microsphere are obtained, and the relationship between the K value and the compression strain is obtained from these values and Equation (5). It is done. However, the compressive strain is a value obtained by dividing the compression displacement by the particle diameter of the resin microsphere in%.

  In the measurement of the K value in the examples described later, as in the same document, the compression speed was the constant load speed compression method, and the load was increased at a rate of 2.6 mN per second. The maximum load was 98 mN.

  In addition to selecting a predetermined material, the relationship between the pressure bonding temperature and the elastic modulus of the first semiconductor chip coat 196 or the second semiconductor chip coat 198 is devised and selected, and the pressure bonding conditions corresponding to the selected material are selected. . By doing so, it becomes possible for the first time to obtain the structure 100 in which the first conductive particles 183a and the second conductive particles 183b are provided in the above-described form.

  For example, the second conductive particles 183b are dropped into the first semiconductor chip coat 196 or the second semiconductor chip coat 198 until the first conductive particles 183a come into contact with the first electrode 191 and the second electrode 193 at the pressure bonding temperature. The hardness of the conductive particles 183 is set to be larger than the hardness of the first semiconductor chip coat 196 or the second semiconductor chip coat 198 so as to enter.

  The adhesion temperature is set according to the physical properties of the resin layer 189 and the glass transition temperatures of the first semiconductor chip coat 196 and the second semiconductor chip coat 198. Further, the bonding temperature is set to be equal to or higher than the melting temperature of the resin layer 189. From this point of view, the bonding temperature is, for example, 180 ° C. or higher, preferably 200 ° C. or higher. Moreover, it is preferable that the melt viscosity of the resin is low at the bonding temperature. From this viewpoint, the bonding temperature is, for example, 300 ° C. or lower, preferably 280 ° C. or lower. Moreover, it is good to make adhesion temperature low from a viewpoint of expanding the area | region where the melt viscosity of resin is low. Further, the bonding temperature can be a temperature at which the element does not deteriorate depending on the elements formed on the first semiconductor chip 125 and the second semiconductor chip 131.

  Further, in the second region, the second conductive particles 183b are further intruded into the first semiconductor chip coat 196 or the second semiconductor chip coat 198 so as to bring the electrodes close to each other. . The pressurizing pressure is set to, for example, 0.1 MPa or more, preferably 1 MPa or more from the viewpoint of more reliably intruding the second conductive particles 183b into the first semiconductor chip coat 196 or the second semiconductor chip coat 198. Further, the upper limit of the pressurizing pressure can be set according to the hardness of the conductive particles 183, for example, 10 MPa or less, preferably 6 MPa or less.

  By heating, the resin in the resin layer 189 melts. In addition, the second conductive particles 183b intrude into the first semiconductor chip coat 196 or the second semiconductor chip coat 198 in the second region by pressurization. At the same time, the melted resin is discharged from the region between the first conductive particles 183 a and the first electrode 191 and the second electrode 193.

  Here, the second conductive particles 183b and the first conductive particles 183a have substantially the same particle size. For this reason, the second conductive particles 183b are recessed into the first semiconductor chip coat 196 or the second semiconductor chip coat 198 until the electrode interval L becomes equal to the particle diameter of the first conductive particles 183a. Then, the stacked body is cooled in a state where the electrode interval L is equal to the particle size of the first conductive particles 183a, that is, in a state where the first conductive particles 183a are in contact with the first electrode 191 and the second electrode 193. Thus, the resin layer 189 is cured, the electrodes are connected by the first conductive particles 183a, and the second conductive particles 183b are indented into the first semiconductor chip coat 196 or the second semiconductor chip coat 198. Is maintained.

  In the present embodiment, the plurality of conductive particles 183 includes first conductive particles 183a and second conductive particles 183b. The second conductive particles 183b are intruded into at least one of the first semiconductor chip coat 196 and the second semiconductor chip coat 198 in the second region, and the first semiconductor chip 125 and the second semiconductor chip 131 The first electrode 191 and the second electrode 193 that have receded from the element formation surface to the outside of the semiconductor device 100 are so close that they can contact the common first conductive particles 183a. For this reason, in the stacking direction of the semiconductor chip, the first electrode 191 and the second electrode 193 are reliably electrically connected via the first conductive particles 183a in the stacking direction.

  In the present embodiment, the depth of the first recess 192 is smaller than the thickness of the first semiconductor chip coat 196 in the second region, that is, the electrode non-formation region, and the depth of the second recess 194 is the second region. That is, it is smaller than the thickness of the second semiconductor chip coat 198 in the electrode non-formation region. Therefore, in a state where the first electrode 191 and the second electrode 193 are in contact with the first conductive particles 183a, the outer surface of the first semiconductor chip coat 196 and the second surface of the semiconductor device 100 are in the second region. The distance between the semiconductor chip coat 198 and the outer surface of the semiconductor device 100 is larger than the particle size of the first conductive particles 183a, and a margin is secured in the thickness direction for the amount of intrusion of the second conductive particles 183b. It becomes the composition.

  Therefore, the semiconductor device 100 has a structure in which the second conductive particles 183b are prevented from entering the outside of the semiconductor device 100 from the first semiconductor chip coat 196 or the second semiconductor chip coat 198 in the manufacturing process. It has become. For this reason, even when the element formation surfaces of the semiconductor chip are bonded facing each other inward, the second conductive particles 183b are more outside the semiconductor device 100 than the first semiconductor chip coat 196 or the second semiconductor chip coat 198. It is difficult to contact or intrude into the components arranged on the lower layer side of the semiconductor chip. For this reason, the semiconductor device 100 has a high degree of freedom in designing the lower layers of the first semiconductor chip coat 196 and the second semiconductor chip coat 198, and has a more excellent configuration due to manufacturing stability.

  Moreover, in this embodiment, the film-like adhesive tape 181 is used, and it is only necessary to perform heat treatment at a predetermined single temperature at the time of bonding, so that the semiconductor chips can be bonded easily. However, the heat treatment at the time of bonding is not limited to the treatment at a single temperature, for example, step cure that heats at 200 ° C. for 100 seconds and then heats at 250 ° C. for 100 seconds, or after thermocompression bonding at 200 ° C. for 10 seconds, You may perform the postcure which oven-cure at 10 degreeC for 10 minutes.

  In the following embodiments, specific examples of semiconductor packages using the configuration described in the first embodiment will be described.

(Second embodiment)
FIG. 3 is a cross-sectional view showing the configuration of the semiconductor device of this embodiment. The semiconductor device 110 shown in FIG. 3 has a structure in which the semiconductor device 100 described in the first embodiment is mounted on the first resin substrate 101.

  Also in the semiconductor device 110, the second semiconductor chip 131, the adhesive tape 181, and the first semiconductor chip 125 are stacked in this order, and the second electrode (not shown) in the second semiconductor chip 131 and the first semiconductor chip 125 are stacked. The first electrode (not shown) is connected via the first conductive particles (not shown) in the adhesive tape 181.

  In addition, an electrode provided on the back surface of the second semiconductor chip 131 and an electrode of the first resin substrate 101 which is a mounting substrate are connected by a wire 159. The first semiconductor chip 125, the second semiconductor chip 131, and the wire 159 are sealed with a sealing resin 163. Here, the first resin substrate 101 is formed by laminating the first resin substrate 101, the built-up 103, and the core 105, and a plurality of bump electrodes 161 are provided on the back surface of the first resin substrate 101.

  In the present embodiment, since the second semiconductor chip 131 and the first semiconductor chip 125 mounted on the first resin substrate 101 are bonded by the adhesive tape 181, the first electrode in the first semiconductor chip 125 ( (Not shown) and the second electrode (not shown) in the second semiconductor chip 131 can be reliably electrically connected through a short conduction path.

  Further, by using the adhesive tape 181, the chips can be bonded with a simple process, and the electrodes can be stably connected with high reliability.

  Further, the first semiconductor chip 125 and the first resin substrate 101 can be electrically connected without wire bonding the first electrode (not shown) in the first semiconductor chip 125 and the electrode on the first resin substrate 101. Can be connected.

(Third embodiment)
FIG. 4 is a cross-sectional view showing the configuration of the semiconductor device of this embodiment. The basic configuration of the semiconductor device 120 shown in FIG. 4 is the same as that of FIG. 3, but in FIG. 4, the second semiconductor chip 131 is flip-connected to the first resin substrate 101 as the mounting substrate via the bump electrode 165. The first semiconductor chip 125 is disposed between the first resin substrate 101 and the second semiconductor chip 131.

  Also in this embodiment, since the first semiconductor chip 125 and the second semiconductor chip 131 are bonded by the adhesive tape 181, the same effect as that of the second embodiment can be obtained.

(Fourth embodiment)
In the second and third embodiments, the entire chip mounting surface of the first resin substrate 101 may be sealed with the sealing resin 163.

5 and 6 are cross-sectional views showing the configuration of such a semiconductor device.
FIG. 5 is an example of a two-stage stack type chip-on-chip (COC) structure having the same basic configuration as FIG.

  FIG. 5 shows an example of a two-stage stack type, but the semiconductor chips may be further multi-stage stacks. FIG. 6 is an example of such a configuration.

  The basic configuration of the semiconductor device shown in FIG. 6 is the same as that in FIG. 5, but a third semiconductor chip 145 is further stacked on the first semiconductor chip 125, and the first semiconductor chip 125 and the third semiconductor chip 145 are stacked. Are different from each other by the adhesive tape 181.

  In the example of FIG. 6, the third semiconductor chip 145 is the same size as the first semiconductor chip 125, and the third semiconductor chip 145 is also embedded in the sealing resin 163.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

Example 1
(Preparation of adhesive tape)
An adhesive tape having a thickness of 40 μm containing conductive particles in the resin layer was produced.

  The constituent components and the compounding ratio of the resin layer were as shown in Table 1. In Table 1, blending is shown in parts by weight unless otherwise specified.

The following were used as the conductive particles 183.
Average particle diameter (number average particle diameter): 25 μm
Core particle 185 material: divinylbenzene copolymer metal layer 187: Ni / Au plating

  Moreover, the compounding quantity of the electroconductive particle in an adhesive tape was 2.5 vol% with respect to the total volume of the acrylic rubber, an epoxy resin, a phenol novolak, a silane coupling agent, and an imidazole in an adhesive tape.

  When the constituents of the resin layer were mixed in the formulation shown in Table 1, and the varnish obtained by dispersing the conductive particles was applied to the polyester sheet and dried at a temperature at which the organic solvent volatilized, it was good. A film-forming adhesive tape was obtained.

(Adhesion and evaluation of semiconductor chips)
Connection between the semiconductor chips shown in FIG. 7 was performed using the adhesive tape obtained above. The basic configuration of FIG 7 is similar to FIG. 2 described above. The material and configuration of the semiconductor device are as follows. Table 2 shows the configuration of the conductive particles shown in FIG.
First semiconductor chip 125 and second semiconductor chip 131: plate thickness 625 μm
First semiconductor chip coat 196: Polybenzoxazole second semiconductor chip coat 198: Polybenzoxazole first electrode 191: Ti / Cu, φ75 μm diameter second electrode 193: Ti / Cu, φ75 μm diameter first recess 192: Depth 10 μm
Second recess 194: depth 10 μm

  At the time of bonding, an adhesive tape 181 is disposed between the first semiconductor chip 125 and the second semiconductor chip 131, and a 200 μm thick silicon rubber is disposed so that pressure is uniformly applied to the upper surface of the semiconductor chip, Thermocompression bonding was performed at 250 ° C., 2 MPa, and 600 seconds.

  In addition, as an index (A) of the hardness of the conductive particles 183 at the pressure bonding temperature, the compression hardness (K value) of the conductive particles was measured by the method described above. The compression speed was a constant load speed compression method, and the load was increased at a rate of 2.6 mN per second. The maximum load was 98 mN.

  Further, as an index (B) of the hardness of the semiconductor chip coat resin at the pressure bonding temperature, the tensile modulus of the semiconductor chip coat resin is measured using a tensile tester (Tensilon RTA-100) manufactured by Orientec Co., Ltd. A tensile test (stretching speed: 8 mm / min) was performed on (3 mm × 30 mm) in an atmosphere at 250 ° C., and the elastic modulus was measured from the initial gradient of the stress-strain curve.

  The connection state of the obtained laminate was observed with an SEM (scanning electron microscope). The first semiconductor chip coat and the second semiconductor chip coat are conductive particles intruded and the conductive particles are in contact with each other between the first electrode and the second electrode. “X” indicates that the conductive particles did not intrude into the chip coat and the second semiconductor chip coat and the conductive particles were not in contact between the first electrode and the second electrode.

(Example 2)
In Example 1, the following were used as conductive particles in the adhesive tape.
Average particle diameter (number average particle diameter): 50 μm
Core particle 185 material: acrylic copolymer metal layer 187: Ni / Au plating Other than that, an adhesive tape and a semiconductor device using the same were prepared and evaluated according to the materials and methods of Example 1.

(Example 3)
In Example 1, it was set as the structure shown below and Table 2. FIG.
First semiconductor chip 125 and second semiconductor chip 131: plate thickness 625 μm
First semiconductor chip coat 196: Polybenzoxazole second semiconductor chip coat 198: Polybenzoxazole first electrode 191: Ti / Cu, φ75 μm diameter second electrode 193: Ti / Cu, φ75 μm diameter first recess 192: Depth 5 μm
Second recess 194: depth 5 μm

In Example 1, the following were used as conductive particles in the adhesive tape.
Average particle diameter (number average particle diameter): 15 μm
Core particle 185 material: divinylbenzene copolymer metal layer 187: Ni / Au plating Other than that, an adhesive tape and a semiconductor device using the same were prepared and evaluated according to the materials and methods of Example 1.

(Comparative Example 1)
In Example 1, the following were used as conductive particles in the adhesive tape.
Average particle diameter (number average particle diameter): 25 μm
Core particle material: benzoguanamine-formaldehyde cocondensate Metal layer: Ni / Au plating

  Other than that, production and evaluation of an adhesive tape and a semiconductor device using the same were performed in accordance with the materials and methods of Example 1. However, in this comparative example, the pressure bonding conditions were 180 ° C., 2 MPa, and 600 seconds.

  Under this pressure bonding condition, the conductive particles on the chip coat were pulverized without entering the semiconductor chip coat. Also, the conductive particles on the electrode were pulverized in the same manner as the conductive particles present in the semiconductor chip coat, and a good connection state could not be obtained.

It is sectional drawing which shows the structure of the semiconductor device in this embodiment. It is sectional drawing which shows the structure of the semiconductor device in this embodiment. It is sectional drawing which shows the structure of the semiconductor device in this embodiment. It is sectional drawing which shows the structure of the semiconductor device in this embodiment. It is sectional drawing which shows the structure of the semiconductor device in this embodiment. It is sectional drawing which shows the structure of the semiconductor device in this embodiment. It is sectional drawing which shows the structure of the semiconductor device in an Example. It is sectional drawing which shows the structure of a semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor device 101 1st resin board 103 Built-up 105 Core 107 Built-up 110 Semiconductor device 120 Semiconductor device 125 1st semiconductor chip 131 2nd semiconductor chip 141 1st UBM
143 Second UBM
145 Third semiconductor chip 159 Wire 161 Bump electrode 163 Sealing resin 165 Bump electrode 181 Adhesive tape 183 Conductive particle 183a First conductive particle 183b Second conductive particle 185 Core particle 187 Metal layer 189 Resin layer 191 First electrode 192 First concave portion 193 Second electrode 194 Second concave portion 196 First semiconductor chip coat 198 Second semiconductor chip coat 201 First substrate 211 Second substrate 225 First semiconductor chip 231 Second semiconductor chip 281 Adhesive tape 283 Conductive particles 289 Resin Layer 291 First electrode 292 First recess 293 Second electrode 294 Second recess 296 First insulating film 298 Second insulating film

Claims (7)

A first semiconductor chip having a first insulating film and a first electrode on the surface;
A second semiconductor chip having a second insulating film and a second electrode on the surface;
Including
The first insulating film covers a part of the surface of the first semiconductor chip, and in the uncovered region of the first insulating film, the surface of the first semiconductor chip is more than the surface of the first insulating film. Also retracted to the first semiconductor chip side and the first electrode is provided,
The second insulating film covers a part of the surface of the second semiconductor chip, and in the uncovered region of the second insulating film, on the surface of the second semiconductor chip, from the surface of the second insulating film Also retracted to the second semiconductor chip side and the second electrode is provided,
The first semiconductor chip and the second semiconductor chip are opposed to each other with the first insulating film and the second insulating film inside, and the first electrode and the second electrode are opposed to each other. It is bonded via an adhesive tape,
The adhesive tape includes a first resin and a plurality of conductive particles present in the first resin,
The plurality of conductive particles are
A first conductive particle in a region where the first and second electrodes face each other, and in contact with these electrodes;
The first conductive particles have substantially the same particle size, the first and second insulating films are in regions facing each other, and are indented into at least one of the first and second insulating films. Second conductive particles having,
A semiconductor device including: The semiconductor device according to claim 1,
A semiconductor device in which the first and second insulating films are made of an organic resin material.   3. The semiconductor device according to claim 2, wherein the organic resin material includes one or more selected from the group consisting of polyimide, polybenzoxazole, benzocyclobutene, and cyclic olefin. The semiconductor device according to claim 1,
The plurality of conductive particles, a core made of a second resin, a conductive layer covering the outside of the core,
A semiconductor device. The semiconductor device according to claim 4,
The semiconductor device in which the one surface of the first semiconductor chip and the one surface of the second semiconductor chip are both element formation surfaces. The semiconductor device according to claim 1,
The K value (N / mm ² ) represented by the following formula of the second conductive particles at the pressure bonding temperature of the adhesive tape is (A), and the tensile elastic modulus of the first or second insulating film at the pressure bonding temperature ( When (MPa) is (B),
3 <(A) / (B) <30
A semiconductor device.
K = (3 / √2) ・ F ・ S ^-3/2・ R ^-1/2
(In the above formula, F and S are the load value (N) and compression displacement (mm) in 10% compression deformation of the second conductive particles, respectively, and R is the second conductive particles) The radius of A method of manufacturing a semiconductor device according to claim 1,
Preparing the first semiconductor chip, the second semiconductor chip and the adhesive tape;
With the surface of the first semiconductor chip in contact with one surface of the adhesive tape and the surface of the second semiconductor chip in contact with the other surface of the adhesive tape, A second semiconductor chip and the adhesive tape are pressure-bonded to bring the first conductive particles into contact with the first and second electrodes, and the second conductive particles are placed in the first and second insulating films. The invading process,
A method of manufacturing a semiconductor device including:

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