JP3395747B2 - Manufacturing method of semiconductor integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to relates to a semiconductor integrated circuit, and more particularly to a method of manufacturing a semiconductor integrated circuit of the thin and, compact flip-chip structure.

[0002]

2. Description of the Related Art In order to cope with the recent increase in the number of pins of semiconductor integrated circuits (LSI) and the miniaturization of packages, flip chip mounting has been increasingly adopted. In the conventional flip-chip structure semiconductor integrated circuit,
A device is formed on the surface of the silicon chip, electrode pads are arranged around the surface of the silicon chip, the device is sealed with resin, and solder balls are arranged on each electrode pad. There is. In this flip chip, so-called face-down mounting is performed in which the elements are directed downward and the solder balls are connected to the mounting substrate. On the other hand, in order to realize a so-called face-up mounting chip in which the element is mounted upward, an LSI having a structure in which the element chip is mounted on a substrate having electrode pads or solder balls formed on the back surface has been proposed. .

[0003]

In such a conventional semiconductor integrated circuit, the following problems occur when the flip chip structure is adopted. That is, in the case of a flip chip, since the electrode pads are placed on the entire circuit surface of the chip, when observing the internal waveform of the chip with an EB tester or the like, wiring correction by FIB (focused ion beam) is required. There were the following problems when doing it. The first problem is that it is difficult for the flip chip to supply the power and signals necessary for observing the internal waveform of the chip. The reason is that in order to observe the internal waveform, it is necessary to supply power with the chip face-up. Therefore, wire bonding is the most effective connection method for supplying power, but flip-chip supports multiple pins, so
Because the electrode pads are placed on the entire surface of the chip, it may be necessary to connect with wires longer than usual.

The second problem is that it is difficult to observe the internal waveform due to the wires and electrode pads. The reason is that in order to accurately observe the waveform, it is necessary to remove the passivation film on the wiring to be observed by FIB or the like, but if there is a wiring under the wire, the wiring below it cannot be processed. Also, if the electrode pad is a pin that is indispensable for measurement, such as a clock signal terminal, it is impossible to observe the wiring under the pad. A third problem is that when the FIB wiring is corrected, the wiring under the signal pad cannot be used for the correction. The fourth problem is that the FIB wiring correction needs to be performed in a quantity larger than that actually required, but in the case of a flip chip, it is difficult to read how much is processed. The reason is F
Although it is necessary to correct the IB wiring before assembling the LSI package, in the case of a flip chip, it takes time to complete the assembly inspection after the correction of the FIB wiring, and the assembly yield is sometimes bad. Is difficult to see.

Further, in a semiconductor integrated circuit in which an element is mounted on a substrate on which electrode pads are formed and is modularized, it can be configured as a chip in which the electrode pads are arranged on the back surface of the substrate, so that the element is mounted face up. Although it is possible to improve the above-mentioned problems in the flip chip, it is necessary to provide wiring for electrically connecting the substrate and the element, and assembling man-hours increase as compared with the monolithic structure. There is a problem that reliability tends to occur, and it is difficult to realize a thin and small LSI.

It is an object of the present invention to solve the above-mentioned problems in the conventional flip chip, particularly the problem that it is difficult to evaluate the characteristics of the chip, analyze the failure, and correct the wiring by FIB and the like, while making the thin and small monolithic structure there is provided a method for manufacturing a semiconductor integrated circuit.

[0007]

[0008]

A method of manufacturing a semiconductor integrated circuit according to the present invention comprises a step of oxidizing a surface of a first semiconductor substrate to form a base insulating film, and a step of forming the base insulating film on the base insulating film. A step of forming a through hole for external connection penetrating in the thickness direction, a second semiconductor substrate is integrally bonded on the surface of the base insulating film, and the surface of the second semiconductor substrate is polished. Forming a semiconductor layer having a required thickness, forming an element such as a transistor in the semiconductor layer, and forming an embedded through hole connected to the external connection through hole in the thickness direction of the semiconductor layer And a step of forming at least one interlayer insulating film and a wiring layer on the surface of the semiconductor layer to electrically connect the element and the buried through hole, and polishing and removing the first semiconductor substrate. Characterized in that it comprises a step, the exposed step of forming an electrode pad connected to the through hole for external connection on the back surface of the base insulating film.

Further, another manufacturing method of the present invention comprises a step of oxidizing the surface of the first semiconductor substrate to form a base insulating film, and one or more power supply wirings and a lower layer on the surface of the base insulating film. A step of forming a side insulating film, a step of forming a through hole for external connection penetrating the base insulating film and the lower insulating film in the thickness direction, and a second step on the surface of the uppermost lower insulating film. Bonding the semiconductor substrates together and polishing the surface of the second semiconductor substrate to form a semiconductor layer having a required thickness; and forming an element such as a transistor on the semiconductor layer, and Forming a buried through hole connected to an external connection through hole in the thickness direction of the semiconductor layer, and 1 on the surface of the semiconductor layer.
A step of forming the above-mentioned interlayer insulating film and a wiring layer to electrically connect the element and the embedded through hole; a step of polishing and removing the first semiconductor substrate; and a step of removing the back surface of the base insulating film. The method may further include forming an electrode pad connected to the external connection through hole.

According to the semiconductor integrated circuit manufactured by the present invention, the electrode pads for inputting / outputting the power source and the signal are provided on the back surface of the chip, so that the front surface side of the chip can be electrically connected to the wiring layer or the element. Thus, it becomes possible to realize the characteristic evaluation and the failure analysis of the semiconductor integrated circuit, and it becomes possible to facilitate the wiring correction by the FIB on the chip surface side. Further, since elements such as transistors are formed in the silicon layer on the insulating film, parasitic capacitance can be reduced, and an integrated circuit with high speed operation and low power consumption can be expected. Furthermore, because the element is formed monolithically,
The chip can be made thinner and smaller.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of a semiconductor integrated circuit according to an embodiment of the present invention. A silicon layer 12 having a small thickness is provided on a base insulating film 11 made of a silicon oxide film. An oxide film 13 is formed, and an element formation region and a wiring region are defined by the element isolation oxide film 13. The element formation region is
P well 14 and N well 15 are formed, and P well 14
An N-type MOS transistor 16 is formed in the N well 15, and a P-type MOS transistor 17 is formed in the N well 15. In addition, a buried through hole 18 is formed in the wiring region so as to penetrate the silicon layer 12 in the thickness direction. An external connection through hole 19 penetrating in the thickness direction is formed in the base insulating film 11 at a position corresponding to the embedded through hole 18, and is electrically connected to one end of the embedded through hole 18. The other end of the external connection through hole 19 is electrically connected to the electrode pad 20 and the solder ball 21 provided on the back surface of the base insulating film 11. It should be noted that the wiring region of the silicon layer 12 in which the buried through holes 18 are formed is in a high resistance state because impurities are not introduced,
Therefore, the buried through holes 18 are electrically separated from each other by the high resistance of the silicon.

On the other hand, a first layer is formed on the upper side of the silicon layer 12.
Interlayer insulating film 22, first wiring layer 23, second interlayer insulating film 2
4, the second wiring layer 25, the third interlayer insulating film 26, the third wiring layer 27, and the protective insulating film 28 are sequentially formed in a stacked state,
A mold resin film 29 is formed on the protective insulating film 28. The first to third interlayer insulating films 22, 24, 2
6, and the protective insulating film 28 is formed of a silicon oxide film,
The first to third wiring layers 23, 25 and 27 are formed by forming a metal thin film of copper, aluminum or the like in a desired pattern. Further, each of the first to third interlayer insulating films 2
2, 24 and 26 have contact holes and through holes 3
0, 31, 32 are provided, and the first to third wiring layers 23, 25, 27, the N-type MOS transistor 16 and the P-type MOS transistor 17, and the buried through hole 18 are electrically connected to each other. The required circuit is constructed.

Next, a method of manufacturing the semiconductor integrated circuit shown in FIG. 1 will be described with reference to process sectional views of FIG. First, as shown in FIG. 2A, a wafer-shaped silicon substrate 41 having a thickness of about 400 to 500 μm is prepared, and the surface of the silicon substrate 41 is oxidized to obtain mechanically sufficient strength. A thick silicon oxide film 11 is formed. The silicon oxide film 11 becomes the base insulating film 11. Next, as shown in FIG. 2B, a photoresist (not shown) is selectively formed on the surface of the base insulating film 11, and the base insulating film 11 is etched using this photoresist to form a through hole. Opening is performed and a metal such as tungsten is embedded in the through hole to form the external connecting through hole 19.

Then, as shown in FIG. 2 (c), another wafer-shaped silicon substrate (shown by a chain line in the figure) 12 'is adhered onto the surface of the base insulating film 11 and heat-treated at 800 ° C. or higher. Laminate by doing. Then, the bonded wafer is subjected to a chemical mechanical polishing method (CMP method), and the surface of the silicon substrate 12 'is mirror-polished to form a silicon layer 12 having a thickness of about 1 μm. Then, as shown in FIG. 2D, P-type impurities and N-type impurities are selectively introduced into the silicon layer 12 by a well-known impurity diffusion technique to form P-wells 14 and N-wells 15, and The surface of the boundary region is selectively oxidized to form the element isolation oxide film 13, and the element formation region and the wiring region are divided. Furthermore, in the element formation region, by a well-known method,
The P well 14 has a gate insulating film 16a and a gate electrode 1
6b and N-type source / drain regions 16c are formed to form N
The type MOS transistor 16 is formed. Similarly, the N
A gate insulating film 17a, a gate electrode 17b and a P-type source / drain region 17c are formed in the well 15 to form an N-type MO.
The S transistor 17 is formed. Further, a through hole is opened in the wiring region, and tungsten or the like is embedded in the through hole to form a buried through hole 18. At this time, by forming the embedded through hole 18 at the same position as the external connection through hole 19, both through holes can be electrically connected to each other.

Then, as shown in FIG. 2E, a silicon oxide film is deposited on the silicon layer 12 by a CVD method or the like to form a first interlayer insulating film 22, and the first interlayer insulating film 22 is formed. Of the MOS transistor by forming a contact hole 30 by forming a metal film of tungsten, copper, aluminum or the like after forming a hole at a required position of the MOS transistor. Forming the first wiring layer 23 electrically connected to the drain regions 16c and 17c and the buried through hole 18. Similarly, a second interlayer insulating film 24 is formed on the first wiring layer 23, and then a through hole 31 and a second wiring layer 25 are formed. Further, the third interlayer insulating film 26, the through hole 32, and the third wiring layer 27 are formed. Then, a protective insulating film 28 is formed, and a mold resin film 29 is formed by coating the entire surface with a mold resin so as to cover the surface thereof.

Thereafter, the silicon substrate 41 exposed on the back surface of the wafer is ground and polished to expose the back surface of the base insulating film 11. As a result, the other end of the external connection through hole 19 formed in the base insulating film 11 is exposed. Then, a copper film is formed on the back surface of the base insulating film 11, and the copper film is patterned to form the electrode pad 20 integrated with the through hole 19 for external connection. Finally, the wafer is cut into individual chips by dicing, and then the electrode pads 20 of each chip are cut.
Solder balls 21 are mounted on the top of the semiconductor integrated circuit shown in FIG.

As described above, in the first embodiment, the semiconductor integrated circuit in which the electrode pad 20 is arranged on the back surface of the chip is formed as a monolithic structure. Therefore, the signal input / output electrode pad can be installed on the back surface of the chip, and even when the electrode pad is provided over almost the entire back surface of the chip, the electrical connection to the wiring on the front surface side of the chip is required. The electrode pad does not get in the way. Therefore, it is possible to evaluate the semiconductor integrated circuit and analyze the failure. Further, since there is no electrode pad on the front surface side of the chip, it becomes possible to facilitate the wiring correction by the FIB for the wiring layer on the front surface side of the chip. In addition, since elements such as MOS transistors are formed in a thin silicon layer on the insulating film, the capacitance can be reduced and high speed operation,
An integrated circuit with low power consumption can be expected. Furthermore, since the element is monolithically formed on the silicon layer, the chip can be made thinner and smaller.

In the manufacturing process, a thin silicon substrate 41 is used as a base material, a thin film silicon layer 12 is formed on the base material, elements are formed on the silicon layer 12, and a multilayer wiring structure is formed thereon. Since the thick silicon substrate 41 is manufactured and finally removed by polishing, the mechanical strength in the manufacturing process can be secured and the cracking of the wafer can be prevented. The silicon oxide film and the silicon layer can be thinly formed, and thin chips can be manufactured.

FIG. 3 is a cross-sectional view of the second embodiment of the present invention, in which parts equivalent to those in the first embodiment are designated by the same reference numerals. In this second embodiment, the silicon layer 12
On the back surface side of the first lower insulating film 33 and the second lower insulating film 34.
Are laminated, and the base insulating film 11 is formed on the back surface side. The ground layer 35 formed of a metal thin film between the first lower insulating film 33 and the second lower insulating film 34 is a metal thin film between the second lower insulating film 34 and the base insulating film 11. The formed power supply layers 36 are formed respectively. Here, the ground layer 35 and the power supply layer 36 are formed in a mesh shape so as to spread over the entire surface of the chip. Also,
The through hole 19 for external connection is formed in the first lower insulating film 3
3, the second lower insulating film 34 and the underlying insulating film 11 are formed so as to penetrate therethrough, and are electrically connected to the electrode pads 20 and the solder balls 21 on the back surface of the underlying insulating film 11. The structure of the buried through hole 18 and the MOS transistors 16 and 17 formed in the silicon layer 12, and the first to third interlayer insulating films 22, 24 and 26 and protection formed on the silicon layer 12. The configurations of the insulating film 28 and the first to third wiring layers 23, 25, 27, and the configuration of the mold resin film 29 are the same as those in the first embodiment.

FIG. 4 is a sectional view of steps of the manufacturing method according to the second embodiment. First, as shown in FIG. 4A, the point that the surface of the silicon substrate 41 is oxidized to form the base insulating film 11 is the same as in the first embodiment. In making the decision,
As shown in (b), a metal film such as aluminum is formed on the surface of the base insulating film 11 and formed into a desired pattern to form the power supply layer 36. Then, a silicon oxide film is grown thereon by a CVD method to form a second lower insulating film 34, a metal film such as aluminum is similarly formed on the surface of the second lower insulating film 34, and a desired pattern is formed to form a ground layer. 35 is formed. Further, a silicon oxide film is similarly grown thereon by the CVD method to form a first lower insulating film 33. Then, as shown in FIG. 4C, another wafer-shaped silicon substrate is brought into close contact with the surface of the first lower insulating film 33,
Bonding is performed by heat treatment at 0 ° C. or higher. Then, the bonded wafer is subjected to a CMP method, and the surface of the silicon substrate is mirror-polished to form a silicon layer 12 having a thickness of about 1 μm.

Thereafter, similar to the first embodiment shown in FIG. 2, MOS transistors 16 and 1 are formed on the silicon layer 12.
7 is formed, and the interlayer insulating films 22, 24, 2 are formed thereon.
6, the wiring layers 23, 25, 27, the contact holes 30, 31, 32 are formed, and the protective insulating film 28 and the mold resin film 29 are further formed. Further, after the silicon substrate 41 on the back surface side of the base insulating film 11 is removed by polishing, the exposed back surface is electrically connected to the external connection through hole 19 as in the first embodiment.
Form 0. Then, the wafer is diced into individual chips, and the solder balls 21 are connected to the electrode pads to manufacture the semiconductor integrated circuit of FIG.

Also in the semiconductor integrated circuit of the second embodiment, as in the first embodiment, the semiconductor integrated circuit in which the electrode pads are arranged on the back surface of the chip can be formed as a monolithic structure. Even when the semiconductor chip is arranged almost all over the back surface of the chip, the electrode pad does not interfere with the electrical connection to the wiring on the front surface side of the chip, and the semiconductor integrated circuit can be evaluated and the failure can be analyzed. Further, since there is no electrode pad on the front surface side of the chip, the FIB for the wiring layer on the front surface side of the chip is
It is possible to easily modify the wiring by. Also,
Since elements such as MOS transistors are formed in a thin silicon layer on the insulating film, the capacitance can be reduced,
High-speed operation and low power consumption integrated circuits can be expected. In particular,
In the second embodiment, the ground layer 35 and the power supply layer 36 are arranged on the back surface side of the chip, and these are formed in a mesh shape, so that the inductance and resistance of the power supply wiring of the chip should be reduced. Will also be possible. further,
Since the element is monolithically formed on the silicon layer, the chip can be made thinner and smaller.

Also in the manufacturing process, as in the first embodiment, the element and the laminated wiring structure are manufactured with the thick silicon substrate as the base material, and the thick silicon substrate is finally removed by polishing. The mechanical strength in the manufacturing process can be secured, the cracking of the wafer can be prevented, and the silicon oxide film and the silicon layer of the finally formed semiconductor integrated circuit can be thinly formed correspondingly, which enables the manufacture of thin chips. .

The present invention is not limited to the above embodiment, and the multilayer wiring structure formed on the front surface side of the chip and the ground layer and the power supply layer formed on the rear surface side can be formed in any structure. . Needless to say, the electrode pads on the back surface of the chip may be directly mounted on the mounting substrate without providing solder balls.

[0025]

As described above, according to the manufacturing method of the present invention.
Since the semiconductor integrated circuit manufactured by the above is configured as a semiconductor integrated circuit having a monolithic structure in which electrode pads are arranged on the back surface side of the chip, the following effects can be obtained.
That is, since there is no electrode pad on the front surface side of the chip, there is no wire for connecting to the electrode pad, power supply to the wiring or elements existing on the front surface side of the chip, signal supply, or internal wiring of the chip. It becomes easy to observe the signal waveform with an EB tester or the like, and it becomes possible to realize characteristic evaluation and failure analysis of the semiconductor integrated circuit. Further, the wiring can be easily corrected by FIB for the wiring layer on the surface. further,
Since elements such as transistors are formed in the silicon layer on the insulating film, parasitic capacitance can be reduced, and an integrated circuit with high speed operation and low power consumption can be expected. In particular, since the element is formed monolithically, the chip can be made thinner and smaller. Further, according to the manufacturing method of the present invention
If a thick semiconductor substrate is used as a base material,
Manufacture laminated wiring structure and finally polish the semiconductor substrate
Mechanical strength in the manufacturing process
It secures and prevents the cracking of the wafer, and the final shape
Silicon oxide film or silicon layer of the semiconductor integrated circuit to be formed
Can be formed thin, and thin chips can be manufactured.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the method of manufacturing the semiconductor integrated circuit according to the first embodiment of the present invention in the order of steps.

FIG. 3 is a sectional view of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a method of manufacturing a semiconductor integrated circuit according to a second embodiment of the present invention in the order of steps.

[Explanation of symbols]

11 Base insulating film 12 Silicon layer (second silicon substrate) 13 Element isolation oxide film 16 N-type MOS transistor 17 P-type MOS transistor 18 Embedded through holes 19 Through hole for external connection 20 electrode pads 21 solder balls 22, 24, 26 Interlayer insulation film 23, 25, 27 wiring layers 28 Protective insulation film 29 Mold resin film 30, 31, 32 Contact hole (through hole) 33,34 Lower insulating film 35 Ground layer 36 power layers 41 Silicon substrate (first silicon substrate)

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H01L 27/12 H01L 21/90 C 23/12 L (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21 / 3205 H01L 21/66 H01L 21/768 H01L 27/12

Claims (2)

(57) [Claims] 1. A step of oxidizing a surface of a first semiconductor substrate to form a base insulating film, and a step of forming an external connection through hole penetrating the base insulating film in the thickness direction. A step of integrally bonding a second semiconductor substrate on the surface of the base insulating film, and polishing the surface of the second semiconductor substrate to form a semiconductor layer having a required thickness; Forming an element such as a transistor in the layer and forming an embedded through hole connected to the through hole for external connection in the thickness direction of the semiconductor layer; and one or more interlayer insulating films on the surface of the semiconductor layer. And a step of forming a wiring layer to electrically connect the element and the embedded through hole, a step of removing the first semiconductor substrate by polishing, and a step of polishing the external surface on the exposed back surface of the base insulating film. Contact A method of manufacturing a semiconductor integrated circuit, comprising a step of forming an electrode pad connected to a continuous through hole. 2. A step of oxidizing a surface of a first semiconductor substrate to form a base insulating film, and 1 on the surface of the base insulating film.
The step of forming the power supply wiring and the lower insulating film described above, the step of forming a through hole for external connection penetrating the base insulating film and the lower insulating film in the thickness direction, and the lower insulating film of the uppermost layer. A step of integrally bonding a second semiconductor substrate on the surface of the film and polishing the surface of the second semiconductor substrate to form a semiconductor layer having a required thickness; Forming an element and forming a buried through hole connected to the external connecting through hole in the thickness direction of the semiconductor layer; and forming one or more interlayer insulating films and wiring layers on the surface of the semiconductor layer. And electrically connecting the element to the embedded through hole, polishing and removing the first semiconductor substrate, and connecting the external connection through hole to the back surface of the base insulating film. The method of manufacturing a semiconductor integrated circuit which comprises a step of forming an electrode pad.