JP2001196374A - Semiconductor integrated circuit and producing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate a wiring correction based on the characteristic evaluation of a chip, fault analysis and FIB or the like and to provide a thin and miniaturized semiconductor integrated circuit in a monolithic structure and a producing method therefor on the other hand. SOLUTION: Elements 16 and 17 such as transistors and an embedded through hole 18 are formed on a semiconductor layer 12 integrally formed on the front surface of a base insulating film 11 and a through hole 19 for external connection through in the direction of the thickness is formed on the base insulating film 11. An electrode pad electrically connected to the through hole 19 for external connection is provided on the back surface of the base insulating film 19, and wiring structures 22-28 for at least one layer for electrically connecting the elements and the embedded through hole are provided on the front surface of the semiconductor layer 12. Since no electrode pad exists on the front side of the chip, power supply to wiring or elements existent on the front side of the chip, signal supply or waveform of a signal inside the chip can be easily observed by an EB tester or the like and the characteristic evaluation or fault analysis of the semiconductor integrated circuit is enabled. Besides, the wiring correction based on FIB to the wiring layer on the front surface is facilitated. Further, thinning and miniaturizing can be provided because of the monolithic structure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a thin and small flip-chip structured semiconductor integrated circuit and a method of manufacturing the same.

[0002]

2. Description of the Related Art In order to cope with recent increase in the number of pins of a semiconductor integrated circuit (LSI) and downsizing of a package, flip-chip mounting has been increasingly adopted. In a conventional flip-chip structure semiconductor integrated circuit,
Elements are formed on the surface of the silicon chip, electrode pads are arranged around the surface of the silicon chip, the elements are sealed with resin or the like, and solder balls or the like are arranged on each electrode pad. I have. In this flip chip, a so-called face-down mounting is performed in which a solder ball is connected to a mounting substrate with the element facing downward. On the other hand, in order to realize a so-called face-up mounting chip in which elements are mounted upward, an LSI having a structure in which element chips are mounted on a substrate having electrode pads or solder balls formed on the back surface has been proposed. .

[0003]

In such a conventional semiconductor integrated circuit, the following problems occur when the flip-chip structure is used. That is, in the case of the flip chip, since the electrode pads are placed on the entire circuit surface of the chip, when observing the internal waveform of the chip with an EB tester or the like, or when correcting the wiring with a FIB (focused ion beam). There were the following problems when performing it. The first problem is that it is difficult for the flip chip to supply power and signals necessary for observing the internal waveform of the chip. The reason is that in order to observe the internal waveform, it is necessary to supply power while the chip is face-up. For this reason, wire bonding is the most effective connection method for supplying power, but since flip chips are compatible with multi-pin connections,
This is because the electrode pads are placed on the entire surface of the chip, so that connection may need to be made with a longer wire than usual.

[0004] The second problem is that it is difficult to observe the internal waveform due to wires and electrode pads. The reason for this is that in order to accurately observe the waveform, it is necessary to remove the passivation film on the wiring to be observed by FIB or the like. However, if there is a wiring under the wire, the wiring under the wire cannot be processed. Further, when the electrode pad is a pin which is indispensable for measurement like a clock signal terminal, it is impossible to observe the wiring under the pad. A third problem is that when the FIB wiring is corrected, the wiring under the signal pad cannot be used for the correction. The fourth problem is that it is necessary to perform the FIB wiring correction more than the actually required quantity, but in the case of flip chips, it is difficult to read how much quantity to process. The reason is F
IB wiring correction must be performed before assembling the LSI package. However, in the case of a flip chip, it takes time until the completion of the assembly inspection after the FIB wiring correction, and sometimes the yield of assembly is poor. Is difficult to see.

Further, in a semiconductor integrated circuit in which elements are mounted on a substrate on which electrode pads are formed to form a module in which electrode pads are provided on the back surface of the substrate, the elements are mounted face up. Although it is possible to improve the above-described problem in the flip chip, wiring for electrically connecting the substrate and the element is required, and the number of assembling steps is increased and compared with the monolithic structure. There is a problem that reliability is apt to occur and it is difficult to realize a thin and small LSI.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems in the conventional flip chip, in particular, problems in which it is difficult to evaluate the characteristics of the chip, to analyze the failure, and to correct the wiring by FIB, etc., and to realize a thin and small monolithic structure. A semiconductor integrated circuit and a method for manufacturing the same are provided.

[0007]

A semiconductor integrated circuit according to the present invention comprises a base insulating film, a semiconductor layer integrally formed on the surface of the base insulating film, and an element such as a transistor formed on the semiconductor layer. A buried through-hole formed through the semiconductor layer in the thickness direction; and an external connection through-hole formed through the base insulating film in the thickness direction and electrically connected to the buried through-hole. An electrode pad provided on the back surface of the base insulating film and electrically connected to the through hole for external connection; and formed on the surface of the semiconductor layer and electrically connecting at least the element and the buried through hole. And a wiring structure of one or more layers. Here, it is preferable that the wiring structure on the surface of the semiconductor layer is a multilayer wiring structure in which a plurality of wiring layers are respectively insulated by an interlayer insulating film. Also,
One or more lower insulating films are formed between the surface of the base insulating film and the semiconductor layer, and the external connection through holes are formed in a state penetrating the base insulating film and the lower insulating film, It is preferable that a ground layer and a power supply layer are formed between the lower insulating films or between the lower insulating film and the base insulating film. Further, a solder ball may be connected to the electrode pad.

According to a method of manufacturing a semiconductor integrated circuit of the present invention, a step of oxidizing a surface of a first semiconductor substrate to form a base insulating film, and penetrating the base insulating film through the base insulating film in a thickness direction. A step of forming a through hole for external connection, a step of integrally bonding a second semiconductor substrate on the surface of the base insulating film, and polishing the surface of the second semiconductor substrate to form a semiconductor of a required thickness. Forming a device such as a transistor in the semiconductor layer, and forming a buried through hole connected to the external connection through hole in a thickness direction of the semiconductor layer; Forming one or more interlayer insulating films and wiring layers on the surface to make an electrical connection between the device and the buried through hole; polishing and removing the first semiconductor substrate; And characterized in that it comprises a step of forming an electrode pad connected to the through hole for external connection on the back surface of the base insulating film.

In another manufacturing method of the present invention, a step of oxidizing a surface of a first semiconductor substrate to form a base insulating film, and forming one or more power supply wirings on the surface of the base insulating film. Forming a side insulating film; forming an external connection through-hole penetrating the base insulating film and the lower insulating film in the thickness direction; and forming a second through-hole on the surface of the lowermost insulating film in the uppermost layer. Bonding the semiconductor substrate integrally, and polishing the surface of the second semiconductor substrate to form a semiconductor layer of a required thickness; and forming an element such as a transistor on the semiconductor layer, Forming a buried through hole connected to an external connection through hole in a thickness direction of the semiconductor layer;
Forming the above-described interlayer insulating film and wiring layer to electrically connect the element and the buried through hole; polishing and removing the first semiconductor substrate; Forming an electrode pad connected to the external connection through-hole.

According to the semiconductor integrated circuit of the present invention, a power supply,
By installing signal input / output electrode pads on the back surface of the chip, electrical connection to the wiring layers or elements can be made from the front surface side of the chip, and the characteristics evaluation and failure analysis of the semiconductor integrated circuit can be realized. It is possible to facilitate wiring correction by FIB on the side. Since elements such as transistors are formed in the silicon layer over the insulating film, parasitic capacitance can be reduced, and an integrated circuit with high speed operation and low power consumption can be expected. Furthermore, since the elements are formed monolithically, the chip can be made thinner,
Miniaturization can be realized.

[0011]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of a semiconductor integrated circuit according to one embodiment of the present invention. A thin silicon layer 12 is provided on a base insulating film 11 made of a silicon oxide film. An oxide film 13 is formed, and an element formation region and a wiring region are defined by the element isolation oxide film 13. The element formation region,
A P well 14 and an N well 15 are formed.
, An N-type MOS transistor 16 is formed in the N-well 15, and a P-type MOS transistor 17 is formed in the N-well 15. Further, a buried through hole 18 penetrating the silicon layer 12 in the thickness direction is formed in the wiring region. The base insulating film 11 has a through hole 19 for external connection penetrating in a thickness direction at a location corresponding to the buried through hole 18, and is electrically connected to one end of the buried through hole 18. The other end of the external connection through hole 19 is electrically connected to an electrode pad 20 and a solder ball 21 provided on the back surface of the base insulating film 11. Note that the wiring region of the silicon layer 12 where each of the buried through holes 18 is formed has a high resistance state since no impurity is introduced thereinto.
Therefore, the buried through holes 18 are electrically separated from each other by the high resistance of the silicon.

On the other hand, the first layer
Interlayer insulating film 22, first wiring layer 23, second interlayer insulating film 2
4, a second wiring layer 25, a third interlayer insulating film 26, a third wiring layer 27, and a protective insulating film 28 are sequentially formed in a laminated state,
A mold resin film 29 is formed on the protective insulating film 28. The first to third interlayer insulating films 22, 24, 2
6, and the protective insulating film 28 is formed of a silicon oxide film;
The first to third wiring layers 23, 25, 27 are formed by forming a metal thin film of copper, aluminum, or the like into a required pattern. Further, each of the first to third interlayer insulating films 2
2, 24 and 26 have contact holes and through holes 3
0, 31, and 32, the first to third wiring layers 23, 25, and 27, the N-type MOS transistor 16 and the P-type MOS transistor 17, and the buried through hole 18 are electrically connected to each other. Thus, a required circuit is configured.

Next, a method of manufacturing the semiconductor integrated circuit shown in FIG. 1 will be described with reference to the process sectional views of FIG. First, as shown in FIG. 2A, a wafer-shaped silicon substrate 41 having a thickness of about 400 to 500 μm is prepared, and the surface of the silicon substrate 41 is oxidized to obtain mechanically sufficient strength. A thick silicon oxide film 11 is formed. This silicon oxide film 11 becomes the base insulating film 11. Next, as shown in FIG. 2B, a photoresist (not shown) is selectively formed on the surface of the base insulating film 11, and the base insulating film 11 is etched using the photoresist to form through holes. An opening is formed and a metal such as tungsten is buried in the through hole to form the through hole 19 for external connection.

Next, as shown in FIG. 2C, another wafer-shaped silicon substrate (indicated by a chain line) 12 'is adhered to the surface of the base insulating film 11 and heat-treated at 800 ° C. or more. And stick them together. Then, the bonded wafer is subjected to a chemical mechanical polishing method (CMP method), and the surface of the silicon substrate 12 ′ is mirror-polished to form a silicon layer 12 having a thickness of about 1 μm. Then, as shown in FIG. 2D, a P-type impurity and an N-type impurity are selectively introduced into the silicon layer 12 by a well-known impurity diffusion technique to form a P-well 14 and an N-well 15, and The surface of the boundary region is selectively oxidized to form an element isolation oxide film 13 and separate an element formation region and a wiring region. Furthermore, in the element formation region, a well-known method is used.
The gate insulating film 16a and the gate electrode 1
6b and N-type source / drain regions 16c
A type MOS transistor 16 is formed. Similarly, the N
A gate insulating film 17a, a gate electrode 17b and a P-type source / drain region 17c are formed in the well 15 to form an N-type MO.
An S transistor 17 is formed. Further, a through hole is opened in the wiring region, and a buried through hole 18 is formed by burying tungsten or the like in the through hole. At this time, by forming the buried through hole 18 at the same position as the external connection through hole 19, it is possible to electrically connect both through holes to each other.

Next, as shown in FIG. 2E, a silicon oxide film is deposited on the silicon layer 12 by a CVD method or the like to form a first interlayer insulating film 22, and the first interlayer insulating film 22 is formed. After a hole is opened at a required location, a metal film of tungsten, copper, aluminum or the like is formed to form a contact hole 30, and the metal film is formed in a required pattern to thereby reduce the source of each MOS transistor. Forming a first wiring layer 23 electrically connected to the drain regions 16c and 17c and the buried through hole 18; Similarly, a second interlayer insulating film 24 is formed on the first wiring layer 23, and then a through hole 31 and a second wiring layer 25 are formed. Further, a third interlayer insulating film 26, a through hole 32, and a third wiring layer 27 are formed. Thereafter, a protective resin film 28 is formed, and a molding resin is coated on the entire surface so as to cover the surface thereof, thereby forming a molding resin film 29.

Thereafter, the silicon substrate 41 exposed on the back surface of the wafer is ground and polished to expose the back surface of the base insulating film 11. Thereby, the other end of the external connection through hole 19 formed in the base insulating film 11 is exposed. Then, a copper film is formed on the back surface of the base insulating film 11, and the copper film is patterned to form an electrode pad 20 integrated with the through hole 19 for external connection. Finally, the wafer is cut into individual chips by dicing, and the electrode pads 20 of each chip are placed thereon.
The solder ball 21 is mounted thereon, and the semiconductor integrated circuit of FIG. 1 is completed.

As described above, in the first embodiment, the semiconductor integrated circuit in which the electrode pads 20 are arranged on the back surface of the chip is formed as a monolithic structure. Therefore, the electrode pads for input / output of signals can be provided on the back surface of the chip, and even when the electrode pads are provided over almost the entire back surface of the chip, when the electrode pads are electrically connected to the wiring on the front surface side of the chip. The electrode pads do not interfere. Therefore, evaluation and failure analysis of the semiconductor integrated circuit can be performed. Further, since there is no electrode pad on the front surface side of the chip, it is possible to easily correct the wiring of the wiring layer on the front surface side of the chip by FIB. Further, since elements such as MOS transistors are formed in a thin silicon layer on the insulating film, the capacity can be reduced, and high-speed operation and
An integrated circuit with low power consumption can be expected. Furthermore, since the element is formed monolithically on the silicon layer, the chip can be made thinner and smaller.

In the manufacturing process, a thin silicon layer 12 is formed on a thick silicon substrate 41 as a base material, elements are formed thereon, and a multilayer wiring structure is formed thereon. Since the manufactured silicon substrate 41 is finally removed by polishing, the mechanical strength in the manufacturing process can be ensured, and the wafer can be prevented from cracking. A silicon oxide film or a silicon layer can be formed thin, and a thin chip can be manufactured.

FIG. 3 is a sectional view of a second embodiment of the present invention, in which parts equivalent to those of the first embodiment are denoted by the same reference numerals. In the second embodiment, the silicon layer 12
A first lower insulating film 33 and a second lower insulating film 34
Are laminated, and a base insulating film 11 is formed on the back surface side. A ground layer 35 formed of a metal thin film between the first lower insulating film 33 and the second lower insulating film 34 is formed between the second lower insulating film 34 and the base insulating film 11 by a metal thin film. The formed power supply layers 36 are respectively formed. Here, the ground layer 35 and the power supply layer 36 are formed in a mesh shape so as to spread over the entire surface of the chip. Also,
The through hole 19 for external connection is formed in the first lower insulating film 3.
3, the second lower insulating film 34 and the underlying insulating film 11 are formed so as to penetrate therethrough, and are electrically connected to the electrode pads 20 and the solder balls 21 on the back surface of the underlying insulating film 11. The structure of the buried through hole 18 and the MOS transistors 16 and 17 formed in the silicon layer 12, and the first to third interlayer insulating films 22, 24 and 26 formed on the silicon layer 12 and protection. The configuration of the insulating film 28 and the first to third wiring layers 23, 25, 27, and the configuration of the mold resin film 29 are the same as those in the first embodiment.

FIG. 4 is a process sectional view of the manufacturing method according to the second embodiment. First, as shown in FIG. 4A, the surface of a silicon substrate 41 is oxidized to form a base insulating film 11, which is the same as in the first embodiment. Figure 4
As shown in (b), a power source layer 36 is formed by forming a metal film such as aluminum on the surface of the base insulating film 11 and forming it into a required pattern. Then, a silicon oxide film is grown thereon by a CVD method to form a second lower insulating film 34, a metal film such as aluminum is formed on the surface of the second lower insulating film 34, and a ground pattern is formed by forming a required pattern. 35 is formed. Further, a first lower insulating film 33 is formed thereon by similarly growing a silicon oxide film by the CVD method. Then, as shown in FIG. 4C, another wafer-shaped silicon substrate is brought into close contact with the surface of the first lower insulating film 33,
It is bonded by heat treatment at 0 ° C. or more. Then, the bonded wafer is subjected to a CMP method, and the surface of the silicon substrate is mirror-polished to form a silicon layer 12 having a thickness of about 1 μm.

Thereafter, as in the first embodiment shown in FIG.
7 and an interlayer insulating film 22, 24, 2
6, the wiring layers 23, 25, 27, the contact holes 30, 31, 32, etc. are formed, and further the protective insulating film 28 and the mold resin film 29 are formed. After removing the silicon substrate 41 on the back surface side of the base insulating film 11 by polishing, the exposed back surface is provided with an electrode pad 2 electrically connected to the through hole 19 for external connection as in the first embodiment.
0 is formed. Then, the semiconductor integrated circuit of FIG. 3 is manufactured by dicing the wafer into individual chips and connecting the solder balls 21 to the electrode pads.

In the semiconductor integrated circuit according to the second embodiment, as in the first embodiment, the semiconductor integrated circuit in which the electrode pads are arranged on the back surface of the chip can be formed as a monolithic structure. Even when the chip is disposed over substantially the entire back surface of the chip, the electrode pads do not hinder the electrical connection to the wiring on the front surface side of the chip, and the evaluation and failure analysis of the semiconductor integrated circuit can be performed. Further, since there is no electrode pad on the front surface side of the chip, the FIB
Wiring can be easily corrected. Also,
Since elements such as MOS transistors are formed in a thin silicon layer on the insulating film, the capacitance can be reduced.
An integrated circuit with high speed operation and low power consumption can be expected. In particular,
In the second embodiment, the ground layer 35 and the power supply layer 36 are disposed on the back side of the chip, and particularly, these are formed in a mesh shape, so that the inductance and resistance of the power supply wiring of the chip can be reduced. Also becomes possible. further,
Since the element is monolithically formed on the silicon layer, the chip can be made thinner and smaller.

In the manufacturing process, as in the first embodiment, an element and a laminated wiring structure are manufactured with a thick silicon substrate as a base material, and the thick silicon substrate is finally removed by polishing. The mechanical strength in the manufacturing process can be secured and the wafer can be prevented from cracking, and the silicon oxide film and silicon layer of the finally formed semiconductor integrated circuit can be formed thinner, which enables the manufacture of thin chips. .

The present invention is not limited to the above embodiment, and the multilayer wiring structure formed on the front surface side of the chip, and the ground layer and power supply layer formed on the rear surface side can be formed in any structures. . Needless to say, the electrode pads on the rear surface of the chip may be directly mounted on the mounting substrate without providing solder balls.

[0025]

As described above, the present invention is configured as a semiconductor integrated circuit having a monolithic structure in which the electrode pads are provided on the back surface of the chip, so that the following effects can be obtained. That is, since there is no electrode pad on the front surface side of the chip, there is no wire for connecting to the electrode pad, so that power and signals are supplied to wirings and elements existing on the front surface side of the chip, and signals inside the chip. It is easy to observe the signal waveform with an EB tester or the like, and it is possible to evaluate the characteristics of the semiconductor integrated circuit and analyze the failure. Further, wiring correction by the FIB on the wiring layer on the surface is facilitated. Furthermore, since elements such as transistors are formed in the silicon layer over the insulating film, parasitic capacitance can be reduced, and an integrated circuit with high speed operation and low power consumption can be expected. In particular, since the elements are formed monolithically, the chip can be made thinner and smaller.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method of manufacturing the semiconductor integrated circuit according to the first embodiment of the present invention in the order of steps.

FIG. 3 is a sectional view of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 4 is a sectional view illustrating a method of manufacturing a semiconductor integrated circuit according to a second embodiment of the present invention in the order of steps.

[Explanation of symbols]

 REFERENCE SIGNS LIST 11 base insulating film 12 silicon layer (second silicon substrate) 13 element isolation oxide film 16 n-type MOS transistor 17 p-type MOS transistor 18 buried through hole 19 external connection through hole 20 electrode pad 21 solder ball 22, 24, 26 interlayer Insulating film 23, 25, 27 Wiring layer 28 Protective insulating film 29 Mold resin film 30, 31, 32 Contact hole (through hole) 33, 34 Lower insulating film 35 Ground layer 36 Power supply layer 41 Silicon substrate (first silicon substrate)

Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat II (Reference) H01L 27/12 H01L 21/90 C 23/12 L F term (Reference) 4M106 AA01 AA04 AD01 AD10 AD24 BA02 BA03 5F033 HH08 HH11 HH19 JJ08 JJ11 JJ19 KK08 KK11 MM30 QQ00 QQ37 QQ48 QQ76 RR04 SS11 SS25 SS27 VV04 VV05 VV07 XX36 XX37

Claims (6)

[Claims] 1. A base insulating film, a semiconductor layer integrally formed on a surface of the base insulating film, an element such as a transistor formed on the semiconductor layer, and a semiconductor layer penetrating the semiconductor layer in a thickness direction. A buried through hole formed in the base insulating film, an external connection through hole formed through the base insulating film in a thickness direction and electrically connected to the buried through hole, and provided on a back surface of the base insulating film. An electrode pad electrically connected to the external connection through-hole; and one or more wiring structures formed on the surface of the semiconductor layer for electrically connecting at least the element and the buried through-hole. A semiconductor integrated circuit characterized by the above-mentioned. 2. The semiconductor integrated circuit according to claim 1, wherein the wiring structure on the surface of the semiconductor layer is a multilayer wiring structure in which a plurality of wiring layers are respectively insulated by an interlayer insulating film. 3. One or more lower insulating films are formed between the surface of the base insulating film and the semiconductor layer, and the external connection through holes penetrate the base insulating film and the lower insulating film. 2. A ground layer and a power supply layer are formed in a state, and a ground layer and a power supply layer are formed between the lower insulating films or between the lower insulating film and the base insulating film.
Or the semiconductor integrated circuit according to 2. 4. The semiconductor integrated circuit according to claim 1, wherein a solder ball is connected to said electrode pad. 5. A step of oxidizing a surface of the first semiconductor substrate to form a base insulating film, and forming an external connection through hole in the base insulating film penetrating the base insulating film in a thickness direction. A step of integrally bonding a second semiconductor substrate on the surface of the base insulating film, and polishing the surface of the second semiconductor substrate to form a semiconductor layer of a required thickness; Forming an element such as a transistor in a layer and forming a buried through hole connected to the external connection through hole in a thickness direction of the semiconductor layer; and forming one or more interlayer insulating films on the surface of the semiconductor layer. Forming a wiring layer and making an electrical connection between the element and the buried through hole; polishing and removing the first semiconductor substrate; Contact A method for manufacturing a semiconductor integrated circuit, comprising a step of forming an electrode pad connected to a connection through hole. 6. A step of oxidizing a surface of a first semiconductor substrate to form a base insulating film;
Forming the power supply wiring and the lower insulating film, forming an external connection through-hole penetrating the base insulating film and the lower insulating film in the thickness direction, and forming the lower insulating film on the uppermost layer. A step of integrally laminating a second semiconductor substrate on the surface of the film and polishing the surface of the second semiconductor substrate to form a semiconductor layer of a required thickness; Forming an element and forming a buried through hole connected to the external connection through hole in a thickness direction of the semiconductor layer; and forming one or more interlayer insulating films and wiring layers on a surface of the semiconductor layer. Making an electrical connection between the element and the buried through hole, polishing and removing the first semiconductor substrate, and connecting to the through hole for external connection on the back surface of the base insulating film. The method of manufacturing a semiconductor integrated circuit which comprises a step of forming an electrode pad.