JP2003258157A - Method for producing chip-size package - Google Patents
Method for producing chip-size packageInfo
- Publication number
- JP2003258157A JP2003258157A JP2002053621A JP2002053621A JP2003258157A JP 2003258157 A JP2003258157 A JP 2003258157A JP 2002053621 A JP2002053621 A JP 2002053621A JP 2002053621 A JP2002053621 A JP 2002053621A JP 2003258157 A JP2003258157 A JP 2003258157A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- forming
- insulating resin
- resin layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 44
- 239000010410 layer Substances 0.000 claims abstract description 197
- 239000004065 semiconductor Substances 0.000 claims abstract description 109
- 229920005989 resin Polymers 0.000 claims abstract description 95
- 239000011347 resin Substances 0.000 claims abstract description 95
- 230000001681 protective effect Effects 0.000 claims abstract description 37
- 239000011241 protective layer Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 39
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 104
- 229910000679 solder Inorganic materials 0.000 description 21
- 238000007747 plating Methods 0.000 description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 19
- 229910052802 copper Inorganic materials 0.000 description 19
- 239000010949 copper Substances 0.000 description 19
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 16
- 238000007772 electroless plating Methods 0.000 description 16
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 12
- 238000009713 electroplating Methods 0.000 description 11
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 8
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- WSFSSNUMVMOOMR-UHFFFAOYSA-N Formaldehyde Chemical compound O=C WSFSSNUMVMOOMR-UHFFFAOYSA-N 0.000 description 4
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 description 4
- 239000000654 additive Substances 0.000 description 4
- 239000001569 carbon dioxide Substances 0.000 description 4
- 229910002092 carbon dioxide Inorganic materials 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- ZNBNBTIDJSKEAM-UHFFFAOYSA-N 4-[7-hydroxy-2-[5-[5-[6-hydroxy-6-(hydroxymethyl)-3,5-dimethyloxan-2-yl]-3-methyloxolan-2-yl]-5-methyloxolan-2-yl]-2,8-dimethyl-1,10-dioxaspiro[4.5]decan-9-yl]-2-methyl-3-propanoyloxypentanoic acid Chemical compound C1C(O)C(C)C(C(C)C(OC(=O)CC)C(C)C(O)=O)OC11OC(C)(C2OC(C)(CC2)C2C(CC(O2)C2C(CC(C)C(O)(CO)O2)C)C)CC1 ZNBNBTIDJSKEAM-UHFFFAOYSA-N 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 238000007664 blowing Methods 0.000 description 2
- 239000003054 catalyst Substances 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 229910000365 copper sulfate Inorganic materials 0.000 description 2
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000007602 hot air drying Methods 0.000 description 2
- 229910000378 hydroxylammonium sulfate Inorganic materials 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000003672 processing method Methods 0.000 description 2
- 229910000029 sodium carbonate Inorganic materials 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- PYRZPBDTPRQYKG-UHFFFAOYSA-N cyclopentene-1-carboxylic acid Chemical compound OC(=O)C1=CCCC1 PYRZPBDTPRQYKG-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000006386 neutralization reaction Methods 0.000 description 1
- 150000002940 palladium Chemical class 0.000 description 1
- 239000012286 potassium permanganate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Dicing (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置を製造
するチップサイズパッケージの製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a chip size package for manufacturing a semiconductor device.
【０００２】[0002]
【従来の技術】従来の技術では、半導体装置のチップサ
イズパッケージの製造方法は、ウエハーに直接に加工処
理し、最後の工程で、個片に断裁するウエハー一括処理
が主流である。上記加工処理を説明する。まず、多数の
半導体素子を面付けして形成したウエハーを準備する。
次に、多数の半導体素子が形成するウエハーの全面に絶
縁樹脂層を形成する。次に、前記半導体素子の電極部と
導通をとるため、前記絶縁樹脂層にバイアホールを孔設
する。2. Description of the Related Art In the prior art, a method of manufacturing a chip size package of a semiconductor device is mainly a batch processing of wafers in which a wafer is directly processed and cut into individual pieces in a final step. The above processing will be described. First, a wafer formed by imposing a large number of semiconductor elements is prepared.
Next, an insulating resin layer is formed on the entire surface of the wafer on which a large number of semiconductor elements are formed. Next, a via hole is formed in the insulating resin layer to establish electrical connection with the electrode portion of the semiconductor element.
【０００３】前記絶縁樹脂層からバイアホールの内壁ま
で、めっき法を用いて、導体層を形成し、予め準備した
フォトマスクを用いて、所定の配線パターンを形成す
る。A conductor layer is formed from the insulating resin layer to the inner wall of the via hole by a plating method, and a predetermined wiring pattern is formed by using a photomask prepared in advance.
【０００４】次に、前記配線パターンを保護する保護層
を形成する。保護層の形成は、前記配線パターンの全面
にソルダーレジスト樹脂を塗布、又は積層して保護層
（ソルダーレジスト層）を形成する。前記配線パターン
の電極部と導通をとるため、の前記絶縁樹脂層に開口部
を孔設する。Next, a protective layer for protecting the wiring pattern is formed. The protective layer is formed by applying or laminating a solder resist resin on the entire surface of the wiring pattern to form a protective layer (solder resist layer). An opening is provided in the insulating resin layer for electrical connection with the electrode portion of the wiring pattern.
【０００５】次に前記開口部に外部端子、例えばハンダ
ボールを搭載する。次に、ダイシング装置を用いて断裁
し、面付けされた半導体素子を個片化して、半導体装置
のチップサイズパッケージ（半導体素子と略同一の大き
さとした半導体装置）を製造する。Next, an external terminal such as a solder ball is mounted in the opening. Next, it is cut using a dicing device, and the faced semiconductor elements are diced into individual pieces to manufacture a chip size package of the semiconductor device (a semiconductor device having substantially the same size as the semiconductor element).
【０００６】図６は、従来の技術の製造方法で得られた
チップサイズパッケージの一例を示す部分側断面図であ
る。半導体素子のサイズと半導体装置のサイズとは略同
じサイズに仕上がっている。図６の側断面図は、基板と
なるウエハー２表面に形成された半導体素子の電極３
が、導通するバイアホールによって外部端子１１に接続
した半導体装置を示している。前記半導体装置の両サイ
ドには絶縁樹脂層は形成されていないチップサイズパッ
ケージである。FIG. 6 is a partial side sectional view showing an example of a chip size package obtained by a conventional manufacturing method. The size of the semiconductor element and the size of the semiconductor device are almost the same. The side sectional view of FIG. 6 shows an electrode 3 of a semiconductor element formed on the surface of a wafer 2 which is a substrate.
Shows a semiconductor device connected to the external terminal 11 by a conductive via hole. It is a chip size package in which an insulating resin layer is not formed on both sides of the semiconductor device.
【０００７】上述したウエハー上で一括処理する製造方
法では、前記配線パターンの配線領域は、半導体素子の
サイズ内に制限され、半導体素子のサイズ以上の配線領
域を持つ半導体装置のチップサイズパッケージは作成で
きないという問題がある。In the above-described manufacturing method for performing batch processing on a wafer, the wiring area of the wiring pattern is limited to the size of the semiconductor element, and a chip size package of a semiconductor device having a wiring area larger than the size of the semiconductor element is produced. There is a problem that you cannot do it.
【０００８】又、従来のウエハー一括処理の製造方法で
はファンアウト構造のチップサイズパッケージを製造で
きないという問題がある。Further, there is a problem in that a chip-size package having a fan-out structure cannot be manufactured by the conventional manufacturing method for batch processing of wafers.
【０００９】近年、配線パターンの高密度化、微細化、
及び電極数の増加する多ピン化等、に対応するため配線
領域の拡大と、ファンアウト構造のチップサイズパッケ
ージをウエハー一括処理の製造方法により製造するこ
と、等が望まれている。又、製造コストを削減すること
が要望されている。In recent years, wiring patterns have become denser and finer,
In order to cope with the increase in the number of electrodes and the increase in the number of pins, it is desired to expand the wiring region and manufacture a chip size package having a fan-out structure by a wafer batch processing method. It is also desired to reduce the manufacturing cost.
【００１０】[0010]
【発明が解決しようとする課題】本発明の課題は、上記
の問題を解決しようとするもので、ウエハー一括処理で
あっても、ファンアウト構造のチップサイズパッケージ
を得ることのできるチップサイズパッケージの製造方法
を提供するものである。SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems, and to provide a chip size package which can obtain a fan out structure chip size package even in the wafer batch processing. A manufacturing method is provided.
【００１１】[0011]
【課題を解決するための手段】本発明の請求項１に係る
発明は、半導体装置を製造するチップサイズパッケージ
の製造方法において、（ａ）多数の半導体素子が形成さ
れたウエハーの裏面に保護テープを貼り付ける工程と、
（ｂ）前記ウエハーの表面から保護テープの表面まで断
裁を行い、半導体素子を個々に分離した後、所定の割合
（％）まで、保護テープを拡張する事により、半導体素
子間に所定の隙間を形成する工程と、（ｃ）前記ウエハ
ーの表面全面に絶縁性樹脂を塗布し、半導体素子表面、
及び前記半導体素子間の隙間までを覆う絶縁樹脂層を形
成する工程と、（ｄ）前記保護テープを剥離する工程
と、（ｅ）前記絶縁樹脂層に、半導体素子の電極と導通
を取るためのバイアホールを孔設する工程と、（ｆ）前
記絶縁樹脂層全面にバイアホール内壁までを覆う配線層
を形成後、該配線層に所定の配線パターンを形成する工
程と、（ｇ）前記配線パターン、及び前記絶縁樹脂層を
覆うよう全面に配線保護層を形成後、前記配線保護層
に、配線パターンの電極と導通を取るためのホールを孔
設後、外部接続端子を形成する工程と、（ｈ）前記ウエ
ハーから、半導体装置を個々に切断個片化し、チップサ
イズパッケージを得る工程とを有することを特徴とする
チップサイズパッケージの製造方法である。According to a first aspect of the present invention, in a method of manufacturing a chip size package for manufacturing a semiconductor device, (a) a protective tape is provided on the back surface of a wafer on which a large number of semiconductor elements are formed. And the process of sticking
(B) After cutting from the surface of the wafer to the surface of the protective tape and separating the semiconductor elements individually, the protective tape is expanded to a predetermined ratio (%) to form a predetermined gap between the semiconductor elements. Forming step, and (c) applying an insulating resin to the entire surface of the wafer to form a semiconductor element surface,
And a step of forming an insulating resin layer covering even a gap between the semiconductor elements, (d) a step of peeling the protective tape, and (e) a step of electrically connecting the insulating resin layer to an electrode of the semiconductor element. Forming a via hole; (f) forming a wiring layer covering the inner wall of the via hole on the entire surface of the insulating resin layer, and then forming a predetermined wiring pattern on the wiring layer; and (g) the wiring pattern. And a step of forming a wiring protective layer on the entire surface so as to cover the insulating resin layer, forming a hole in the wiring protective layer for establishing electrical connection with an electrode of a wiring pattern, and then forming an external connection terminal, h) A step of producing a chip size package by individually cutting semiconductor devices from the wafer to obtain a chip size package.
【００１２】次に、本発明の請求項２に係る発明は、請
求項１記載の工程（ｆ）前記ウエハーの表面から、前記
絶縁樹脂層全面にバイアホール内壁までを覆うよう全面
に配線層を形成後、該配線層に所定の配線パターンを形
成する工程が終了した後、（ａ）前記配線パターン、及
び前記絶縁樹脂層を覆うよう全面に絶縁樹脂層を形成す
る工程と、（ｂ）前記絶縁樹脂層に、半導体素子の電極
と導通を取るためのバイアホールを孔設する工程と、
（ｃ）前記絶縁樹脂層全面にバイアホール内壁までを覆
う配線層を形成後、該配線層に所定の配線パターンを形
成する工程と、を繰り返し、半導体素子の上面に、配線
パターンを２層以上に多層化する事を特徴とする請求項
１記載のチップサイズパッケージの製造方法である。Next, the invention according to claim 2 of the present invention is the step (f) according to claim 1, in which a wiring layer is formed on the entire surface of the wafer from the surface of the wafer to cover the inner wall of the via hole. After formation, after the step of forming a predetermined wiring pattern on the wiring layer is completed, (a) a step of forming an insulating resin layer on the entire surface so as to cover the wiring pattern and the insulating resin layer; A step of forming a via hole in the insulating resin layer for establishing conduction with the electrode of the semiconductor element,
(C) The step of forming a wiring layer covering the inner wall of the via hole on the entire surface of the insulating resin layer and then forming a predetermined wiring pattern on the wiring layer is repeated to form two or more wiring patterns on the upper surface of the semiconductor element. The method for manufacturing a chip size package according to claim 1, wherein the chip size package is multi-layered.
【００１３】次に、本発明の請求項３に係る発明は、半
導体装置を製造するチップサイズパッケージの製造方法
において、（ａ）多数の半導体素子が形成されたウエハ
ーの裏面に保護テープを貼り付ける工程と、（ｂ）前記
ウエハーの表面から保護テープの表面まで断裁を行い、
半導体素子を個々に分離した後、所定の割合（％）ま
で、保護テープを拡張する事により、半導体素子間に所
定の隙間を形成する工程と、（ｃ）前記ウエハーの表面
全面に絶縁樹脂を塗布し、半導体素子表面、及び前記半
導体素子間の隙間まで覆う絶縁樹脂層を形成する工程
と、（ｄ）前記保護テープを剥離する工程と、（ｅ）前
記ウエハーの裏面全面に絶縁樹脂層を形成する工程と、
（ｆ）前記ウエハーの裏面側の絶縁樹脂層に、半導体素
子の電極と導通を取るため、前記絶縁樹脂層にバイアホ
ールを孔設、及び前記半導体装置間の隙間の絶縁樹脂層
部位にウエハー表面から裏面まで貫通する貫通孔を孔設
する工程と、（ｇ）前記ウエハーの表面側の絶縁樹脂層
に、半導体素子の電極と導通を取るためのバイアホール
を孔設する工程と、（ｈ）前記ウエハーの裏面側の絶縁
樹脂層全面にバイアホール、及び貫通孔の内壁までを覆
う配線層を形成後、該配線層に所定の配線パターンを形
成する工程と、（ｉ）前記ウエハーの表面側の絶縁樹脂
層全面にバイアホール内壁までを覆う、配線層を形成
後、該配線層に所定の配線パターンを形成する工程と、
（ｊ）前記ウエハーの表面側に、前記配線パターン、及
び前記絶縁樹脂層を覆うよう全面に配線保護層を形成す
る工程と、（ｋ）前記ウエハーの裏面側に、前記配線パ
ターン、及び前記絶縁樹脂層までを覆うよう全面に配線
保護層を形成後、前記配線保護層に、配線パターンの電
極と導通を取るためのホールを孔設後、外部接続端子を
形成する工程と、（ｌ）前記ウエハーから、半導体装置
を個々に切断個片化し、チップサイズパッケージを得る
工程とを有することを特徴とするチップサイズパッケー
ジの製造方法である。Next, the invention according to claim 3 of the present invention is, in a method of manufacturing a chip size package for manufacturing a semiconductor device, (a) attaching a protective tape to the back surface of a wafer on which a large number of semiconductor elements are formed. And (b) cutting from the surface of the wafer to the surface of the protective tape,
After separating the semiconductor elements individually, a step of forming a predetermined gap between the semiconductor elements by expanding the protective tape up to a predetermined rate (%), and (c) applying an insulating resin to the entire surface of the wafer. Coating, forming an insulating resin layer covering the surface of the semiconductor element and the gap between the semiconductor elements, (d) removing the protective tape, and (e) forming an insulating resin layer on the entire back surface of the wafer. Forming process,
(F) In the insulating resin layer on the back surface side of the wafer, via holes are formed in the insulating resin layer to establish electrical continuity with the electrodes of the semiconductor element, and the wafer surface is formed in the insulating resin layer portion in the gap between the semiconductor devices. Through (g) to a back surface, and (g) forming a via hole in the insulating resin layer on the front surface side of the wafer for establishing electrical connection with the electrode of the semiconductor element, and (h). A step of forming a via hole and a wiring layer covering the inner wall of the through hole on the entire surface of the insulating resin layer on the back surface of the wafer, and then forming a predetermined wiring pattern on the wiring layer, and (i) a front surface side of the wafer A step of forming a wiring layer on the entire surface of the insulating resin layer up to the inner wall of the via hole, and then forming a predetermined wiring pattern on the wiring layer,
(J) a step of forming a wiring protection layer on the entire surface so as to cover the wiring pattern and the insulating resin layer on the front surface side of the wafer; and (k) the wiring pattern and the insulation on the back surface side of the wafer. Forming a wiring protection layer on the entire surface to cover the resin layer, forming holes in the wiring protection layer for establishing electrical connection with the electrodes of the wiring pattern, and then forming external connection terminals; And a step of obtaining a chip size package by individually cutting a semiconductor device from a wafer to obtain a chip size package.
【００１４】次に、本発明の請求項４に係る発明は、請
求項３記載の工程（ｈ）前記ウエハーの裏面側の前記絶
縁樹脂層全面にバイアホール、及び貫通孔の内壁までを
覆う配線層を形成後、該配線層に所定の配線パターンを
形成する工程が、終了後に、（ａ）前記ウエハーの裏面
側全面に、前記配線パターン、及び前記絶縁層を覆う絶
縁樹脂層を形成する工程と、（ｂ）前記ウエハーの裏面
側に、半導体素子の電極と導通を取るため、前記絶縁樹
脂層にバイアホールを孔設、及び前記半導体装置間の隙
間の絶縁樹脂層部位に貫通孔を孔設する工程と、（ｃ）
前記ウエハーの裏面側全面に前記絶縁樹脂層からバイア
ホール、及び貫通孔の内壁までを覆う配線層を形成後、
該配線層に所定の配線パターンを形成する工程と、を繰
り返し、前記ウエハーの裏面に、配線パターンを２層以
上に多層化する事を特徴とする請求項３記載のチップサ
イズパッケージの製造方法である。Next, the invention according to claim 4 of the present invention is the step (h) according to claim 3, wherein the wiring covers the entire surface of the insulating resin layer on the back surface side of the wafer, the via hole and the inner wall of the through hole. After forming the layer, after the step of forming a predetermined wiring pattern on the wiring layer is completed, (a) forming an insulating resin layer covering the wiring pattern and the insulating layer on the entire rear surface of the wafer. (B) On the back surface side of the wafer, a via hole is formed in the insulating resin layer in order to establish electrical continuity with the electrode of the semiconductor element, and a through hole is formed in the insulating resin layer portion in the gap between the semiconductor devices. The step of setting, (c)
After forming a wiring layer covering from the insulating resin layer to the via hole and the inner wall of the through hole on the entire back surface of the wafer,
4. The method for manufacturing a chip size package according to claim 3, wherein the step of forming a predetermined wiring pattern on the wiring layer is repeated to form the wiring pattern on the back surface of the wafer in two or more layers. is there.
【００１５】[0015]
【００１６】本発明のチップサイズパッケージの製造方
法について詳細に説明する。The method for manufacturing the chip size package of the present invention will be described in detail.
【００１７】図１は、本発明の製造方法で得られたチッ
プサイズパッケージの一例を示す部分側断面図である。FIG. 1 is a partial side sectional view showing an example of a chip size package obtained by the manufacturing method of the present invention.
【００１８】図１の側断面図は、基板となるウエハー２
表面に形成された半導体素子の電極３が、導通するバイ
アホールによって外部端子１１と接続された半導体装置
である。本発明の方法によれば、前記半導体の両サイド
には絶縁樹脂部が形成され、両サイドにも回路が形成さ
れたチップサイズパッケージとなっている。The side sectional view of FIG. 1 shows a wafer 2 which is a substrate.
This is a semiconductor device in which the electrode 3 of the semiconductor element formed on the surface is connected to the external terminal 11 by a conductive via hole. According to the method of the present invention, an insulating resin portion is formed on both sides of the semiconductor, and a circuit is formed on both sides of the semiconductor chip package.
【００１９】図２は、本発明の製造方法で得られたチッ
プサイズパッケージの一例を示す部分側断面図である。FIG. 2 is a partial side sectional view showing an example of a chip size package obtained by the manufacturing method of the present invention.
【００２０】図２の側断面図は、基板となるウエハー２
表面に形成された半導体素子の電極３が、導通する貫通
孔１２（貫通スルホール１３）によって、ウエハーの裏
面に形成する配線パターンと回路を形成し、前記回路と
導通するバイアホールによって外部端子１１と回路を形
成した半導体装置である。前記半導体の両サイドは本発
明の方法により形成した絶縁樹脂部に前記貫通スルホー
ル１３が形成されたチップサイズパッケージである。The side sectional view of FIG. 2 shows a wafer 2 which is a substrate.
The electrode 3 of the semiconductor element formed on the front surface forms a wiring pattern and a circuit formed on the back surface of the wafer by the through hole 12 (through through hole 13) that conducts, and the external terminal 11 and the external terminal 11 by the via hole that conducts with the circuit. It is a semiconductor device in which a circuit is formed. Both sides of the semiconductor are chip size packages in which the through-holes 13 are formed in the insulating resin portion formed by the method of the present invention.
【００２１】本発明のチップサイズパッケージの製造方
法を、図３を用いて説明する。図３（ａ）は、多数の半
導体素子１４が面付けして形成されたウエハー２であ
る。次いで、図３（ｂ）に示すように、多数の半導体素
子が形成されたウエハーの裏面に保護テープ４（ダイシ
ングテープ）を貼り付ける。A method of manufacturing the chip size package of the present invention will be described with reference to FIG. FIG. 3A shows a wafer 2 formed by mounting a large number of semiconductor elements 14 on the surface. Next, as shown in FIG. 3B, a protective tape 4 (dicing tape) is attached to the back surface of the wafer on which a large number of semiconductor elements are formed.
【００２２】次いで、前記ウエハーの表面側から保護テ
ープ４の表面まで断裁を行い、前記半導体素子１４を個
々に切断分離する。次いで図３（ｃ）に示すように、保
護テープを面方向に引っ張る。これにより保護テープは
図中の矢印方向に所定の割合（％）まで拡張される事に
より、保護テープ上に有る半導体素子間には所定の隙間
が形成される。次いで、図３（ｄ）に示すように、前記
ウエハーの表面から絶縁樹脂を塗布し、前記半導体素子
間の隙間までを覆う絶縁樹脂層５を全面に形成する。次
に、前記ウエハーの裏面から、前記保護テープを剥離す
る。ここで前記の剥離後に、図３（ｄ）に示すように、
例えば、ヒートシンク用の銅板６を裏面に貼り合わせて
も構わない。Next, cutting is performed from the surface side of the wafer to the surface of the protective tape 4, and the semiconductor elements 14 are individually cut and separated. Next, as shown in FIG. 3C, the protective tape is pulled in the surface direction. As a result, the protective tape is expanded to a predetermined ratio (%) in the direction of the arrow in the figure, so that a predetermined gap is formed between the semiconductor elements on the protective tape. Next, as shown in FIG. 3D, an insulating resin is applied from the surface of the wafer to form an insulating resin layer 5 covering the entire space between the semiconductor elements. Next, the protective tape is peeled off from the back surface of the wafer. Here, after the peeling, as shown in FIG.
For example, the copper plate 6 for heat sink may be attached to the back surface.
【００２３】次いで、図３（ｅ）に示すように、前記ウ
エハーの表面側に形成した前記絶縁樹脂層５に、半導体
素子の電極と導通を取るためのバイアホール７を孔設す
る。前記孔設の一手段として、レーザー光による孔明け
加工機を使用することが望ましい。Next, as shown in FIG. 3 (e), a via hole 7 is formed in the insulating resin layer 5 formed on the front surface side of the wafer to establish continuity with the electrode of the semiconductor element. As a means for forming the holes, it is desirable to use a laser beam drilling machine.
【００２４】次に、図３（ｆ）に示すように、前記ウエ
ハーの表面側から、前記絶縁樹脂層からバイアホール内
壁まで全面に、無電解めっき法を用いて、無電解めっき
層８を形成する。Next, as shown in FIG. 3F, an electroless plating layer 8 is formed on the entire surface from the surface side of the wafer to the inner wall of the via hole by the electroless plating method. To do.
【００２５】次いで、前記無電解めっき層８の全面に感
光性レジスト層を形成した後、予め準備したフォトマス
クを用い感光性レジスト層へのパターン露光し、現像も
行い、前記無電解めっき層に所定の配線パターンを有す
るレジストパターンを形成する。次いで、前記レジスト
パターンの表面、及びレジストパターンから露出した無
電解めっき層部位に、電解めっき層を形成し、前記レジ
スト層を剥離除去した後、該表面に露出する無電解めっ
き層をソフトエッチング法によって除去し、独立した導
体回路の配線パターン１０を形成する。Then, after forming a photosensitive resist layer on the entire surface of the electroless plating layer 8, the photosensitive resist layer is subjected to pattern exposure and development using a photomask prepared in advance, and the electroless plating layer is formed. A resist pattern having a predetermined wiring pattern is formed. Then, an electrolytic plating layer is formed on the surface of the resist pattern and the electroless plating layer portion exposed from the resist pattern, and after removing the resist layer by peeling, the electroless plating layer exposed on the surface is soft-etched by a method. Then, the wiring pattern 10 of the independent conductor circuit is formed.
【００２６】次いで、前記ウエハーの表面から、前記配
線パターンから絶縁層まで、全面に配線保護するソルダ
ーレジスト層９を形成後、前記ソルダーレジスト層に、
配線パターンの電極と導通を取るためのホールを孔設す
る。前記孔設はレーザー光による孔明け加工機を使用す
る。次に、前記ホールに外部接続端子、例えばハンダボ
ールを装着形成する。（図３（ｇ）参照）Next, after forming a solder resist layer 9 for protecting the wiring from the surface of the wafer to the wiring pattern to the insulating layer, the solder resist layer 9 is formed on the solder resist layer.
A hole is provided to establish electrical connection with the electrode of the wiring pattern. A laser beam machine is used to form the holes. Next, an external connection terminal, for example, a solder ball is attached and formed in the hole. (See Fig. 3 (g))
【００２７】次いで、図３（ｈ）に示すように、前記ウ
エハーから、半導体装置１を個々に切断個片化し分離す
ることでチップサイズパッケージを得る。上述した説明
では、半導体素子の上面に配線パターンを１層形成する
事例につき述べたが、半導体素子上に２層以上の配線パ
ターンを形成することも可能である。以下その方法を説
明する。Next, as shown in FIG. 3H, the semiconductor device 1 is individually cut into individual pieces from the wafer to obtain a chip size package. In the above description, an example of forming one wiring pattern on the upper surface of the semiconductor element has been described, but it is also possible to form two or more wiring patterns on the semiconductor element. The method will be described below.
【００２８】まず、前述した工程に従いウエハーの表面
に、所定の配線パターンを形成する工程まで行う。この
とき、図３（ｇ）のソルダーレジスト層９、外部接続端
子１１を有しない状態となっている。次いで、図３
（ｄ）に示すように、前記ウエハーの表面側に、前記配
線パターンから前記絶縁層まで、全面に絶縁樹脂層を形
成する。次に、図３（ｅ）に示すように、前記ウエハー
の表面から、前記絶縁樹脂層に、半導体素子の電極と導
通を取るためのバイアホールを孔設する。次に、図３
（ｆ）に示すように、前記ウエハーの表面から、前記絶
縁樹脂層からバイアホール内壁まで、全面に、無電解め
っき層を形成する。次いで、感光性レジスト層を形成し
た後、予め準備したフォトマスクを用いてレジスト層へ
のパターン露光し、現像をおこない、該無電解めっき層
に所定の配線パターンを有するレジストパターンを形成
する。次いで前記レジストパターンの表面に、電解めっ
き層を形成した後、前記レジスト層を剥離除去し、該表
面に露出する無電解めっき層をソフトエッチング法によ
って除去し、配線パターン１０を形成する。（図３
（ｇ）参照）以上の図３（ｄ）と、図３（ｅ）と、図３
（ｆ）と、図３（ｇ）の４工程を繰り返し行うことで、
半導体素子の上面に、配線パターンを２層以上の多層化
配線を備えたチップサイズパッケージの製造が可能とな
る。First, the steps up to the step of forming a predetermined wiring pattern on the surface of the wafer are performed according to the steps described above. At this time, the solder resist layer 9 and the external connection terminals 11 of FIG. Then, FIG.
As shown in (d), an insulating resin layer is formed on the entire surface of the wafer from the wiring pattern to the insulating layer. Next, as shown in FIG. 3E, a via hole is formed in the insulating resin layer from the surface of the wafer to establish electrical connection with the electrode of the semiconductor element. Next, FIG.
As shown in (f), an electroless plating layer is formed on the entire surface from the surface of the wafer, from the insulating resin layer to the inner wall of the via hole. Then, after forming a photosensitive resist layer, pattern exposure is performed on the resist layer using a photomask prepared in advance and development is performed to form a resist pattern having a predetermined wiring pattern on the electroless plating layer. Next, after forming an electrolytic plating layer on the surface of the resist pattern, the resist layer is peeled and removed, and the electroless plating layer exposed on the surface is removed by a soft etching method to form the wiring pattern 10. (Fig. 3
(See (g)) FIG. 3 (d) above, FIG. 3 (e), and FIG.
By repeating (f) and the four steps of FIG. 3 (g),
It is possible to manufacture a chip size package having a multilayer wiring having two or more wiring patterns on the upper surface of the semiconductor element.
【００２９】なお、上記の配線パターンの形成方法は、
サブトラクテイブ法、又はセミアデテイブ法、若しくは
フルアデテイブ法であってもよく、適宜選択しても構わ
ない。The method of forming the wiring pattern is as follows.
It may be a subtractive method, a semi-additive method, or a full-additive method, and may be appropriately selected.
【００３０】次に、図４、図５を用いて本発明のチップ
サイズパッケージの他の製造方法を説明する。図４
（ａ）は、多数の半導体素子１４が面付け形成されたウ
エハー２である。次いで、図４（ｂ）に示すように、前
記ウエハーの裏面に保護テープ４（ダイシングテープ）
を貼り付けた後、ウエハー２を保護テープ４の表面まで
断裁し、半導体素子１４を個々に切断分離する。次い
で、図４（ｃ）に示すように、保護テープを面方向に引
っ張る。これにより保護テープは図中矢印方向に所定の
割合（％）まで拡張する事により、保護テープ上にある
半導体素子間には所定の隙間が形成される。Next, another method of manufacturing the chip size package of the present invention will be described with reference to FIGS. Figure 4
(A) is a wafer 2 on which a large number of semiconductor elements 14 are formed by imposition. Then, as shown in FIG. 4B, a protective tape 4 (dicing tape) is formed on the back surface of the wafer.
After sticking, the wafer 2 is cut to the surface of the protective tape 4, and the semiconductor elements 14 are individually cut and separated. Next, as shown in FIG. 4C, the protective tape is pulled in the surface direction. As a result, the protective tape expands to a predetermined ratio (%) in the direction of the arrow in the figure, so that a predetermined gap is formed between the semiconductor elements on the protective tape.
【００３１】次いで、図４（ｄ）に示すように、前記ウ
エハーの表面側から、絶縁樹脂を塗布し前記半導体素子
間の隙間までを覆う絶縁樹脂層５を全面に形成する。次
に、前記ウエハーの裏面から、前記ダイシングテープ４
を剥離する。Next, as shown in FIG. 4D, an insulating resin is applied from the front surface side of the wafer to form an insulating resin layer 5 covering the entire space between the semiconductor elements. Next, from the back surface of the wafer, the dicing tape 4
Peel off.
【００３２】次いで、図４（ｅ）に示すように、前記ウ
エハーの裏面側全面に絶縁樹脂層５を形成する。Next, as shown in FIG. 4E, an insulating resin layer 5 is formed on the entire back surface of the wafer.
【００３３】次いで、前記ウエハーの表面側に、半導体
素子の電極と導通を取るため、前記絶縁樹脂層へのバイ
アホール７を孔設と、前記半導体素子間の隙間に絶縁樹
脂層を形成した形成部にウエハー表面から裏面まで貫通
する貫通ホール１２のとを孔設する。但し、場合によっ
ては、前記バイアホール７の孔設は不要となることも有
るため適宜選択する必要がある。（図４（ｆ）参照）な
お、前記バイアホール７と貫通ホール１２の孔設はレー
ザー光による孔明け加工機を使用することが望ましい。
また、貫通ホール１２の孔説はウエハー裏面側から行う
ことが望ましい。Next, a via hole 7 is formed in the insulating resin layer on the front surface side of the wafer to establish electrical connection with the electrode of the semiconductor element, and an insulating resin layer is formed in the gap between the semiconductor elements. A through hole 12 is formed in the portion to penetrate from the front surface to the back surface of the wafer. However, in some cases, it may not be necessary to form the via hole 7, and thus it is necessary to select it appropriately. (See FIG. 4 (f)) It is desirable to use a laser beam drilling machine for forming the via hole 7 and the through hole 12.
Further, it is desirable that the through hole 12 be formed from the back side of the wafer.
【００３４】次いで、前記ウエハーの表面側と、裏面側
とに、両面の前記絶縁樹脂層５、及びバイアホール７、
前記貫通ホール１２の内壁までを覆うよう全面に、無電
解めっき層８を形成する。（図４（ｇ）参照）Next, the insulating resin layer 5 on both sides and the via hole 7 are formed on the front surface side and the back surface side of the wafer.
An electroless plating layer 8 is formed on the entire surface to cover the inner wall of the through hole 12. (See Fig. 4 (g))
【００３５】次いで、ウエハーの両面の前記無電解めっ
き層に、感光性レジスト層を形成した後、予め準備した
フォトマスクを用いて感光性レジスト層へのパターン露
光し、現像を行うことで、前記無電解めっき層に所定の
配線パターンを有するレジストパターンを形成する。Next, a photosensitive resist layer is formed on the electroless plating layers on both sides of the wafer, and then the photosensitive resist layer is subjected to pattern exposure using a photomask prepared in advance and development is performed, whereby A resist pattern having a predetermined wiring pattern is formed on the electroless plating layer.
【００３６】次いで、前記レジストパターンの表面に、
電解めっき法を用いて、電解めっき層を形成し、前記レ
ジスト層を剥離除去した後、前記ウエハー両表面に露出
する無電解めっき層をソフトエッチング法によって除去
し、ウエハー両面に独立した導体回路の配線パターン１
０を形成する。（図５（ｈ）参照）Then, on the surface of the resist pattern,
By using an electrolytic plating method, an electrolytic plating layer is formed, the resist layer is peeled and removed, and then the electroless plating layers exposed on both surfaces of the wafer are removed by a soft etching method. Wiring pattern 1
Form 0. (See Fig. 5 (h))
【００３７】次に、前記ウエハーの表面側に、前記配線
パターンから前記絶縁層までを覆うよう全面に配線保護
層としてのソルダーレジスト層９を形成する。次に、前
記ウエハーの裏面側に、前記配線パターンから前記絶縁
層までを覆うよう全面に配線保護層としてのソルダーレ
ジスト層９を形成後、前記ソルダーレジスト層に、配線
パターンの電極と導通を取るためのホールを孔設する。
前記ホールに外部接続端子１１を、例えばハンダボール
等を装着形成する。（図５（ｉ）参照）Next, a solder resist layer 9 as a wiring protection layer is formed on the entire surface of the front surface of the wafer so as to cover the wiring pattern and the insulating layer. Next, a solder resist layer 9 as a wiring protection layer is formed on the entire back surface of the wafer so as to cover the wiring pattern and the insulating layer, and then the solder resist layer is electrically connected to the electrodes of the wiring pattern. A hole will be provided for this purpose.
An external connection terminal 11, for example, a solder ball or the like is attached and formed in the hole. (See Figure 5 (i))
【００３８】前記ウエハーを断裁し、半導体装置１を個
々に切断個片化し、チップサイズパッケージを得る。
（図５（ｊ）参照）上述した説明では、半導体素子の裏
面に配線パターンを１層形成する事例に付き述べたが、
半導体素子の裏面に２層以上の配線パターンを形成する
ことも可能である。The wafer is cut and the semiconductor device 1 is cut into individual pieces to obtain a chip size package.
(See FIG. 5 (j)) In the above description, an example of forming one layer of the wiring pattern on the back surface of the semiconductor element has been described.
It is also possible to form a wiring pattern of two or more layers on the back surface of the semiconductor element.
【００３９】まず、前述した工程に従い、図５（ｈ）に
示すように、前記ウエハーの両面に、所定の配線パター
ン１０を形成する工程が終了した後に、図４（ｅ）に示
すように、前記ウエハーの裏面側に、前記配線パターン
から前記絶縁層までを覆うよう全面に絶縁樹脂層５を形
成する。次に、図４（ｆ）に示すように、前記絶縁樹脂
層にバイアホールの孔設と、前記半導体素子間の隙間に
絶縁樹脂層を形成した形成部を貫通する貫通孔を孔設す
る。次に、図４（ｇ）に示すように、前記ウエハーの裏
面側に、前記絶縁樹脂層、及びホール内壁までを覆うよ
う全面に無電解めっき８層を形成する。次に、前記ウエ
ハーの裏面側の無電解めっき層全面に、レジスト層を形
成した後、前記レジスト層を所定の配線パターンを有す
るレジストパターンを形成する。次に、前記レジストパ
ターンの表面側に、電解めっき層を形成し、前記レジス
ト層を剥離除去し、前記電解めっき層の表面に露出する
無電解めっき層をソフトエッチング法によって除去し、
配線パターン１０を形成する。（図５（ｈ）参照）First, according to the above-mentioned process, as shown in FIG. 5H, after the process of forming the predetermined wiring patterns 10 on both surfaces of the wafer is completed, as shown in FIG. An insulating resin layer 5 is formed on the entire back surface of the wafer so as to cover the wiring pattern and the insulating layer. Next, as shown in FIG. 4F, a via hole is formed in the insulating resin layer, and a through hole is formed in the gap between the semiconductor elements, the through hole penetrating the forming portion where the insulating resin layer is formed. Next, as shown in FIG. 4G, eight layers of electroless plating are formed on the entire back surface of the wafer so as to cover the insulating resin layer and the inner wall of the hole. Next, after forming a resist layer on the entire surface of the electroless plating layer on the back surface side of the wafer, a resist pattern having a predetermined wiring pattern is formed on the resist layer. Next, on the surface side of the resist pattern, an electrolytic plating layer is formed, the resist layer is peeled off, and the electroless plating layer exposed on the surface of the electrolytic plating layer is removed by a soft etching method,
The wiring pattern 10 is formed. (See Fig. 5 (h))
【００４０】すなわち、ウエハーの裏面から、以上の図
４（ｅ）と、図４（ｆ）と、図４（ｇ）と、図５（ｈ）
の４工程を繰り返し行うことで、半導体素子を形成した
ウエハーの裏面に、配線パターンを２層以上の多層化配
線を備えたチップサイズパッケージの製造カ゛可能とな
る。That is, from the back surface of the wafer, the above FIG. 4 (e), FIG. 4 (f), FIG. 4 (g), and FIG.
By repeating the above four steps, it is possible to manufacture a chip size package having a multilayer wiring having two or more wiring patterns on the back surface of the wafer on which the semiconductor element is formed.
【００４１】[0041]
【作用】ウエハー一括処理方法では、ウエハーから半導
体装置を個片に断裁するダイシング工程が従来の製造方
法では工程の最後に行っている。しかし、本発明の方法
は保護テープの貼付け後に断裁する。これにより、配線
エリアを広げる作用がある。In the wafer batch processing method, the dicing step of cutting the semiconductor device into individual pieces from the wafer is performed at the end of the step in the conventional manufacturing method. However, the method of the present invention cuts after applying the protective tape. This has the effect of expanding the wiring area.
【００４２】[0042]
【実施例】次に、本発明の、以下に具体的な実施例に従
って説明する。EXAMPLES Next, the present invention will be described below with reference to specific examples.
【００４３】＜実施例１＞図３は、本発明の図１に示す
チップサイズパッケージの製造方法の一実施例を説明す
る工程図である。<Embodiment 1> FIG. 3 is a process chart for explaining an embodiment of a method for manufacturing the chip size package shown in FIG. 1 of the present invention.
【００４４】まず、図３（ａ）に示すように、Ｓｉ材の
ウェハー２上に、Ａｌ材からなる電極パッドを形成した
多数の半導体素子１４が形成された８インチφウエハー
２を準備した。First, as shown in FIG. 3A, an 8-inch φ wafer 2 was prepared in which a large number of semiconductor elements 14 each having an electrode pad made of an Al material were formed on the wafer 2 made of a Si material.
【００４５】次に、図３（ｂ）に示すように、前記ウエ
ハー２の裏面に保護テープ４を貼り合わせた。前記テー
プは（株）リンテック製、商品名：ダイシングテープ−
Ｄ６７５を使用した。Next, as shown in FIG. 3B, a protective tape 4 was attached to the back surface of the wafer 2. The tape is manufactured by Lintec Co., Ltd., product name: Dicing Tape-
D675 was used.
【００４６】次に、図３（ｃ）に示すように、ダイシン
グ装置を用いて、ウエハーの表面から断裁を行い、半導
体素子１４を個々に切断分離した。このとき、保護テー
プの切断は行わない。Next, as shown in FIG. 3C, a dicing device was used to cut the surface of the wafer, and the semiconductor elements 14 were individually cut and separated. At this time, the protective tape is not cut.
【００４７】次に、ウエハー拡張器を用いて、前記保護
テープ４を均等に拡張し、半導体素子間に所定の隙間を
形成した。（図３（ｃ）参照）Next, the protective tape 4 was evenly expanded using a wafer expander to form a predetermined gap between the semiconductor elements. (See Fig. 3 (c))
【００４８】次に、ウエハーの表面側に絶縁樹脂層５を
形成した。前記絶縁樹脂層はドライフイルムを用いて形
成したものであり、前記ドライフイルムは味の素（株）
製の商品名：ＡＢＦ−７０Ｈを使用し、真空ラミネータ
ー法により、９０℃に加熱しながら積層した。次に、室
温にて冷却した後、前記ドライフイルムの支持フイルム
を剥離し、熱風乾燥炉に入れて、１５０℃、３０分のポ
ストキュアー加熱を行った。Next, the insulating resin layer 5 was formed on the front surface side of the wafer. The insulating resin layer is formed by using dry film, and the dry film is manufactured by Ajinomoto Co., Inc.
Product name: ABF-70H was used and laminated by a vacuum laminator method while heating to 90 ° C. Next, after cooling at room temperature, the supporting film of the dry film was peeled off, put in a hot air drying furnace, and post cure heating was carried out at 150 ° C. for 30 minutes.
【００４９】次に、ウエハーの裏面側より前記保護テー
プ４を剥離した後、ウエハー裏面に接着剤を用いてヒー
トシンク用の銅版６を貼りつけた。（図３（ｄ）参照）Next, after peeling off the protective tape 4 from the back side of the wafer, a copper plate 6 for heat sink was attached to the back side of the wafer using an adhesive. (See Fig. 3 (d))
【００５０】次に、図３（ｅ）に示すように、ビーム径
が１５０μｍφの炭酸ガスレーザー光を用いて、前記絶
縁樹脂層５の所定の位置に孔径が１２０μｍφバイアホ
ール用孔７を形成した。Next, as shown in FIG. 3E, a carbon dioxide gas laser beam having a beam diameter of 150 μmφ was used to form a via hole 7 having a hole diameter of 120 μmφ at a predetermined position of the insulating resin layer 5. .
【００５１】バイアホール用孔７を形成後、ＫＭｎＯ
４：濃度６０ｇ／ｌ、ＮａＯＨ：濃度４０ｇ／ｌからな
るデスミア溶液で、温度８０℃、１０分間洗浄処理し、
バイアホール用孔７内壁に付着した異物、例えばエポキ
シ樹脂成分等からなる残査を解除去した。その後、硫酸
ヒドロキシルアミン：２０ｇ／ｌ、硫酸：５０ｍｌ／ｌ
からなる中和溶液で、温度４５℃、５分間の中和処理
後、水洗した。After forming the via hole 7, KMnO
4: Wash with a desmear solution having a concentration of 60 g / l and NaOH: concentration of 40 g / l at a temperature of 80 ° C. for 10 minutes,
The foreign matter adhered to the inner wall of the via hole hole 7, for example, a residue made of an epoxy resin component was removed. Then, hydroxylamine sulfate: 20 g / l, sulfuric acid: 50 ml / l
Was neutralized at 45 ° C. for 5 minutes and then washed with water.
【００５２】次に、パラジウム触媒、アトテック（株）
製、商品名：ネオガントを使用して、絶縁樹脂層、バイ
アホール用孔内壁、及びホールの底部までの全表面に、
パラジウム核（Ｐｂ核）を付着した。Next, palladium catalyst, Atotech Co., Ltd.
Product name: Neogant is used to cover the insulating resin layer, the inner wall of the via hole, and the entire surface up to the bottom of the hole.
A palladium nucleus (Pb nucleus) was attached.
【００５３】次に、金属銅として、２．３ｇ／ｌ、ＥＤ
ＴＡを２０ｇ／ｌ、ホルマリンを２．５ｇ／ｌを基本組
成とし、水酸化ナトリウムにて、ｐＨ＝１２．５に調整
した無電解銅めっき液ジャパンエナジー（株）製の製品
名ＫＣ−５００に、空気を吹き込みながら、温度７０
℃、１５分間めっき処理して、絶縁樹脂層表面、及びバ
イアホール内の表面に、０．５μｍ厚の無電解銅めっき
層８を形成した。（図３（ｆ）参照）Next, as copper metal, 2.3 g / l, ED
Electroless copper plating solution with a basic composition of 20 g / l of TA and 2.5 g / l of formalin and adjusted to pH = 12.5 with sodium hydroxide KC-500 manufactured by Japan Energy Co., Ltd. , While blowing air, temperature 70
A plating treatment was performed at 15 ° C. for 15 minutes to form an electroless copper plating layer 8 having a thickness of 0.5 μm on the surface of the insulating resin layer and the surface in the via hole. (See Fig. 3 (f))
【００５４】次いで、ドライフイルムの感光性レジスト
を無電解銅めっき層８上全面にラミネートした後、予め
準備したフォトマスクを用いて、感光性レジストにパタ
ーン露光した後、炭酸ナトリウム溶液を用いて現像処理
した。これにより、所定のパターンを有するレジスト膜
２０μｍのレジストパターン層を形成した。Then, a photosensitive resist of dry film is laminated on the entire surface of the electroless copper-plated layer 8, and the photosensitive resist is pattern-exposed using a photomask prepared in advance, and then developed using a sodium carbonate solution. Processed. Thus, a resist pattern layer having a resist film of 20 μm having a predetermined pattern was formed.
【００５５】次に、前記ウエハーを硫酸１００ｇ／ｌの
溶液に、２５℃、１分間浸漬させた後、レジストパター
ン表面、及び前記無電解銅めっき層のレジストパターン
層からの露出面に電解めっきを行った。前記電解めっき
液は、硫酸銅濃度７０ｇ／ｌ、硫酸濃度２００ｇ／ｌ、
塩酸濃度５０ｍｇ／ｌ、添加物（奥野製薬（株）製、商
品名トップルチナＳＦ）濃度５ｍｇ／ｌ、からなるめっ
き液を使用した。電解めっき処理条件は、めっき液の温
度は２５℃に維持し、４０分間浸漬して、電流密度は、
３Ａ／ｄｍ２の条件で、電解銅めっき処理し、めっき層
の厚さ１８μｍの電解銅めっき層を形成した。Next, the wafer is immersed in a solution of 100 g / l of sulfuric acid at 25 ° C. for 1 minute, and then electrolytic plating is performed on the resist pattern surface and the exposed surface of the electroless copper plating layer from the resist pattern layer. went. The electrolytic plating solution has a copper sulfate concentration of 70 g / l, a sulfuric acid concentration of 200 g / l,
A plating solution having a hydrochloric acid concentration of 50 mg / l and an additive (Okuno Pharmaceutical Co., Ltd., trade name Toprutina SF) concentration of 5 mg / l was used. The electrolytic plating treatment conditions are as follows: the temperature of the plating solution is maintained at 25 ° C., immersion is performed for 40 minutes, and the current density is
Electrolytic copper plating was performed under the condition of 3 A / dm2 to form an electrolytic copper plated layer having a thickness of 18 μm.
【００５６】次に、前記レジスト層を剥離除去した。次
にウエハー表面の全面をソフトエッチングして、露出し
た前記無電解銅めっき層を除去した。ソフトエッチング
液は、９８％溶液の硫酸４００ｍｌ／ｌ、過酸化水素１
００ｍｌ／ｌ、からなるソフトエッチング液を使用し
た。以上の処理により独立した導体回路の配線パターン
１０を形成した。Next, the resist layer was peeled and removed. Next, the entire surface of the wafer was soft-etched to remove the exposed electroless copper plating layer. The soft etching solution is a 98% solution of sulfuric acid 400 ml / l, hydrogen peroxide 1
A soft etching solution consisting of 00 ml / l was used. By the above process, the wiring pattern 10 of the independent conductor circuit was formed.
【００５７】次に、前記配線パターン１０を保護するた
め、ソルダーレジスト層９を形成した。ソルダーレジス
ト樹脂は市販のＢＴレジンを使用して、ソルダーレジス
ト層９を形成した。Next, a solder resist layer 9 was formed in order to protect the wiring pattern 10. As the solder resist resin, a commercially available BT resin was used to form the solder resist layer 9.
【００５８】次に、炭酸ガスレーザー光を用いて、前記
ソルダーレジスト層９に、下層の電極部と導通をとるた
めに、５００μｍの開口部を開口形成した。その開口部
に直径４００μｍのハンダボール１１を搭載した。（図
３（ｇ）参照）次に、図３（ｈ）に示すように、ダイシ
ング装置を用いて、ウエハーの表面から、半導体装置１
を個々に切断分離し、個片化したファンアウト型チップ
サイズパッケージを得た。Next, a carbon dioxide laser beam was used to form an opening of 500 μm in the solder resist layer 9 in order to establish continuity with the lower electrode part. A solder ball 11 having a diameter of 400 μm was mounted in the opening. (See FIG. 3G) Next, as shown in FIG. 3H, the semiconductor device 1 is removed from the surface of the wafer by using a dicing device.
Were individually cut and separated to obtain individual fan-out type chip size packages.
【００５９】＜実施例２＞図４、図５は、本発明の図２
に示すチップサイズパッケージの製造方法の一実施例を
説明する工程図である。<Embodiment 2> FIG. 4 and FIG.
FIG. 6A is a process diagram illustrating an embodiment of the method of manufacturing the chip size package shown in FIG.
【００６０】まず、図４（ａ）に示すように、Ｓｉ材の
ウェハー２上に、Ａｌ材からなる電極パッドを形成した
多数の半導体素子１４が面付け形成された８インチφウ
エハー２を準備した。First, as shown in FIG. 4A, an 8-inch φ wafer 2 in which a large number of semiconductor elements 14 each having an electrode pad made of an Al material are faced and formed on a wafer 2 made of a Si material is prepared. did.
【００６１】次に、図４（ｂ）に示すように、前記ウエ
ハー２の裏面に保護テープ４を貼り合わせた。前記テー
プ４は（株）リンテック製商品名：ダイシングテープ−
Ｄ６７５を使用した。Next, as shown in FIG. 4B, a protective tape 4 was attached to the back surface of the wafer 2. The tape 4 is manufactured by Lintec Co., Ltd. Product name: Dicing tape-
D675 was used.
【００６２】次に、図４（ｂ）に示すように、ダイシン
グ装置を用いて、ウエハーの表面から断裁を行い、半導
体素子１４を個々に切断分離した。このとき、保護テー
プの切断は行わない。Next, as shown in FIG. 4B, a semiconductor device 14 was cut into individual pieces by cutting from the surface of the wafer using a dicing machine. At this time, the protective tape is not cut.
【００６３】次に、ウエハー拡張器を用いて、前記保護
テープ４を均等に拡張し、半導体装置間に隙間を形成し
た。（図４（ｃ）参照）Next, the protective tape 4 was uniformly expanded using a wafer expander to form a gap between the semiconductor devices. (See FIG. 4 (c))
【００６４】次に、図４（ｄ）に示すように、ウエハー
の表面に絶縁樹脂層５を形成した。前記絶縁樹脂層はド
ライフイルムを用いて形成した。前記ドライフイルムは
味の素（株）製の商品名：ＡＢＦ−７０Ｈを使用し、真
空パミネーターにより、９０℃に加熱しながら積層し
た。次に、室温にて冷却した後、前記ドライフイルムの
支持フイルムを剥がし、熱風乾燥炉に入れて、１５０
℃、３０分のポストキュアー加熱を行った。Next, as shown in FIG. 4D, an insulating resin layer 5 was formed on the surface of the wafer. The insulating resin layer was formed using dry film. The dry film was laminated using ABF-70H (trade name, manufactured by Ajinomoto Co., Inc.) with a vacuum laminator while heating at 90 ° C. Next, after cooling at room temperature, the supporting film of the dry film is peeled off, and the dry film is put in a hot-air drying oven for 150 minutes.
Post-cure heating was performed at 30 ° C. for 30 minutes.
【００６５】次に、ウエハーの裏面側より、前記保護テ
ープ４を剥離した。Next, the protective tape 4 was peeled off from the back side of the wafer.
【００６６】次に、ウエハーの裏面側に、絶縁樹脂層５
を形成した。該絶縁樹脂は前記同様に、味の素（株）製
の商品名：ＡＢＦ−７０Ｈを用いて、前記と同じ方法で
形成した。（図４（ｅ）参照）Next, the insulating resin layer 5 is formed on the back surface of the wafer.
Was formed. In the same manner as above, the insulating resin was formed by using ABF-70H (trade name) manufactured by Ajinomoto Co., Inc. in the same manner as described above. (See Fig. 4 (e))
【００６７】次に、図４（ｆ）に示すように、ビーム径
が１５０μｍφの炭酸ガスレーザー光を用いて、前記表
面側絶縁樹脂層５の所定の位置に孔径が１２０μｍφバ
イアホール用孔７の孔設、及び前記半導体素子間の隙間
に絶縁樹脂層を貫通する貫通孔１２の孔説を行った。Next, as shown in FIG. 4 (f), carbon dioxide gas laser beam having a beam diameter of 150 μmφ is used to form a via hole hole 7 having a hole diameter of 120 μmφ at a predetermined position of the surface side insulating resin layer 5. A hole was provided and a through hole 12 was formed to penetrate the insulating resin layer in the gap between the semiconductor elements.
【００６８】バイアホール用孔７、及び貫通孔１２を形
成後、ＫＭｎＯ４：濃度６０ｇ／ｌ、ＮａＯＨ：濃度４
０ｇ／ｌからなるデスミア溶液で、温度８０℃、１０分
間洗浄処理し、バイアホール用孔７、及び貫通孔１２の
内壁に付着した異物、例えばエポキシ樹脂成分等の残さ
を溶解除去した。その後、硫酸ヒドロキシルアミン：２
０ｇ／ｌ、硫酸：５０ｍｌ／ｌからなる中和溶液で、温
度４５℃、５分間の中和処理後、水洗した。After forming the via hole 7 and the through hole 12, KMnO4: concentration 60 g / l, NaOH: concentration 4
A desmear solution consisting of 0 g / l was washed at a temperature of 80 ° C. for 10 minutes to dissolve and remove foreign matters attached to the inner walls of the via hole holes 7 and the through holes 12, such as epoxy resin component residue. Then hydroxylamine sulfate: 2
A neutralization solution consisting of 0 g / l and sulfuric acid: 50 ml / l was neutralized at a temperature of 45 ° C. for 5 minutes and then washed with water.
【００６９】次に、ウエハーの表面、裏面から、パラジ
ウム触媒、アトテック（株）製、商品名：ネオガントを
使用して、ウエハーの両面の絶縁樹脂層からバイアホー
ル用孔７、及びウエハーを貫通する貫通孔１２の内壁か
ら底部まで全表面にパラジウム核（Ｐｂ核）を付着し
た。Next, a palladium catalyst, manufactured by Atotech Co., Ltd., trade name: Neogant is used from the front and back surfaces of the wafer to penetrate the holes 7 for via holes and the wafer from the insulating resin layers on both surfaces of the wafer. Palladium nuclei (Pb nuclei) were attached to the entire surface from the inner wall of the through hole 12 to the bottom.
【００７０】次に、金属銅として、２．３ｇ／ｌ、ＥＤ
ＴＡを２０ｇ／ｌ、ホルマリンを２．５ｇ／ｌを基本組
成とし、水酸化ナトリウムにて、ｐＨ＝１２．５に調整
した無電解銅めっき液ジャパンエナジー（株）製の商品
名、ＫＣ−５００に、空気を吹き込みながら、温度７０
℃、１５分間めっき処理して、ウエハー両面の絶縁樹脂
層からバイアホール用孔７、及びウエハーを貫通する貫
通孔１２の内壁から底部まで全表面に、０．５μｍ厚の
無電解銅めっき層８を形成した。（図４（ｆ）参照）Next, as copper metal, 2.3 g / l, ED
A basic composition of TA 20 g / l and formalin 2.5 g / l, adjusted to pH = 12.5 with sodium hydroxide, the electroless copper plating solution Japan Energy Co., Ltd. trade name, KC-500. While blowing air into the
After the plating process at 15 ° C. for 15 minutes, the electroless copper plating layer 8 having a thickness of 0.5 μm is formed on the entire surface from the insulating resin layer on both surfaces of the wafer to the via hole 7 and the inner wall of the through hole 12 penetrating the wafer to the bottom. Was formed. (See Fig. 4 (f))
【００７１】次に、両面の無電解銅めっき層に、ドライ
フイルムの感光性レジストをラミネートした後、予め準
備したフォトマスクを用いて、感光性レジストへのパタ
ーン露光した後、炭酸ナトリウム溶液を用いて現像処理
した。これにより、所定のパターンとしたレジスト膜２
０μｍのレジストパターン層を形成した。なお、レジス
トパターン層を両面に形成した。Next, after a photosensitive resist of dry film was laminated on the electroless copper plating layers on both sides, the photosensitive resist was pattern-exposed using a photomask prepared in advance, and then a sodium carbonate solution was used. And developed. Thereby, the resist film 2 having a predetermined pattern
A resist pattern layer of 0 μm was formed. A resist pattern layer was formed on both sides.
【００７２】次に、ウエハーを、硫酸１００ｇ／ｌの溶
液に、２５℃、１分間浸漬させた後、ウエハー両面に形
成したレジストパターン層の表面、及び前記無電解銅め
っき層のレジストパターン層からの露出面に電解めっき
を行った。前記電解めっき液は、硫酸銅濃度７０ｇ／
ｌ、硫酸濃度２００ｇ／ｌ、塩酸濃度５０ｍｇ／ｌ、添
加物、奥野製薬（株）製の商品名トップルチナＳＦ濃度
５ｍｇ／ｌからなるめっき液を使用した。電解めっき処
理条件は、２５℃、４０分間、電流密度は、３Ａ／ｄｍ
２の条件で、電解銅めっき処理し、めっき層厚さ１８μ
ｍの電解銅めっき層を形成した。Next, the wafer was immersed in a solution of 100 g / l of sulfuric acid at 25 ° C. for 1 minute, and then, from the surface of the resist pattern layer formed on both surfaces of the wafer and from the resist pattern layer of the electroless copper plating layer. The exposed surface of was electroplated. The electrolytic plating solution has a copper sulfate concentration of 70 g /
1, a sulfuric acid concentration of 200 g / l, a hydrochloric acid concentration of 50 mg / l, an additive, and a plating solution consisting of Okuno Pharmaceutical Co., Ltd. trade name Toprutina SF concentration of 5 mg / l were used. Electrolytic plating conditions are 25 ° C., 40 minutes, current density is 3 A / dm
Under the conditions of 2, electrolytic copper plating treatment, plating layer thickness 18μ
m electrolytic copper plating layer was formed.
【００７３】次に、ウエハーの表面、及び裏面から、前
記レジスト層を剥離除去した。次にウエハー表裏面の全
面をソフトエッチングして、露出した前記無電解銅めっ
き層を除去した。ソフトエッチング液は、９８％溶液の
硫酸４００ｍｌ／ｌ、過酸化水素１００ｍｌ／ｌからな
るソフトエッチング液を使用した。独立した導体回路の
配線パターン１０を形成した。以上の処理により独立し
た導体回路の配線パターン１０を形成した。（図５
（ｈ）参照）Next, the resist layer was peeled off from the front and back surfaces of the wafer. Next, the entire front and back surfaces of the wafer were soft-etched to remove the exposed electroless copper plating layer. The soft etching solution used was a 98% solution of sulfuric acid 400 ml / l and hydrogen peroxide 100 ml / l. The wiring pattern 10 of an independent conductor circuit was formed. By the above process, the wiring pattern 10 of the independent conductor circuit was formed. (Fig. 5
(See (h))
【００７４】次いで、ウエハーの表面、及び裏面から、
市販のＢＴレジンを使用して、ソルダーレジスト層９を
形成した。Then, from the front and back surfaces of the wafer,
The solder resist layer 9 was formed using a commercially available BT resin.
【００７５】次に、炭酸ガスレーザー光を用いて、前記
ウエハーの裏面のソルダーレジスト層９に、下層のパタ
ーンの電極部と導通をとるために、５００μｍの開口部
を開口形成した後、その開口部に直径４００μｍのハン
ダボール１１を搭載した。（図５（ｉ）参照）次に、図
５（ｊ）に示すように、ダイシング装置を用いて、ウエ
ハーの表面から、半導体装置１を個々に切断分離し、個
片化したファンアウト型チップサイズパッケージを得
た。Next, a carbon dioxide laser beam is used to form an opening of 500 μm in the solder resist layer 9 on the back surface of the wafer in order to establish continuity with the electrode portion of the lower pattern, and then the opening is formed. A solder ball 11 having a diameter of 400 μm was mounted on the portion. (See FIG. 5 (i)) Next, as shown in FIG. 5 (j), the dicing device is used to individually cut and separate the semiconductor device 1 from the surface of the wafer to obtain individual fan-out chips. Got the size package.
【００７６】[0076]
【発明の効果】本発明のウエハー一括処理の製造方法に
よれば、ファンアウト型のチップサイズパッケージを制
作することができる。又、本発明の製造方法は半導体素
子のサイズより広い配線エリアが形成できる。そのた
め、従来の製造方法で得られたチップサイズパッケージ
より外部接続端子を設置できる場所が増える。すなわ
ち、本発明の製造方法によれば、外部接続端子数を従来
の半導体装置より増やすことが出来る。According to the method of manufacturing a batch processing of wafers of the present invention, a fan-out type chip size package can be manufactured. Further, the manufacturing method of the present invention can form a wiring area wider than the size of the semiconductor element. Therefore, more places can be provided for the external connection terminals than the chip size package obtained by the conventional manufacturing method. That is, according to the manufacturing method of the present invention, the number of external connection terminals can be increased as compared with the conventional semiconductor device.
【図１】本発明の製造方法で得られたチップサイズパッ
ケージの一例を示す部分側断面図である。FIG. 1 is a partial side sectional view showing an example of a chip size package obtained by a manufacturing method of the present invention.
【図２】本発明の製造方法で得られたチップサイズパッ
ケージの他の例を示す部分側断面図である。FIG. 2 is a partial side sectional view showing another example of the chip size package obtained by the manufacturing method of the present invention.
【図３】（ａ）〜（ｈ）は、本発明の図１に示すチップ
サイズパッケージの製造方法を説明する工程図である。3 (a) to 3 (h) are process diagrams illustrating a method for manufacturing the chip size package shown in FIG. 1 of the present invention.
【図４】（ａ）〜（ｇ）は、本発明の図２に示すチップ
サイズパッケージの製造方法を説明する工程図である。4A to 4G are process diagrams illustrating a method for manufacturing the chip size package shown in FIG. 2 of the present invention.
【図５】（ｈ）〜（ｊ）は、本発明の図２に示すチップ
サイズパッケージの製造方法を説明する工程図である。5 (h) to (j) are process drawings for explaining a method for manufacturing the chip size package shown in FIG. 2 of the present invention.
【図６】従来の製造方法で得られたチップサイズパッケ
ージの一例を示す部分側断面図である。FIG. 6 is a partial side sectional view showing an example of a chip size package obtained by a conventional manufacturing method.
１…半導体装置 ２…ウエハー ３…電極パッド ４…保護テープ ５…絶縁樹脂層 ６…ヒートシンク用の銅板 ７…バイアホール ８…無電解銅めっき層 ９…ソルダーレジスト層 １０…配線パターン １１…外部接続端子 １２…貫通孔 １３…貫通スルホール １４…半導体素子 1 ... Semiconductor device 2 ... Wafer 3 ... Electrode pad 4… Protective tape 5 ... Insulating resin layer 6 ... Copper plate for heat sink 7 ... Via hole 8 ... Electroless copper plating layer 9 ... Solder resist layer 10 ... Wiring pattern 11 ... External connection terminal 12 ... Through hole 13 ... Through hole 14 ... Semiconductor element
Claims (4)
ージの製造方法において、（ａ）多数の半導体素子が形
成されたウエハーの裏面に保護テープを貼り付ける工程
と、（ｂ）前記ウエハーの表面から保護テープの表面ま
で断裁を行い、半導体素子を個々に分離した後、所定の
割合（％）まで、保護テープを拡張する事により、半導
体素子間に所定の隙間を形成する工程と、（ｃ）前記ウ
エハーの表面全面に絶縁性樹脂を塗布し、半導体素子表
面、及び前記半導体素子間の隙間までを覆う絶縁樹脂層
を形成する工程と、（ｄ）前記保護テープを剥離する工
程と、（ｅ）前記絶縁樹脂層に、半導体素子の電極と導
通を取るためのバイアホールを孔設する工程と、（ｆ）
前記絶縁樹脂層全面にバイアホール内壁までを覆う配線
層を形成後、該配線層に所定の配線パターンを形成する
工程と、（ｇ）前記配線パターン、及び前記絶縁樹脂層
を覆うよう全面に配線保護層を形成後、前記配線保護層
に、配線パターンの電極と導通を取るためのホールを孔
設後、外部接続端子を形成する工程と、（ｈ）前記ウエ
ハーから、半導体装置を個々に切断個片化し、チップサ
イズパッケージを得る工程とを有することを特徴とする
チップサイズパッケージの製造方法。1. A method of manufacturing a chip size package for manufacturing a semiconductor device, comprising: (a) attaching a protective tape to the back surface of a wafer having a large number of semiconductor elements formed thereon; and (b) protecting the front surface of the wafer. Cutting the surface of the tape, separating the semiconductor elements into individual pieces, and then expanding the protective tape to a predetermined percentage (%) to form a predetermined gap between the semiconductor elements; A step of applying an insulating resin to the entire surface of the wafer to form an insulating resin layer covering the surface of the semiconductor element and the gap between the semiconductor elements; (d) a step of peeling the protective tape; and (e) Forming a via hole in the insulating resin layer for establishing electrical connection with the electrode of the semiconductor element, and (f)
A step of forming a wiring layer covering the inner wall of the via hole on the entire surface of the insulating resin layer and then forming a predetermined wiring pattern on the wiring layer; and (g) wiring the entire surface so as to cover the wiring pattern and the insulating resin layer. After forming the protective layer, forming a hole in the wiring protective layer for establishing electrical connection with the electrode of the wiring pattern, and then forming an external connection terminal, and (h) individually cutting the semiconductor device from the wafer. And a step of obtaining a chip size package.
表面から、前記絶縁樹脂層全面にバイアホール内壁まで
を覆うよう全面に配線層を形成後、該配線層に所定の配
線パターンを形成する工程が終了した後、（ａ）前記配
線パターン、及び前記絶縁樹脂層を覆うよう全面に絶縁
樹脂層を形成する工程と、（ｂ）前記絶縁樹脂層に、半
導体素子の電極と導通を取るためのバイアホールを孔設
する工程と、（ｃ）前記絶縁樹脂層全面にバイアホール
内壁までを覆う配線層を形成後、該配線層に所定の配線
パターンを形成する工程と、を繰り返し、半導体素子の
上面に、配線パターンを２層以上に多層化する事を特徴
とする請求項１記載のチップサイズパッケージの製造方
法。2. The step (f) according to claim 1, wherein after forming a wiring layer over the entire surface of the insulating resin layer from the surface of the wafer to the inner wall of the via hole, a predetermined wiring pattern is formed on the wiring layer. After the step of forming is completed, (a) a step of forming an insulating resin layer on the entire surface so as to cover the wiring pattern and the insulating resin layer, and (b) the insulating resin layer is electrically connected to the electrode of the semiconductor element. Repeating a step of forming a via hole for taking, and a step of (c) forming a wiring layer covering the inner wall of the via hole on the entire surface of the insulating resin layer and then forming a predetermined wiring pattern on the wiring layer, 2. The method for manufacturing a chip size package according to claim 1, wherein the wiring pattern is formed in two or more layers on the upper surface of the semiconductor element.
ージの製造方法において、（ａ）多数の半導体素子が形
成されたウエハーの裏面に保護テープを貼り付ける工程
と、（ｂ）前記ウエハーの表面から保護テープの表面ま
で断裁を行い、半導体素子を個々に分離した後、所定の
割合（％）まで、保護テープを拡張する事により、半導
体素子間に所定の隙間を形成する工程と、（ｃ）前記ウ
エハーの表面全面に絶縁樹脂を塗布し、半導体素子表
面、及び前記半導体素子間の隙間まで覆う絶縁樹脂層を
形成する工程と、（ｄ）前記保護テープを剥離する工程
と、（ｅ）前記ウエハーの裏面全面に絶縁樹脂層を形成
する工程と、（ｆ）前記ウエハーの裏面側の絶縁樹脂層
に、半導体素子の電極と導通を取るため、前記絶縁樹脂
層にバイアホールを孔設、及び前記半導体装置間の隙間
の絶縁樹脂層部位にウエハー表面から裏面まで貫通する
貫通孔を孔設する工程と、（ｇ）前記ウエハーの表面側
の絶縁樹脂層に、半導体素子の電極と導通を取るための
バイアホールを孔設する工程と、（ｈ）前記ウエハーの
裏面側の絶縁樹脂層全面にバイアホール、及び貫通孔の
内壁までを覆う配線層を形成後、該配線層に所定の配線
パターンを形成する工程と、（ｉ）前記ウエハーの表面
側の絶縁樹脂層全面にバイアホール内壁までを覆う、配
線層を形成後、該配線層に所定の配線パターンを形成す
る工程と、（ｊ）前記ウエハーの表面側に、前記配線パ
ターン、及び前記絶縁樹脂層を覆うよう全面に配線保護
層を形成する工程と、（ｋ）前記ウエハーの裏面側に、
前記配線パターン、及び前記絶縁樹脂層までを覆うよう
全面に配線保護層を形成後、前記配線保護層に、配線パ
ターンの電極と導通を取るためのホールを孔設後、外部
接続端子を形成する工程と、（ｌ）前記ウエハーから、
半導体装置を個々に切断個片化し、チップサイズパッケ
ージを得る工程とを有することを特徴とするチップサイ
ズパッケージの製造方法。3. A method of manufacturing a chip size package for manufacturing a semiconductor device, comprising: (a) attaching a protective tape to a back surface of a wafer having a large number of semiconductor elements formed thereon; and (b) protecting the front surface of the wafer. Cutting the surface of the tape, separating the semiconductor elements into individual pieces, and then expanding the protective tape to a predetermined percentage (%) to form a predetermined gap between the semiconductor elements; A step of applying an insulating resin to the entire surface of the wafer to form an insulating resin layer covering the surface of the semiconductor element and the gap between the semiconductor elements; (d) a step of peeling the protective tape; and (e) a wafer Forming an insulating resin layer on the entire back surface of the wafer, and (f) forming a via hole in the insulating resin layer on the back surface side of the wafer in order to establish continuity with the electrode of the semiconductor element. And (g) forming a through hole penetrating from the front surface of the wafer to the back surface of the insulating resin layer in the gap between the semiconductor devices, and (g) forming an electrode of a semiconductor element on the insulating resin layer on the front surface of the wafer A step of forming a via hole for electrical continuity, and (h) forming a via hole on the entire surface of the insulating resin layer on the back surface side of the wafer and a wiring layer covering the inner wall of the through hole, and then forming a predetermined wiring layer on the wiring layer. And (i) forming a wiring layer on the entire surface of the insulating resin layer on the front surface of the wafer up to the inner wall of the via hole, and then forming a predetermined wiring pattern on the wiring layer. (J) a step of forming a wiring protective layer on the entire surface so as to cover the wiring pattern and the insulating resin layer on the front surface side of the wafer, and (k) a back surface side of the wafer,
After forming a wiring protection layer on the entire surface so as to cover the wiring pattern and the insulating resin layer, after forming a hole in the wiring protection layer for establishing electrical connection with an electrode of the wiring pattern, an external connection terminal is formed. Process, and (l) from the wafer,
And a step of obtaining a chip size package by individually cutting the semiconductor device into individual pieces.
裏面側の前記絶縁樹脂層全面にバイアホール、及び貫通
孔の内壁までを覆う配線層を形成後、該配線層に所定の
配線パターンを形成する工程が、終了後に、（ａ）前記
ウエハーの裏面側全面に、前記配線パターン、及び前記
絶縁層を覆う絶縁樹脂層を形成する工程と、（ｂ）前記
ウエハーの裏面側に、半導体素子の電極と導通を取るた
め、前記絶縁樹脂層にバイアホールを孔設、及び前記半
導体装置間の隙間の絶縁樹脂層部位に貫通孔を孔設する
工程と、（ｃ）前記ウエハーの裏面側全面に前記絶縁樹
脂層からバイアホール、及び貫通孔の内壁までを覆う配
線層を形成後、該配線層に所定の配線パターンを形成す
る工程と、を繰り返し、前記ウエハーの裏面に、配線パ
ターンを２層以上に多層化する事を特徴とする請求項３
記載のチップサイズパッケージの製造方法。4. The step (h) according to claim 3, wherein a via hole and a wiring layer covering up to the inner wall of the through hole are formed on the entire surface of the insulating resin layer on the back surface side of the wafer, and then a predetermined wiring is formed on the wiring layer. After the step of forming a pattern is completed, (a) a step of forming an insulating resin layer covering the wiring pattern and the insulating layer on the entire back surface of the wafer, and (b) a back surface of the wafer, A step of forming a via hole in the insulating resin layer and a through hole in an insulating resin layer portion in a gap between the semiconductor devices in order to establish continuity with an electrode of a semiconductor element; and (c) a back surface of the wafer. After forming a wiring layer covering the insulating resin layer, the via hole, and the inner wall of the through hole on the entire side surface, a step of forming a predetermined wiring pattern on the wiring layer is repeated, and the wiring pattern is formed on the back surface of the wafer. 2 layers or more Claim, characterized in that a multilayer structure 3
A method for manufacturing the described chip size package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002053621A JP3829736B2 (en) | 2002-02-28 | 2002-02-28 | Manufacturing method of chip size package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002053621A JP3829736B2 (en) | 2002-02-28 | 2002-02-28 | Manufacturing method of chip size package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003258157A true JP2003258157A (en) | 2003-09-12 |
| JP3829736B2 JP3829736B2 (en) | 2006-10-04 |
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ID=28665002
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002053621A Expired - Fee Related JP3829736B2 (en) | 2002-02-28 | 2002-02-28 | Manufacturing method of chip size package |
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| Country | Link |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| JP2009283957A (en) * | 2009-07-13 | 2009-12-03 | Sanyo Electric Co Ltd | Method of manufacturing semiconductor device |
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| JP2011513949A (en) * | 2008-02-22 | 2011-04-28 | インテル・コーポレーション | IC package and manufacturing method thereof |
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| JP2001110828A (en) * | 1999-10-13 | 2001-04-20 | Sanyo Electric Co Ltd | Manufacturing method of semiconductor device |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005142248A (en) * | 2003-11-05 | 2005-06-02 | Casio Comput Co Ltd | Semiconductor device and manufacturing method therefor |
| JP4561079B2 (en) * | 2003-11-05 | 2010-10-13 | カシオ計算機株式会社 | Manufacturing method of semiconductor device |
| US7193301B2 (en) | 2003-11-28 | 2007-03-20 | Oki Electric Industry Co., Ltd. | Semiconductor device and manufacturing method thereof |
| JP2011513949A (en) * | 2008-02-22 | 2011-04-28 | インテル・コーポレーション | IC package and manufacturing method thereof |
| WO2010058646A1 (en) * | 2008-11-21 | 2010-05-27 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Semiconductor package and method for manufacturing same |
| JP2009283957A (en) * | 2009-07-13 | 2009-12-03 | Sanyo Electric Co Ltd | Method of manufacturing semiconductor device |
| WO2011090164A1 (en) * | 2010-01-22 | 2011-07-28 | 三洋電機株式会社 | Semiconductor module manufacturing method |
| JP2011151231A (en) * | 2010-01-22 | 2011-08-04 | Sanyo Electric Co Ltd | Method of manufacturing semiconductor module |
| US8592257B2 (en) | 2010-01-22 | 2013-11-26 | Sanyo Electric Co., Ltd. | Method for manufacturing semiconductor modules |
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