JP2000244127A - Wiring board and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board which makes the conduction between a lower conductor layer and an upper conductor layer reliable with a via hole conductive material by forming the via hole in a resin-insulating layer of a wiring board satisfactorily, and a method of manufacturing the board. SOLUTION: A via hole 5 is formed through exposure and development, then the bottom 5A of the via hole is etched with resin, and then the surface of the exposed lower conductor layer 4 is etched (conductor layer etching process) to remove remaining resin 5B and the metal on the surface of the lower conductor layer 4. Also, if the thickness of the lower conductor layer 4 etched at the conductor layer etching process is set at 5 to 30% of the thickness of the lower conductive layer 4, conduction between the lower conductor layer 4 and the upper conductor layer 8 by a via hole conductive material 7 is made super.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board and a method of manufacturing the wiring board, for example, a plurality of wiring conductor layers formed with a resin insulating layer interposed therebetween, and a plurality of wiring layers penetrating the resin insulating layer. The present invention relates to a wiring board having via conductors for conducting conductive layers to each other and a method of manufacturing the same.

[0002]

2. Description of the Related Art Generally, a method of manufacturing a multilayer wiring board 11 in which a resin insulating layer made of, for example, a photosensitive resin is interposed between conductor layers will be described below. First, as shown in FIG. 5A, a resin insulating layer 13 made of a photosensitive resin is formed on a conductor layer 14 formed on the upper surface of a resin insulating layer 12, and then this resin insulating layer 13 is cut in half. Let it cure. Thereafter, using a photomask, the resin insulating layer 13 is exposed to light, and a via hole 15 exposing the upper surface of the conductor layer 14 is formed by development. Thereafter, the upper surface of the resin insulating layer 13 is subjected to electroless copper plating, electrolytic copper plating, or the like, and unnecessary portions are removed by etching, so that the conductor layer 1 having a desired pattern is formed.
8, and a via conductor 17 for conducting between the conductor layer 18 and the conductor layer 14 is formed (see FIG. 5B).

[0003]

However, it is difficult to form a large number of via holes uniformly over the entire surface of the wiring substrate by photolithography such as development.
That is, even if the via hole 15 is formed with high accuracy in a part of the wiring substrate, the developing speed is slow in other parts, the resin to be removed remains at the bottom of the via hole, and the via hole is formed only in the middle of the resin insulating layer. May not be done. Further, in the developing step for forming the via hole 15, the resin once melted by the developing solution may accumulate at the bottom of the via hole 15 during the formation. When the melted resin accumulates at the bottom of the via hole 15, it becomes difficult to supply a new developing solution to the bottom of the via hole 15 being formed, and the development in the depth direction is hindered. As a result, the resin remains at the bottom of the formed via hole 15, and the bottom surface 15A may be formed due to insufficient development. FIG.
As shown in (c), even if the wiring board on which the resin remains is plated as it is, the conductor layer 14 and the conductor layer 18 are not connected by the via conductor 17.

Then, the bottom surface 1 of the via hole 15 is formed.
In order to remove the residual resin constituting 5A, it is possible to etch (dissolve and remove) the residual resin with a resin etching solution such as a potassium permanganate solution, but it is still possible to completely remove the residual resin. Beer hole 1
Resin was sometimes scattered and remained on the bottom 15A of No.5. Further, not only the above-described photolithography technology, but also in the case of drilling a via hole using a laser, a resin residue when a via hole is formed only incompletely due to laser conditions, and a carbide or the like generated during laser processing. Scraps may be scattered at the bottom of the via hole or remain in a film form.

[0005] In order to completely remove the residual resin (resin residue), it is conceivable to enhance the resin etching. However, the resin etching solution also etches the surface of the resin insulating layer and the like. Problems such as the surface of the layer being excessively roughened and the adhesion strength to the upper conductor layer 18 being reduced are caused.

The present invention has been made in view of the above situation, and eliminates resin residue at the bottom of a via hole formed by photolithography or laser technology.
It is a first object of the present invention to provide a wiring board and a method of manufacturing a wiring board which ensure conduction between a lower conductive layer exposed at the bottom of a via hole and an upper conductive layer. A second object of the present invention is to provide a wiring board and a method of manufacturing the wiring board, which can ensure conduction with components.

[0007]

A wiring board for achieving the above object has a conductor layer, a resin insulation layer laminated on the conductor layer, and a via hole penetrating the resin insulation layer. The gist of the present invention is that the conductor layer has a recess at a portion corresponding to the bottom surface of the via hole on the surface thereof.
According to the present invention, since the concave portion is formed in a portion corresponding to the bottom surface of the via hole in the surface of the conductor layer, there is no residue of the resin insulating layer or residue generated during laser processing on the bottom surface of the via hole, for example, Good electrical connection between the via layer and the conductor layer formed in the via hole can be achieved.

The method of forming a via hole is as follows.
The method is not limited to a known photolithography technique including an exposure step and a development step, but may be a technique using a laser. The type of laser may be selected according to the material of the resin insulating layer to be processed. For example, a CO ₂ laser, an excimer laser, a YAG laser, or the like can be suitably used.

Further, it is preferable that the recess is formed by etching the surface of the conductor layer. If you do this,
When removing the vicinity of the surface of the conductor layer by etching, the resin residue adhered to the surface is also removed together,
The conductor layer is completely exposed at the bottom of the via hole, and good connection is possible. In addition, since the connection between the via conductor and the conductor layer formed in the via hole is made in the concave portion, a sufficient adhesion strength between them can be obtained.

[0010] Further, the depth of the recess is preferably 5 to 30% of the thickness of the conductor layer. When the thickness is 5% or more of the thickness of the conductor layer, the etching solution can sufficiently flow under the resin residue at the bottom of the via hole to form a concave portion from which the resin residue is completely removed. Moreover,
Since the concave portion is formed sufficiently deep, the contact portion between the via conductor and the conductor layer is increased, and the adhesion strength can be increased.
On the other hand, when etching is performed until the depth of the concave portion exceeds 30% of the thickness of the conductor layer, the etchant flows under the resin insulating layer and etches the conductor layer, so that it becomes difficult to form a via conductor. It is particularly preferable that the recess is formed substantially coincident with the bottom surface of the via hole.

In the wiring board having the concave portion formed by etching on the surface of the conductor layer as described above, there is no resin residue at the bottom of the via hole, and when the via conductor is formed in the via hole, the via conductor becomes the conductor layer. And the recess can be connected well. When the conductor layer is used directly as a connection terminal, for example, a plating layer such as a nickel plating layer and a gold plating layer may be formed on the surface of the concave portion. Since there is no resin residue on the concave portion, a desired plating layer can be applied to the conductor layer to provide a connection terminal having excellent connection reliability. Further, a solder bump may be formed in the via hole and used as a connection terminal. Since there is no resin residue on the recess, a solder bump (connection terminal) having excellent connection reliability between the conductor layer and the solder bump can be obtained.

In addition, the present invention can provide a wiring board in which the conductor layers are provided on different insulating layers in the wiring board.
The conductor layer provided with the concave portion may be disposed on any one or both sides of the multilayer wiring board. Specifically, the gist is a wiring board including at least two of the following three groups. That is, a first resin layer having a first lower conductor layer, a first recess formed in the first lower conductor layer, a first via hole opened at a position corresponding to the first recess, and a first resin A first upper conductor layer formed on an insulating layer, and a via formed on an inner peripheral surface of the first via hole and on the first recess to conduct between the first lower conductor layer and the first upper conductor layer; A first conductor comprising
A second resin layer having a second conductor layer, a second recess formed in the second conductor layer, a second via hole opening at a position corresponding to the second recess, A second group of solder bumps formed on the recess and protruding from the upper surface of the second resin insulating layer; a third conductor layer; a third recess formed in the third conductor layer; Third having a third via hole opened at a position corresponding to the concave portion
A resin insulating layer, a metal layer formed on the third recess,
A third group consisting of:

The first group can provide a structure in which the first lower conductor layer and the first upper conductor layer can be better connected to each other by the first via conductor interconnecting the first and second upper conductor layers. In addition, the second group can provide a structure that can be connected favorably to an electronic component such as an IC chip and can firmly fix an electronic component such as an IC chip. Further, the third group has a structure in which a metal layer such as a nickel plating layer or a gold plating layer is provided in the third concave portion exposed from the third via hole, and can be used as a connection terminal having excellent connection reliability. Is provided. If not only one of these structures but also a combination of two groups, or even three groups, in a wiring board, a wiring board with even more excellent connection reliability can be obtained.

Next, a method of manufacturing a wiring board when a via hole is formed by a photolithography technique includes a step of forming a resin insulating layer made of a photosensitive resin on a conductive layer, and exposing and developing the resin insulating layer. Performing a via hole forming step of forming a via hole in the resin insulating layer; and etching the resin on the surface of the resin insulating layer and the inner peripheral surface and the bottom surface of the via hole to form a surface of the conductor layer from the bottom surface of the via hole. A resin etching step of exposing a portion of the conductive layer, and a conductive layer etching step of removing a resin adhered to the conductive layer together with the conductive layer by etching the surface of the conductive layer exposed on the bottom surface of the via hole. And

In a method of manufacturing a wiring board when a via hole is formed by a laser, a method of forming a resin insulating layer made of a non-photosensitive thermosetting resin or the like on a conductive layer includes the steps of: Irradiating a laser beam to the via hole forming step of forming a via hole in the resin insulating layer, a resin etching step of etching the resin on the inner peripheral surface and the bottom surface of the surface of the resin insulating layer and the via hole, A conductor layer etching step of removing a residue such as resin or carbide adhered to the conductor layer together with the conductor layer by etching the surface of the conductor layer exposed at the bottom surface of the via hole.

According to the present invention, after the via hole forming step, a resin etching step is performed by photolithography or laser technology to roughen the surface of the resin insulating layer and the inner peripheral surface of the via hole by resin etching. The resin and the like remaining on the bottom surface are removed to some extent. This resin etching exposes at least a part of the surface of the conductor layer. Thereafter, by etching the surface of the conductor layer exposed at the bottom of the via hole, the resin scattered at the bottom of the via hole can be removed together with the conductor layer to which the resin adheres. Therefore, the resin remaining at the bottom of the via hole can be easily removed. According to the wiring board of the present invention, when the conductor layer is a lower conductor layer and the via holes and the resin insulating layer are plated, the conduction with the upper conductor layer can be ensured. Further, when the conductor layer is a bonding pad for directly connecting to a connection terminal of another electronic component, a wiring board, or the like, conduction with the connection terminal of the semiconductor element can be ensured.

Here, the reason for performing the resin etching step is to ensure that a portion of the conductor layer is exposed at the bottom of the via hole by performing this step. If the resin film remains uniformly at the bottom of the via hole, even if a later conductive layer etching step is performed, the etching solution does not reach the conductive layer, so that the resin residue is removed together with the metal on the surface of the conductive layer. This is because they can no longer do it.

Further, in the above-described method for manufacturing a wiring board by photolithography, the development in the via hole forming step is performed while the wiring board is held substantially horizontally, and the upper and lower surfaces of the wiring board are turned upside down during the development. Then, via holes may be formed on both surfaces of the wiring board.

In the case where via holes are simultaneously formed on both sides of the wiring substrate while the wiring substrate is held substantially horizontally as shown in FIG. 2 during the development step, the developing speed of the upper and lower surfaces of the wiring substrate 1 is reduced. There is a difference. That is, on the upper surface side of the wiring board, the developing solution S easily accumulates, and the resin eluted at the bottom of the via hole being formed easily accumulates. When such a resin residue is present, it is difficult to supply a new developing solution to the bottom of the via hole being formed, and the developing speed in the depth direction of the via hole becomes relatively slow. On the other hand, on the lower surface side of the wiring board, the eluted resin (resin residue) and the old developing solution are removed by the new developing solution, so that the new developing solution is always supplied to the bottom of the via hole during the formation. . Therefore, the developing speed in the depth direction of the via hole becomes relatively high.

According to the method of manufacturing a wiring board of the present invention, the upper and lower surfaces of the wiring board are turned upside down during the developing process. Of the developing speed on the upper and lower surfaces can be prevented. Therefore, the amount, thickness, and the like of the resin remaining at the bottom of the via hole are substantially the same on the upper and lower surfaces of the wiring board. Therefore, the resin etching amount and the conductor layer etching amount do not vary between the upper and lower surfaces of the wiring substrate even in the subsequent resin etching step and the conductor layer etching step.

Here, the wiring board may be any as long as it has a resin insulating layer and a conductor layer. For example, a resin insulating layer and a conductor layer may be provided on one or both sides of a core substrate made of a metal substrate or an insulating substrate. A multilayer wiring board in which a plurality of layers are alternately stacked is exemplified.

After the conductor layer etching step, if the etching is performed until a concave portion is formed in a portion of the surface of the conductor layer corresponding to the via hole, the removal of the resin remaining at the bottom of the via hole becomes more reliable. The surface of the concave portion is preferably a surface with fine irregularities, but according to the present invention, the portion where the conductor layer was first exposed becomes a fine concave portion as the etching proceeds, while the residual resin adheres first. The portion which has been etched is slowly etched to become a fine convex portion, and fine concave and convex portions can be easily formed on the concave portion surface. If there are such fine concave portions, via conductors, solder bumps,
The adhesion strength with a plating layer or the like can be improved.

Further, the method for manufacturing a wiring board according to the present invention comprises:
In the conductor layer etching step, 5-30% of the thickness of the conductor layer with respect to the surface of the conductor layer exposed at the bottom of the via hole.
May be removed by etching. If the etching amount of the conductor layer is less than 5% of the thickness of the conductor layer, it may be insufficient to etch the conductor layer 4 to which the resin 5B has adhered (see FIG. 4B). That is, the adhered resin 5
The vicinity of the surface 4A of the conductor layer 4 exposed from B is eluted by etching, but may be insufficient to elute the conductor layer 4 hidden under the resin 5B.

When the conductor layer is etched more than 30% of the thickness, the resin at the bottom of the via can be completely removed.
The etchant runs under the resin insulating layer (see FIG. 4C). When a via conductor is to be formed in the via hole 5 by plating in a later step, the plating solution does not easily flow around the eaves portion 5c formed at this time, and a good via conductor is not formed. There is a possibility that the connection with the layer becomes defective.

As a method of disposing the photosensitive resin on the substrate surface, a method of applying the photosensitive resin by screen printing or spin coating, or a method of attaching a photosensitive film made of the photosensitive resin can be adopted. Further, as the type of the conductive layer, a conductive layer made of a conductive metal such as copper, nickel, gold, and silver can be used, and therefore, the electroless plating layer or the electrolytic plating layer is formed of a metal used for these wirings. It is composed of In addition, as a method for forming the conductor layer, a known subtractive method or an additive method can be adopted.

In the method for manufacturing a wiring board according to the present invention, the surface of the conductive layer is etched with a roughening solution containing a cupric complex and an organic acid before the step of forming the resin insulating layer. And roughening the surface.
As a method of roughening the surface of the conductor layer, a method of performing acicular plating or blackening treatment is known. However, according to these methods, a different material (alloy) such as an acicular plating layer or a blackening treatment layer is used. Etc.) are formed. However, according to the present invention,
Since the surface of the conductor layer is roughened by dissolving the grain boundaries of the metal, it does not generate a layer of dissimilar material,
The subsequent conductor layer etching step can be favorably performed.

When performing the electroless plating,
As the pretreatment, a method of attaching growth nuclei (Pd, Au, etc.) of electroless plating to a place where an electroless plating layer is to be formed can be adopted.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an example (example) of a first embodiment of a method of manufacturing a wiring board according to the present invention will be described with reference to FIGS.
This will be described sequentially with reference to FIG. First, a copper plating is formed on the upper surface of the resin insulating layer 2 by a known semi-additive method, and the surface thereof is further reduced to 0.1 to 10 μm by using a roughening etching solution containing a cupric complex and an organic acid.
A photosensitive layer containing an epoxy resin previously formed in a film shape as a main component and a silica filler on a 17 μm-thick conductor layer 4 which has been surface-treated (roughened) so as to have a maximum roughness (Rmax) of m. Paste resin sheet, resin insulation layer 3
Is formed (see FIG. 1A).

As the surface treatment of the conductor layer 4, known techniques such as needle plating and blackening can be used instead. However, these techniques involve dissimilar material (alloy) layers interposed at the interface. This may be an obstacle to the subsequent conductor layer etching step. On the other hand, in the case of the roughening etching according to the present embodiment, since the dissimilar material (alloy) layer does not intervene and merely dissolves the grain boundary of the metal of the conductor layer and roughens the conductor layer, The conductor layer etching step becomes easy.

Next, the resin insulating layer 3 is semi-cured by heating at 80 ° C. for 15 minutes, and then exposed using a photomask (not shown).
A photocurable layer is formed on a predetermined portion of the surface of the substrate. Thereafter, a heat treatment is further performed at 80 ° C. for 45 minutes, and the resin insulating layer 3 is semi-cured to a hardness that can withstand the subsequent development step. Thereafter, a via hole 5 is formed by development. At this time, a part of the resin insulating layer 3 remains in the form of a film at the bottom 5A of the via hole 5 to form a so-called incomplete via hole (see FIG. 1B).

This developing step is performed in a state where the wiring board 1 is held horizontally as shown in FIG. This is because the via holes are formed in the vertical direction (depth direction) with respect to the surface of the wiring board by holding the substrate horizontally. However, when held in such a horizontal direction, the developing speed varies between the upper surface and the lower surface of the wiring substrate 1, and thus the upper and lower surfaces of the wiring substrate 1 are reversed during the developing process. By inverting the upper and lower surfaces, it is possible to eliminate the variation in the developing speed between the upper and lower surfaces of the wiring board 1. Therefore,
The thickness of the resin remaining at the bottom 5A of the via hole 5 can be made substantially equal between the upper and lower surfaces.

After development, as shown in FIG. 1B, an undercut portion 3 is formed at the upper end of the via hole 5.
Since A is formed, the undercut portion 3A is cut off by water jet (high-pressure water washing) (FIG. 1 (c)).
reference). Note that this water jet treatment also has an effect of partially removing resin residues such as dissolved matter accumulated at the bottom of the via hole.

Next, the resin on the surface of the resin insulating layer 3 and the inner peripheral surface of the via hole 5 is etched using a potassium permanganate solution. By this resin etching step, the resin remaining at the bottom 5A of the via hole 5 is etched, and a part of the upper surface 4A of the conductor layer 4 is exposed. However, even after the resin etching step, the residual resin 5B is still scattered on the upper surface 4A of the conductor layer 4 (see FIG. 3A).

Next, the surface of the conductor layer 4 is etched by about 1.5 μm using a sodium sulfate solution to remove the residual resin 5B together with the metal (copper) on the surface of the conductor layer 4 (conductor layer etching step). In this manner, a via bottom 5C in which the conductor layer 4 is completely exposed is formed at the bottom of the via hole 5. In the via bottom 5C, a recess 6A having a thickness smaller than the thickness of the conductor layer 4 is formed in the conductor layer 4 (FIG. 3B).

After that, the upper surface of the resin insulating layer 3 is subjected to electroless copper plating, electrolytic copper plating or the like to form the conductor layer 8. At the same time, as shown in FIG. 3C, the conductor layer 4 (recess 6A)
Conductor layer 8 and conductor layer 4 on the upper surface of
Is formed (first group).

Here, the conductor layer etching step will be described with reference to FIG. In the conductor layer etching step of the above embodiment, the exposed surface was etched by about 1.5 μm which is about 9% of the thickness of the conductor layer 4 with respect to the thickness of the conductor layer 4 of 17 μm. In this case, as shown in FIG.
The exposed surface 4A of the conductor layer 4 is etched, and the surface of the conductor layer 4 below the residual resin 5B (shown by a broken line) is also etched, so that the residual resin 5B is removed.

Although FIG. 3B shows a simplified diagram, it is more preferable that fine concaves and convexes are formed on the surface of the concave portion 6A in the conductor layer etching step as described below. That is, since etching is delayed in a portion where the residual resin 5B is adhered, a fine convex portion is formed. On the other hand, in a portion where the conductor layer 4 is exposed without the residual resin 5B, the etching proceeds rapidly, so that a fine concave portion is formed. As a result, fine irregularities are formed on the surface of the recess 6A. Due to such fine unevenness, good adhesion strength to a via conductor, a solder bump, a plating layer, and the like formed thereon can be obtained.

On the other hand, when etching is performed for a thickness of less than 5% (for example, 0.5 μm: about 2.9%) of the thickness of the conductor layer 4, the exposed surface 4A of the conductor layer 4 is etched. However, the surface of the conductor layer 4 below the residual resin 5B could not be etched, and as a result, the residual resin 5B could not be removed (see FIG. 4B).

When the conductive layer 4 is etched to a thickness exceeding 30% (for example, 7 μm: about 41%), the residual resin 5B can be completely removed, but the surface of the conductive layer 4 is not covered with the resin outside the via hole. Etching is performed to the lower side of the insulating layer 3 to form a large eaves portion (overhang portion) 5c (see FIG. 4C). When the eaves portion 5c is large, when the via conductor 7 is formed in the via hole 5 by plating in a later step, the plating solution is difficult to flow around, and the conduction between the via conductor 7 and the conductor layer 4 becomes poor. I will. In order to prevent such poor conduction, the maximum length of the eaves portion 5c should be 5 μm or less, more preferably 3 μm.
m or less, more preferably 2 μm or less. That is, it is preferable that the diameter of the via hole 5 and the diameter of the recess 6 </ b> A substantially match each other.

On the other hand, when the conductor layer 4 is etched by a thickness of 30% or less, more preferably 25% or less, conduction failure may occur even if an eaves portion is slightly formed. No problem. That is, the depth of the recess formed by the conductor layer etching step is preferably 5 to 30%, more preferably 5 to 25% of the thickness of the (lower) conductor layer.

Next, an embodiment (a second embodiment) that is partially different from the above-described method for manufacturing a wiring board according to the first embodiment will be described with reference to FIGS. Note that parts common to the first embodiment will be omitted or simplified. First, FIG. 6 is a partially enlarged cross-sectional view of a wiring board 20 having a substantially rectangular shape in a plan view and a substantially plate shape. The wiring board 20 includes resin insulating layers 26a, 36a, 40a on the upper surface of the core substrate 21 in the figure and resin insulating layers 26b, 36b, 40b on the lower surface, and the resin insulating layers 40a, 40b, which are the outermost layers, are It also has functions. In addition, a conductor layer 24 is provided between the insulating layers.
a, 34a, 44a, 24b, 34b, 44b are formed.

Each conductor layer is made of a resin insulating layer 26a, 3
6a, 40a, 26b, 36b, and 40b, and are connected via via conductors 29 and 39 that penetrate through core substrate 21 and through-hole conductors 23 and 30 that penetrate core substrate 21. The through-hole conductor 30 is coaxially arranged inside the through-hole conductor 23 while being insulated from the through-hole conductor 23.

Each via conductor is formed by filling a plating metal in a via hole penetrating the resin insulating layer, and is connected by a concave portion provided in each lower conductive layer. Since there is no resin residue between the via conductor and the lower conductor layer, the connection reliability between them is extremely high. In this regard, of the wiring board 20 shown in FIG.
7A and 7B show enlarged portions surrounded by broken lines 20p and 20q, respectively. First, as shown in FIG. 7A, concave portions 24e and 34e are formed on the respective surfaces of the conductor layers 24a and 34a.
Resin insulating layers having via holes opening at positions corresponding to e and 34e are laminated. Via conductors 29, 39
Are formed in the via holes and are connected to the conductor layers 24e, 24e by the concave portions 24a, 34a (first group). The via conductors 29 and 39 are each filled with a plating metal, the via conductor 39 is formed right above the via conductor 29, and the solder bump 41 is further connected to the via conductor 39.
It is formed right above.

Similarly, as shown in FIG. 7A, the solder bump 41 formed on the upper surface side of the wiring board 20 has a concave portion 44e (depth depth) formed in the conductor layer 44a (thickness 17 μm) thereunder. (1.7 μm), and is formed in a via hole opened at a position corresponding to (1.7 μm), and is fixed to the concave portion 44e (second group). There is no resin residue between the solder bump 41 and the conductor layer 44a, and both are well connected.

Further, as shown in FIG. 7 (b), the wiring board 20 has an LGA pad 42 formed on the lower surface thereof by forming a plating layer 45 on the surface of a concave portion 44e provided in the conductor layer 44b. ing. A concave portion 44e is formed in the resin insulating layer 40b.
A via hole 43b is formed at a position corresponding to the LGA pad 42, and the LGA pad 42 is exposed from the via hole 43b (third group). The LGA pad 42 is mainly used as an external connection terminal for connecting the wiring board 20 to another wiring board. The plating layer 45
Consists of two layers, nickel plating and gold plating. As described above, in the wiring board 20, in addition to the via conductors inside the wiring board, the solder bumps and the LGA pads on the surface are respectively connected to the recesses of the lower conductive layer, so that good connection reliability over the entire wiring board is obtained. can get.

Next, a method of manufacturing the wiring board 20 will be described with reference to FIGS. First, a double-sided copper-clad board in which copper foils are stuck on both sides of a core board 21 made of a bismaleimide-triazine resin having a thickness of 800 μm is prepared, and a through hole 22 is formed by drilling.
Electroless and electrolytic copper plating is performed on the copper foil on the inner peripheral surface and both surfaces of the through hole 22, and the outer through hole conductor 23 is formed.
Is formed (see FIG. 8A). The surface of the plating layer 24 was coated with a roughened etching solution containing a cupric complex and an organic acid by a commercially available etching apparatus (CZ processing apparatus manufactured by MEC Corporation) to form a surface of 0.1 to 10 μm.
Surface treatment is performed so as to have a maximum roughness (Rmax) of μm.

Next, a resin paste is printed and filled in the through-hole 22 in which the through-hole conductor 23 is formed, the resin paste is cured, and the upper and lower surfaces thereof are flattened by polishing to form an outer resin-filled body 25. I do. Thereafter, an etching resist having a predetermined pattern is formed, unnecessary portions of the plating layer 24 are removed by etching, and conductor layers 24a and 24b are formed on the front side and the back side, respectively (FIG. 8).
(B)). The surfaces of the conductor layers 24a and 24b are subjected to a surface treatment so as to have a maximum roughness (Rmax) of 0.1 to 10 μm by using a roughening etching solution containing a cupric complex and an organic acid.

Next, a photosensitive resin in the form of a film is pasted on each of the front side and the back side of the core substrate 21, and the resin insulating layers 26a and 26b are heat-treated at 80 ° C. for 15 minutes to be semi-cured. The semi-cured resin insulating layers 26a and 26b are exposed using a photomask (not shown). After the exposure, a heat treatment is further performed at 80 ° C. for 45 minutes, so that the resin insulating layer 26 has a hardness enough to withstand the subsequent development process.
a, 26b are semi-cured. Next, a via hole 28 is formed by simultaneously spraying a developing solution from above and below while the wiring board is held horizontally (developing step). In addition,
The wiring board is turned upside down during the developing process in order to prevent the development speed from being varied vertically. Via hole 28
A portion of the resin insulating layers 26a and 26b remains in the form of a film at the bottom of the substrate, which is a so-called incomplete via hole.

After forming the via hole 28 by development,
A through hole 27 is formed by irradiating a laser. The through hole 7 is bored substantially along the central axis of the through hole 2, and the outer resin filler 5 remains on the inner peripheral surface of the through hole conductor 3 with a substantially uniform thickness. Next, after the upper and lower surfaces of the wiring board are washed by water jet (high-pressure washing), the surfaces of the resin insulating layers 26a and 26b and the inner peripheral surfaces of the via holes are resin-etched using a potassium permanganate solution. By this resin etching process,
The resin remaining at the bottom of the via hole 28 is etched, and a part of the upper surface of the lower conductor layers 24a and 24b is exposed. If the lower conductive layers 24a and 24b were originally exposed, the exposed area of the lower conductive layers 24a and 24b can be increased by a resin etching process. However, even after the resin etching step, the conductor layer 24
Residual resin is scattered on the upper surfaces of a and 24b.

Next, the surfaces of the conductor layers 24a and 24b exposed at the bottom of the via hole 28 are etched using a sodium sulfate solution to remove the residual resin together with the metal (copper) on the surfaces of the conductor layers 24a and 24b ( Conductor layer etching step). Thus, the conductor layers 24a and 24b are completely exposed at the bottom of the via hole 28, and the recess 24e is formed.
Is formed (see FIG. 8C). The depth of the recess 24e is about 1.7 μm, which is about 10% of the thickness 17 μm of the conductor layers 24a and 24b.

Further, after the conductor layer etching step, if the via holes are washed with high-pressure pure water using a water jet device, the conductor layers 24a and 24b can be more completely exposed from the bottom surface of the via holes 28. . Further, when an eaves portion (overhang portion) as shown in FIG. 4 (c) is caused by the etching liquid flowing under the resin insulating layer, high-pressure pure water is sprayed on the eaves portion. When it is cut off, occurrence of conduction failure can be reduced.

Next, the inner peripheral surface of the through hole 27, the upper surfaces of the resin insulating layers 26a and 26b, and the inside of the via hole 28 are subjected to electroless and electrolytic copper plating to form a plating layer including the through hole conductor 30 and the via conductor 29. 31 are formed. The via conductor 29 is formed by filling the via hole 28 with a plating metal (see FIG. 9A). The conditions of the plating solution used in the plating layer forming step are as follows: a Cu concentration of 18 g / l, and H ₂ SO ₄ 180 g /
l, Cl ^- ion 48 mg / l, leveler (inhibitor)
0.3 mg / l and a current density of 1 A / dm ² . In addition,
In this embodiment, only one through hole 27 is shown, but a large number of through holes 27 and via holes 28 are formed.

A printing mask 3 made of stainless steel having a plurality of openings 32 h for filling holes corresponding to the through holes 7.
2 (thickness: 100 μm) is prepared. Then, FIG. 9 (b)
As shown in the figure, in the resin filling step, a print mask 32 is placed on a wiring board, and a resin paste 33
p is printed, and the through holes 27 are filled and filled. The resin paste 33p was prepared by adding an inorganic filler (copper or silica) and an imidazole-based curing agent to a bisphenol-type epoxy resin, kneading the mixture, and adjusting the viscosity at 22 to 23 ° C. to be 500 Pa · S or more. Use something.

After the resin filling step, when the metal mask 32 is peeled off, the resin paste 33p is filled in the through holes 27 so that a part thereof protrudes from the surface of the plating layer 31. Next, in the resin curing step, the wiring board is
The resin paste 33p is semi-cured by heating at 20 ° C. for 20 minutes. At the time of this heating, the resin paste 33p temporarily fluidizes and tends to spread and spread along the surface of the wiring board. However, in the present embodiment, since the via hole 28 is previously filled with the via conductor 29, the resin paste 33p does not flow into the via hole 8 and does not cause the shortage of the resin paste 33p in the through hole.
Also, the resin paste 33p flowing into the via hole 28
Does not cause defects such as cracks.

After the resin paste 33p has been semi-cured, the front and back surfaces of the wiring board are polished using a belt sander (rough polishing), and then buff-polished (finished polishing) to be flattened. Next, the semi-cured resin paste 33p is
It is cured by heating at 50 ° C. for 20 minutes.
Is formed, and the curing process of the resin paste is completed (FIG. 10).
(See (a)).

Next, electroless and electrolytic copper plating is performed on the front and back surfaces of the wiring board to form a plating layer 34 (see FIG. 10B). After that, unnecessary portions of the plating layers 31 and 34 are removed by etching. At this time, a lid conductor layer 35 is formed on the resin filler 33, and a part of the plating layers 31 and 34 is also left above the via conductors 29, so that the conductor layers 34a and 34
b is formed (see FIG. 11A). By forming the lid conductor layer 35, the via conductor 39p can be formed on the axis of the resin filler 33 in a later step. Note that the lid conductor layer 3
5 and the surfaces of the conductor layers 34a and 34b are made to have a maximum roughness (Rmax) of 0.1 to 10 [mu] m by using a roughening etching solution containing a cupric complex and an organic acid.
It is preferable to perform a surface treatment so that

Thereafter, resin insulating layers 36a and 36b are further formed on the front and back surfaces. Since the via hole 28 is filled with a via conductor 29 and the through hole 27 is filled with a resin filler 33 and covered with a cover conductor layer 35, the resin insulating layers 36a and 36b have almost no undulation on the surface. It can be formed flat. Therefore,
The via hole forming step in the subsequent step can be performed with high positional accuracy.

Next, a via hole 38 is formed by exposure and development in the same manner as the via hole 28. Next, after the above-described resin etching step and conductor layer etching step, a plating layer including the via conductor 39 is formed by electroless and electrolytic copper plating. Next, an unnecessary portion of the plating layer is removed by etching to form the via conductor 39 including the via conductors 39v and 39p, and the conductor layer 44. In the conductor layer etching step, the conductor layers 34a, 3a
4b and the surface of the lid conductor layer 35 are etched to form concave portions 34e and 35e corresponding to the via holes (see FIG. 11B).

Here, the via conductor 39v is formed immediately above the via conductor 29 in the lower layer, and is connected to the conductor layers 34a and 34b by a concave portion 34e on the surface thereof. Also, via conductor 39
p is formed on the axis of the through-hole conductor 30 and is connected to the lid conductor layer 35 by a concave portion 35e on the surface thereof. With the structure in which the via conductors 39p and the through-hole conductors 30 are arranged on a straight line in the thickness direction of the wiring board, it is possible to further increase the wiring density.

Next, after forming solder resist layers 40a and 40b on the front and back surfaces, respectively,
Via holes 43a and 43b are formed by development. Thereafter, the above-described resin etching step and conductor layer etching step are performed to remove resin residues at the bottoms of the via holes 43a and 43b. In this conductive layer etching step, a concave portion 44e is formed on the surface of the conductive layer 44 corresponding to the via holes 43a and 43b.

Next, the conductor layer 44 exposed from the via holes 43a and 43b is plated with nickel and gold. Thereafter, solder paste is printed and reflowed in the via holes 43a of the solder resist 40a on the front surface to form the solder bumps 41, thereby completing the manufacture of the wiring board 20 (see FIGS. 6 and 7).

The solder bumps 41 are used, for example, for flip-chip connection with an IC chip (not shown) mounted on the wiring board 20. The conductor layer exposed from the via hole 43b of the solder resist layer 40b on the back side is used as an LGA pad 42 as it is as a terminal for connection to another printed wiring board (not shown). The LGA pad 42 has, for example,
If the solder balls and pins are fixed, the wiring board
GA (ball grid array) or PGA (pin grid array) can be used. LGA pad 4
No. 2 obtains a very good connection reliability because the resin etching step and the conductor layer etching step are performed in advance to form a concave portion 44e having no resin residue, and then the plating layer 45 is formed (see FIG. 7B). Can be.

Further, in the wiring board 20, one of the (inner) through-hole conductor 30 and the outer through-hole conductor 23 having the coaxial structure is set to a power supply potential, for example.
When the other is set to the ground potential, the inductance can be reduced and the electrical characteristics can be improved. Also (inside)
When the through-hole conductor 30 is used as a signal wiring and the outer through-hole conductor 23 is used as a ground potential, noise between the signal wirings can be reduced.

In the first and second embodiments,
Although the example in which the via hole is formed by the photolithography technique has been described, the via hole may be formed by the laser technique. Embodiment of the present invention using laser technology (third embodiment)
Will be described with reference to FIGS. First, a conductor layer 54 is formed on the upper surface of the resin insulating layer 52 by a known semi-additive method by copper plating.
The surface of the conductor layer 54 is 0.1 to 10 μm using a roughened etching solution containing a cupric complex and an organic acid.
Surface treatment (roughening) so that the maximum roughness (Rmax) is obtained
Keep it. A thermosetting resin sheet mainly composed of an epoxy resin previously formed in a film shape is pasted on the conductor layer 54 to form a resin insulating layer 53 (see FIG. 12A).

Next, after heating and curing the resin insulating layer 53 under a predetermined condition, the resin insulating layer 53 is irradiated with a CO ₂ laser through a mask having a predetermined pattern to form a via hole 55. A resin residue 55v such as a scum such as a resin melt or a carbide by a laser adheres or remains around the opening, the inner peripheral surface, and the bottom surface of the via hole 55 (see FIG. 12B). Subsequently, the resin residue on the surface of the resin insulating layer 53 and the inner peripheral surface and the bottom surface of the via hole 55 is etched using a potassium permanganate solution. By this resin etching step, the surface of the resin insulating layer 53 is chemically etched.
Is removed together with the resin insulation layer 53. However, even after the resin etching step, the resin residue 55v may remain on the conductor layer 54 in some cases, as shown in FIG.

Next, the exposed surface of the conductor layer 54 is etched by about 1.7 μm using a sodium sulfate solution to remove the resin residue 55v together with the metal (copper) on the surface of the conductor layer 54 (conductor layer etching step). . Thus, at the bottom of the via hole 55, the conductor layer 54 is completely exposed, and a concave portion 56 is formed (FIG. 13A).

Thereafter, the upper surface of the resin insulating layer 53 and the inside of the via hole 55 are subjected to electroless copper plating, electrolytic copper plating and the like, and then unnecessary portions are removed by etching, and as shown in FIG. In addition, a via conductor 57 that conducts between the conductor layer 58 and the conductor layer 54 is formed. Next, a resin insulating layer 59 is formed, and a via hole 60 is formed by a CO ₂ laser similarly to the via hole 55. Thereafter, the above-described resin etching step and conductor layer etching step are performed to form a recess 61 at a position corresponding to the via hole 61. Further, the conductor layer 62 and the via conductor 63 connecting the conductor layer 62 and the conductor layer 58 are formed by a known method (see FIG. 13C).

According to the present embodiment, after the via holes 55 and 60 are formed by the laser, the resin residue adhered to the surface thereof is removed together with the resin insulating layer by the resin etching step, and further, together with the conductor layer by the conductor layer etching step. The resin residue attached to the surface is removed. Therefore, resin residues such as scum generated during laser processing can be completely removed, and furthermore, the connection between the via conductor 57 and the conductor layer 54 and the connection between the via conductor 63 and the conductor layer 58 can be favorably performed.

The above-described first to third embodiments are merely examples of the embodiments of the present invention, and can be appropriately modified and applied without departing from the gist of the present invention. In addition, conventionally known wiring board manufacturing techniques and the like can be appropriately applied. For example, although the description is omitted in the above embodiment, the surfaces of the conductor layer (such as a wiring layer and a through-hole conductor) and the resin insulating layer (including a resin filler) are appropriately roughened by a desired chemical treatment or the like. Further, the adhesion strength between the adjacent conductor layer and another conductor layer or the resin insulating layer can be increased.

[0070]

As described above in detail, in the present invention, after forming a via hole by development or laser light, a resin etching step and a conductor layer etching step are performed, so that no resin remains at the bottom of the via hole. Conduction between the conductor layer and the via conductor can be reliably performed.

Further, since the etching amount (thickness) in the conductor layer etching step is set to 5 to 30% of the thickness of the (lower) conductor layer, the remaining resin can be surely removed, and the conduction between the conductor layer and the via hole can be further improved. Does not impair.

Further, since the developing step is performed while the wiring board is held horizontally, and the upper and lower surfaces of the wiring board are inverted during the developing step, it is possible to eliminate development variations on the upper and lower surfaces of the wiring board. it can. Therefore, in the subsequent resin etching step or conductor layer etching step, there is no variation in the effect on the upper and lower surfaces of the wiring board, and good conduction between the conductor layer and the via conductor is provided on both the upper and lower surfaces of the wiring board. Obtainable.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram illustrating a method for manufacturing a wiring board according to an embodiment.

FIG. 2 is an explanatory view showing a developing step in a state where the wiring board is held horizontally.

FIG. 3 is an explanatory view illustrating a method of manufacturing a wiring board according to an example.

FIG. 4 is an explanatory view showing a state after a conductor layer etching step.

FIG. 5 is an explanatory view showing a conventional method for manufacturing a wiring board.

FIG. 6 is a partially enlarged cross-sectional view of a wiring board according to a second embodiment of the present invention.

FIG. 7 is a partially enlarged cross-sectional view showing a further enlarged part of the wiring board shown in FIG. 6;

FIG. 8 is a partially enlarged cross-sectional view illustrating a process of manufacturing a wiring board up to a via hole forming process according to a second embodiment of the present invention.

FIG. 9 is a partially enlarged cross-sectional view illustrating a step subsequent to FIG. 7 and explaining a through-hole filling step in the order of steps, according to the second embodiment of the present invention. .

FIG. 10 is a partially enlarged cross-sectional view illustrating a step subsequent to FIG. 8 in the manufacturing steps of the wiring board and illustrating a step up to a step of forming a cover conductor layer according to the second embodiment of the present invention.

FIG. 11 is a partially enlarged cross-sectional view illustrating a step subsequent to FIG. 9 and illustrating a stacking step in the order of steps, according to the second embodiment of the present invention.

FIG. 12 is a partially enlarged cross-sectional view illustrating a process of manufacturing a wiring substrate using a laser in the order of steps according to the third embodiment of the present invention.

FIG. 13 is a partially enlarged cross-sectional view illustrating, in the order of steps, steps subsequent to the step illustrated in FIG. 12 among the steps of manufacturing a wiring board using a laser according to the third embodiment of the present invention.

[Explanation of symbols]

 1, 20: Wiring board 2, 3, 26a, 36a, 40a: Resin insulating layer 4, 8, 24a, 34a, 44a: Conductive layer 5, 28: Via hole 5B: Resin resin 7, 29, 39: Via conductor 23 : Outer through-hole conductor 27: Through-hole 30: (Inner) through-hole conductor 33: Resin filler 33p: Resin paste 35: Lid conductor layer

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Naoki Kito 14-18 Takatsuji-cho, Mizuho-ku, Nagoya-shi, Aichi Japan Inside Nihon Special Ceramics Co., Ltd. (72) Inventor Satoshi Hirano 14th Takatsuji-cho, Mizuho-ku, Aichi Prefecture No. 18 Japan Special Ceramics Co., Ltd.

Claims (12)

[Claims] 1. A conductive layer, comprising: a resin insulating layer laminated on the conductive layer; and a via hole penetrating the resin insulating layer, wherein the conductive layer corresponds to a bottom surface of the via hole on a surface thereof. A wiring board comprising a concave portion in a portion. 2. The wiring board according to claim 1, wherein the recess is formed by etching a surface of the conductor layer. 3. The wiring board according to claim 1, wherein the depth of the recess is 5 to 30% of the thickness of the conductor layer. 4. The wiring board according to claim 1, wherein a via conductor is formed in the via hole, and the via conductor is connected to the conductor layer at the concave portion. 5. The wiring board according to claim 1, wherein a plating layer is formed on a surface of the concave portion. 6. The wiring board according to claim 1, wherein a solder bump is formed in the via hole. 7. A wiring board comprising at least two of the following three groups: a first lower conductive layer;
A first recess having a first recess formed in the first lower conductor layer and a first via hole opening at a position corresponding to the first recess;
A resin insulating layer; a first upper conductor layer formed on the first resin insulating layer; an inner peripheral surface of the first via hole;
A first group consisting of a via conductor formed on the concave portion and electrically connecting the first lower conductor layer and the first upper conductor layer; a second conductor layer; and a second conductor layer formed on the second conductor layer. A second recess,
A second resin insulating layer having a second via hole opening at a position corresponding to the second recess, formed on the second recess,
Solder bumps projecting from the upper surface of the second resin insulating layer;
A second group consisting of: a third conductor layer; a third recess formed in the third conductor layer;
A third group including a third resin insulating layer having a third via hole opened at a position corresponding to the third recess, and a metal layer formed on the third recess. 8. A step of forming a resin insulating layer made of a photosensitive resin on the conductive layer, and a step of forming a via hole in the resin insulating layer by exposing and developing the resin insulating layer. And a resin etching step of etching the resin on the surface of the resin insulating layer and the inner peripheral surface and the bottom surface of the via hole; and a conductor layer etching step of etching the surface of the conductor layer exposed on the bottom surface of the via hole. A method for manufacturing a wiring board, comprising: 9. The development in the via-hole forming step is performed with the wiring substrate held substantially horizontally, and the upper and lower surfaces of the wiring substrate are turned upside down during the development to form via holes on both surfaces of the wiring substrate. The method for manufacturing a wiring board according to claim 8, wherein: 10. A step of forming a resin insulating layer on a conductor layer, and irradiating the resin insulating layer with laser light.
A via hole forming step of forming a via hole in the resin insulating layer; a resin etching step of etching a resin on a surface of the resin insulating layer and an inner peripheral surface and a bottom surface of the via hole; a surface of the conductor layer exposed on a bottom surface of the via hole And a conductor layer etching step of etching a wiring board. 11. The conductive layer etching step according to claim 8, wherein 5 to 30% of the thickness of the conductive layer is removed by etching from the surface of the conductive layer exposed at the bottom of the via hole. A method for manufacturing the wiring board according to any one of the above. 12. The method according to claim 1, further comprising, before the step of forming the resin insulating layer, a step of etching the surface of the conductor layer with a roughening liquid containing a cupric complex and an organic acid to roughen the surface. The method for manufacturing a wiring board according to claim 8, wherein: