JP2002305269A - Multilayer interconnection board and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer interconnection board, having connection reliability and a minute-diameter via hole, and to provide a method for manufacturing the multilayer interconnection board. SOLUTION: In the multilayer interconnection board where insulating and conductor wiring layers are laminated mutually, projections 2a and 2b are formed. At the projections 2a and 2b, a periphery section of a lower pad 1 in the via hole 6 for connecting the upper and lower conductor wiring layers is higher than a pad surface.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board having a multilayer structure in which insulating layers and conductor wiring layers are alternately stacked, and a method of manufacturing the same. The present invention relates to a multilayer wiring board in which a via hole is formed by plating and a method for manufacturing the same.

[0002]

2. Description of the Related Art Recently, semiconductor large-scale integrated circuits (LSIs)
In semiconductor devices such as, the degree of integration of transistors increases,
The operation speed reaches 1 GHz in clock frequency, and the number of input / output terminals exceeds 1000.

In order to mount a semiconductor element on a printed wiring board, an interposer such as a BGA (Ball Grid Array) or a CSP (Chip Size Package) has been developed and is now widely used. FIG. 8 shows an example in which a semiconductor element is mounted on an interposer having a BGA structure and mounted on a printed wiring board.

A bump 63 is formed of gold or the like on one surface of a multilayer wiring board 67 in which insulating layers and conductor wiring layers are alternately laminated based on a copper-clad board or a ceramic board 67a in which glass cloth is impregnated with an epoxy resin or the like. And the electrodes of the semiconductor element 61 are electrically connected. A pad 64 surface-treated with gold or the like is formed on the opposite surface, and is connected to a conductor wiring layer 65 of a printed wiring board 71 via a solder ball 66.

[0005] Such a multilayer wiring board is formed by sequentially stacking an insulating resin layer and a conductive wiring layer on a copper-clad board or a ceramic substrate. The insulating layer of the multilayer wiring board manufactured by this method can be formed by applying a resin such as polyimide so as to be thinned. Further, the conductor wiring layer can be formed by plating, and fine wiring can be performed. On the other hand, the via hole connecting the upper and lower conductor wiring layers can be formed by forming a hole by laser processing or the like and filling the inside with plating. For this reason, it is possible to achieve higher wiring density, thinner, and smaller in size as compared with a conventional multilayer printed wiring board in which copper-clad substrates are collectively laminated, or a ceramic multilayer wiring board in which green sheets are laminated and fired collectively. .

In addition to this multi-layering method, there has been proposed a configuration in which a polyimide film with a copper foil is bonded to a conventional multilayer printed wiring board which is to be collectively laminated with an adhesive. Also in this configuration, fine wiring can be formed due to the thinness of the copper foil, and similarly, high wiring density, thinning, and miniaturization can be achieved.

As the processing speed in a semiconductor device increases,
There is an increasing demand for higher speed transmission of signals transmitted through the interposer. At the same time, the number of input / output terminals of the semiconductor element also tends to increase, and the connection method with the interposer becomes completely compatible with wire bonding, and flip-chip connection in a grid arrangement is required. As a result, it is difficult to route the wiring from the connection terminal in the interposer with a single layer, and it is necessary to divide the wiring into at least two layers. In addition, in order to cope with high-speed signals, a microstrip structure, a strip structure, or a coplanar structure of wiring may be required, and the structure of the interposer is becoming more and more multilayered.

[0008] However, from the viewpoint of the manufacture of the interposer, an increase in the number of layers significantly reduces the manufacturing yield. For this reason, it is important how to design the wiring efficiently and reduce the number of layers. One of means for forming an efficient wiring is to reduce the land diameter of a via hole. As a result, in consideration of manufacturing accuracy, it is necessary to reduce the diameter of the via hole itself.

In recent years, the introduction of laser processing machines using excimer lasers and YAG third and fourth harmonics has become popular, and it has become easy to form micro-diameter holes.

As a method of forming a via hole, a hole is formed by a laser or the like, a lower pad surface is exposed, and a seed layer for electroplating is formed by electroless copper plating or the like, and the seed layer is used as an electrode to form a via hole. A constant thickness of plating is formed on the side and bottom of the substrate. In recent years, attention has been paid to filled via plating in which the inside of a hole is filled with a plating metal in order to pass a high-speed signal or to increase a degree of freedom of wiring by forming a via hole right above the via hole.

However, a small via diameter inevitably reduces the contact area with the lower pad, thereby significantly lowering the connection reliability.

[0012]

SUMMARY OF THE INVENTION The present invention has been made in view of the problems of the prior art, and has as its object to provide a multilayer wiring board having a small diameter via hole with connection reliability and a method of manufacturing the same. I do.

[0013]

According to the present invention, in order to achieve the above object, according to the first aspect of the present invention, there is provided a multilayer wiring board comprising an insulating layer and a conductive wiring layer which are alternately laminated. And forming a projection in which the periphery of the lower pad of the via hole connecting the via holes is higher than the pad surface.

According to a second aspect of the present invention, the insulating layer comprises a first insulating layer on the lower pad and a second insulating layer thereon, and the dissolving rate of the second insulating layer with respect to the oxidizing agent is high. 2. The multilayer wiring board according to claim 1, wherein the first insulating layer is larger than the first insulating layer.

According to a third aspect of the present invention, there is provided the multilayer wiring board according to the first or second aspect, wherein the height of the lower pad projection is about the thickness of the first insulating layer. .

According to a fourth aspect of the present invention, the material constituting the first insulating layer is an adhesive.
To the multilayer wiring board according to any one of the first to third aspects.

According to a fifth aspect of the present invention, there is provided the multilayer wiring board according to the first aspect, wherein the protrusion is made of metal.

According to a sixth aspect of the present invention, in the multi-layer wiring board according to the first aspect, the protrusion is made of a resin material having a lower dissolution rate of the oxidizing agent than the first insulating layer. It is.

According to a seventh aspect of the present invention, a step of forming a projection on a lower pad on an insulating layer, a step of forming a second insulating layer on the first pad via a first insulating layer, Forming a hole for forming a via hole with a laser beam, expanding the hole diameter of the first insulating layer using an oxidizing agent, and forming a plating metal inside the hole and on the surface of the second insulating layer. Forming a conductor wiring layer on the second insulating layer.

The invention according to claim 8 is the method of manufacturing a multilayer wiring board according to claim 7, wherein the peripheral portion of the lower pad is left, and the conductor layer in the other portion is half-etched. It is.

According to a ninth aspect of the present invention, there is provided the method for manufacturing a multilayer wiring board according to the seventh aspect, wherein the protrusion is formed by plating around the lower pad.

According to a tenth aspect of the present invention, an insulating material layer whose dissolution rate with respect to an oxidizing agent is smaller than that of the first insulating material is formed on the lower pad, and portions other than the peripheral portion of the lower pad are removed by laser processing. The method according to claim 7, wherein the protruding portion is formed.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A multilayer wiring board according to the present invention will be described with reference to a view near a via hole. FIG. 7 is a sectional view of a conventional multilayer wiring board. The lower pad 51 and the upper pad 56 on the single-layer or multi-layer insulating substrate 52 are electrically connected by a via hole 55.

In forming the via hole 55, first, a hole for forming a via hole is formed by a laser from the surface of the insulating layer 54 on the lower pad. Hole processing is stopped on the lower pad due to the difference in processing speed between the resin and the metal in the laser. Examples of the type of laser include a carbon dioxide laser, a YAG (basic wave, a second harmonic, a third harmonic, and a fourth harmonic) laser, an excimer laser, and the like. YAG third harmonic, fourth harmonic, and excimer laser, which are wavelength lasers, are preferred.

A seed layer for copper electroplating is formed by electroless plating on the inside of the hole and on the surface of the insulating layer 54, including the surface of the lower pad made of copper or the like exposed by the laser processing. Fill the inside with plated metal. Finally, the upper conductive layer 57 and the upper pad 56 are formed by photo-etching the conductive layer on the surface.

As the diameter of the via hole decreases, the contact area with the lower pad 51 decreases, and the connection reliability decreases.

Therefore, as shown in FIGS. 1A and 1B, in the present invention, the connection portion with the lower pad is widened,
The connection reliability is improved.

In order to widen the connection portion with the lower pad, first, a first insulating layer 4 having a high dissolution rate with respect to an oxidizing agent is formed on the lower pad 1 as a layer structure of the insulating layer.
A second insulating layer 5 having a low dissolution rate is laminated thereon.

Further, as the shape of the lower pad 1, a projection 2 is formed on the periphery. FIG. 2 shows a top view of the lower pad formed on the insulating substrate. As shown in FIG. 1A, the protruding portion 2 can be dissolved in the metal protruding portion 2a by the same material as the second insulating layer or by the same oxidizing agent as the second insulating layer, as shown in FIG. 1B. The resin protrusion 2b having a speed may be used.

As shown in FIG. 3D, after a hole 16 for forming a via hole is formed by a laser, the first insulating layer 14 is dissolved by an oxidizing agent. At this time, the protrusion 12
Thereby, the dissolution of the first insulating layer 14 can be suppressed only on the lower pad 11. When the protrusion 12 does not exist,
Since it is very difficult to control the amount of dissolution, the dissolution portion spreads over the area of the lower pad, and the plating connection cannot be established. For this reason, it is necessary that the height of the protrusion 12 is about the thickness of the first insulating layer 14.

The oxidizing agent treatment is preferably a permanganate treatment used for pretreatment of electroless plating. As the conditions, it is preferable to carry out the reaction at a temperature of from room temperature to 80 ° C. with 30 to 80 g / l of potassium permanganate and a 20 to 60 g / l aqueous solution of sodium hydroxide.

As the second insulating layer, any material which is hardly soluble in an oxidizing agent and which is generally used as an insulating layer may be used, and examples thereof include polyimide, polybenzimidazole, polyetherimide, and polyphenylene ether. . These materials hardly dissolve in the permanganate treatment solution. On the other hand, the first insulating layer only needs to be dissolved in an oxidizing agent to some extent and used as the insulating layer. For example, epoxy resin, modified polyimide resin,
Nylon epoxy resin and the like can be mentioned. The first insulating layer may be an adhesive for bonding the substrate and the second insulating layer.

An embodiment will be described below.

<First Embodiment of Manufacturing Method of Protrusion>
FIG. 4A shows a first embodiment of a method of manufacturing a projection.
The description will be made according to the flow of (d).

A copper layer 32 (18 μm thick) formed on the insulating substrate 31 shown in FIG. 4A is coated with PMER (manufactured by Tokyo Ohka Kogyo Co., Ltd.)
It dried at 30 degreeC and 30 minutes (FIG.4 (b)). The film thickness after drying was 6 μm.

As shown in FIG. 4C, exposure and development are performed through a photomask having a predetermined pattern, and a photoresist pattern 34 is formed. At this time, 18μ
When etching a copper layer of m thickness, the center of the lower pad,
In addition, a photoresist pattern 34b such as a halftone dot is formed on the conductor wiring portion so as to be half-etched.

As shown in FIG. 4D, at 50 ° C. and 40 °
The exposed portion of copper is dissolved and removed with a ferric chloride solution of Be to form a projection 3
7a was formed. The thickness of the central portion 35 of the lower pad 36 and the thickness of the conductor wiring 38 were approximately 8 μm.

<Second Embodiment of Manufacturing Method of Protrusion>
The second embodiment of the method of manufacturing the protrusion is shown in FIG.
The description will be made according to the flow of (h).

A copper layer 32 (9 μm thick) formed on the insulating substrate 31 shown in FIG. 5A is coated with PMER (manufactured by Tokyo Ohka Kogyo Co., Ltd.)
It dried at 30 degreeC and 30 minutes (FIG.5 (b)). The film thickness after drying was 6 μm.

As shown in FIG. 5C, exposure and development are performed through a photomask having a predetermined pattern to form a photoresist pattern 34.

As shown in FIG. 5D, at 50 ° C. and 40 °
The exposed copper portion was dissolved and removed with a ferric chloride solution of Be.

As shown in FIG. 5E, the photoresist 34 is removed and the lower pad 36 and the conductor wiring 38 are removed.
Was formed.

As shown in FIG. 5F, EPPR (manufactured by Tokyo Ohka Kogyo Co., Ltd.) was further coated as a photoresist 39 and dried at 80 ° C. for 30 minutes.

As shown in FIG. 5G, exposure and development were performed through a photomask having a predetermined pattern, and an opening was provided in a portion corresponding to the projection. Further, a palladium treatment was performed, and electroless copper plating was performed to form a metal portion corresponding to the protrusion at 5 μm.

As shown in FIG. 5H, the photoresist pattern 40 was removed to form a projection 37a.

<Third Embodiment of Manufacturing Method of Protrusion>
The third embodiment of the method of manufacturing the protrusion is shown in FIG.
The description will be made according to the flow of (g).

A PMER (manufactured by Tokyo Ohka Kogyo) is coated as a photoresist 33 on a copper layer 32 (9 μm thick) formed on an insulating substrate 31 shown in FIG.
It dried at 30 degreeC and 30 minutes (FIG. 6 (b)). The film thickness after drying was 6 μm.

As shown in FIG. 6C, exposure and development are performed through a photomask having a predetermined pattern to form a photoresist pattern 34.

As shown in FIG. 6D, at 50 ° C. and 40 °
The exposed copper portion was dissolved and removed with a ferric chloride solution of Be.

As shown in FIG. 6E, the photoresist 34 is removed and the lower pad 36 and the conductor wiring 38 are removed.
Was formed.

As shown in FIG. 6 (f), a polyimide resin solution (UPI-FINE manufactured by Ube Industries, Ltd.) was applied by screen printing, and 100 ° C./30 minutes, 180 ° C./10 minutes, and 3 ° C.
The imidation was performed at 50 ° C./30 minutes. The film thickness after imidization was 8 μm on the lower pad.

As shown in FIG. 6 (g), only the protrusion 37b was left on the polyimide film by KrF excimer laser, and the other portions were removed. Also, the polyimide opening may be formed only by the KrF excimer laser in the center of the lower pad connected to the via hole, instead of leaving the polyimide resin only in the protrusion. In this case, the polyimide film formed between the insulating substrate and the first insulating layer also serves as an insulating layer.

<Embodiment of Method for Manufacturing Multilayer Wiring Board>
An embodiment of a method for manufacturing a multilayer wiring board will be described in accordance with the flow of FIGS. 3A to 3I, focusing on the periphery of a small-diameter via hole.

As shown in FIG. 3A, the protrusion 12 (having a height of about 1
An epoxy adhesive is coated on a 50 μm thick polyimide tape 13 (UPILEX manufactured by Ube Industries, Ltd.) having a lower pad 11 (9 μm thick) on which a 4 μm) is formed, and then dried at 100 ° C. for 5 minutes. The first insulating layer 14 was formed. At this time, the thickness was about 15 μm from the surface of the base polyimide. Further, the second insulating layer 15
Is laminated at 130 ° C. with a 25 μm thick polyimide tape (UPILEX manufactured by Ube Industries, Ltd.)
Then, it was cured at 180 ° C./1 hour (FIG. 2)
(B)). The thickness of the first insulating layer after curing was substantially the same as the height of the projection 12, and was about 14 μm.

As shown in FIG. 3C, a hole 16 for forming a via hole having a diameter of 20 μm was formed by the fourth harmonic light of the YAG laser. At this time, no resin residue was observed on the copper surface of the lower pad 11.

As shown in FIG. 3D, as the oxidizing agent,
Potassium permanganate heated to 50 ° C. (50 g /
l), using an aqueous solution of sodium hydroxide (20 g / l),
The first insulating layer on the central portion of the lower pad 11 was dissolved to form the void 17.

As shown in FIG. 3E, a thin-film conductor layer 18 was formed inside the hole 16, the gap 17 and the surface of the second insulating layer by electroless copper plating.

As shown in FIG. 3 (f), the inside 19 of the hole was filled with a plating metal by electrolytic copper plating, and a copper plating layer was formed on the surface of the substrate. At this time, the copper thickness on the substrate surface was 9 μm. The composition of the electroless copper plating solution or the electrolytic copper plating solution is not particularly limited, and an appropriate composition can be used according to the plating metal characteristics and the deposition rate.

As shown in FIG. 3 (g), the plating layer on the substrate surface is exposed to the upper pad 21 by a standard photo etching process.
And the conductor wiring layers 20 and 22 were formed.

As shown in FIG. 3 (h), the conductor wiring layer 20 formed earlier was used as a lower pad of the next layer, and a projection 23 was similarly formed on the periphery thereof.

As shown in FIG. 3 (i), by repeating the steps of FIGS. 3 (b) to 3 (g) again, the upper first insulating layer 28, second insulating layer 27, upper pad 24,
The conductor wiring layer 25 and the via hole 26 with high connection reliability were formed, and a multilayer wiring board was formed. Further, by repeating the same steps, it is also possible to manufacture a multi-layered multilayer wiring board.

In this embodiment, a polyimide film is bonded as the second insulating layer.
A polyimide film with a copper foil attached to the surface layer may be attached. In order to form a projection by half etching, it is preferable to use a thick copper foil, and it is more effective to combine the copper foil and the plating than to make a predetermined thickness by plating. In this case, the hole processing by the laser can be performed by changing the processing frequency, thereby performing the hole processing of the upper copper foil and the insulating layer, and stopping at the lower pad.

[0063]

According to the present invention, there is an effect that a contact area at the bottom of a micro-diameter via hole is widened and connection reliability can be obtained even with a micro-diameter. In addition, a protrusion can be formed by utilizing a difference in dissolution rate of the first insulating layer and the second insulating layer with respect to an oxidizing agent.

[0064]

[Brief description of the drawings]

FIG. 1 is a sectional view showing a multilayer wiring board of the present invention.

FIG. 2 is a top view showing a multilayer wiring board of the present invention.

FIG. 3 is a cross-sectional view illustrating a method for manufacturing a multilayer wiring board according to the present invention.

FIG. 4 is a cross-sectional view illustrating a method of manufacturing a projection used in the multilayer wiring board of the present invention.

FIG. 5 is a cross-sectional view illustrating a method of manufacturing a projection used in the multilayer wiring board of the present invention.

FIG. 6 is a cross-sectional view illustrating a method of manufacturing a projection used in the multilayer wiring board of the present invention.

FIG. 7 is a sectional view showing a conventional multilayer wiring board.

FIG. 8 is a cross-sectional view showing an embodiment in which a semiconductor element is mounted on a conventional multilayer wiring board and mounted on a printed wiring board.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Lower pad 2 ... Protrusion part 2a ... Metal protrusion part 2b ... Resin protrusion part 3 ... Insulating board 4 ... First insulating layer 5 ... Second insulating layer 6 ... Via hole 7 ... Upper pad 8 ... Conductor wiring 11 ... Lower part Pad 12 ... Protrusion 13 ... Insulating substrate 14 ... First insulating layer 15 ... Second insulating layer 16 ... Hole 17 ... Void 18 ... Thin film conductor layer 19 ... Via hole 20 ... Conductor wiring 21 ... Upper pad 22 ... Conductor wiring Reference Signs List 23 Projection portion 24 Upper pad 25 Conductor wiring 26 Via hole 27 Second insulating layer 28 First insulating layer 31 Insulating substrate 32 Copper layer 33 Photoresist 34 Photoresist pattern 34a Photoresist Pattern 34b photoresist halftone pattern 35 half-etched portion 36 lower pad 37 projecting portion 37a metal projecting portion 37b resin projecting portion 38 conductive Wiring 39 Photoresist 40 Photoresist pattern 41 Plating metal 42 Resin layer 51 Lower pad 52 Insulating substrate 53 First insulating layer 54 Second insulating layer 55 Via hole 56 Upper pad 57 Conductor Wiring 61 ... Semiconductor element 62 ... Pad 63 ... Bump 64 ... Pad 65 ... Conductor wiring layer 66 ... Solder ball 67a ... Base board 67b ... Multilayer wiring layer 68 ... Via hole 69 ... Lower conductor wiring layer 70 ... Through hole 71 ... Printed wiring board

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Atsushi Sasaki, Inventor 1-5-1, Taito, Taito-ku, Tokyo Letterpress Printing Co., Ltd. (72) Inventor Masataka Maehara 1-1-1, Taito, Taito-ku, Tokyo Letterpress Inside Printing Co., Ltd. (72) Inventor Koji Ichikawa Inside 1-5-1, Taito, Taito-ku, Tokyo Toppan Printing Co., Ltd.

Claims (10)

[Claims] 1. A multilayer wiring board comprising insulating layers and conductive wiring layers alternately laminated, wherein a projection is formed in which a peripheral portion of a lower pad of a via hole connecting upper and lower conductive wiring layers is higher than a pad surface. Characteristic multilayer wiring board. 2. The insulating layer according to claim 1, wherein said insulating layer comprises a first insulating layer on a lower pad and a second insulating layer thereon, wherein a dissolution rate with respect to an oxidant is higher than that of the second insulating layer. 2. The multilayer wiring board according to claim 1, wherein the width is larger. 3. The multilayer wiring board according to claim 1, wherein the height of the lower pad projection is about the thickness of the first insulating layer. 4. The multilayer wiring board according to claim 1, wherein a material forming the first insulating layer is an adhesive. 5. The multilayer wiring board according to claim 1, wherein said projection is made of metal. 6. The multilayer wiring board according to claim 1, wherein said protrusions are made of a resin material having a lower dissolution rate of an oxidizing agent than the first insulating layer. 7. A step of forming a projection on a lower pad on an insulating layer, a step of forming a second insulating layer on the lower pad via a first insulating layer, and Forming a hole for forming a via hole;
Increasing the diameter of the hole in the insulating layer, forming a plated metal inside the hole and on the surface of the second insulating layer, and forming a conductive wiring layer on the second insulating layer. Production method 8. The method for manufacturing a multilayer wiring board according to claim 7, wherein the peripheral portion of the lower pad is left, and the other portion of the conductor layer is half-etched. 9. A method for manufacturing a multilayer wiring board according to claim 7, wherein a projection is formed by plating around the lower pad. 10. An insulating material layer having a lower dissolution rate with respect to an oxidizing agent than the first insulating material is formed on the lower pad,
8. The method for manufacturing a multilayer wiring board according to claim 7, wherein a portion other than a peripheral portion of the lower pad is removed by laser processing to form a projection.