JP4980295B2 - Wiring substrate manufacturing method and semiconductor device manufacturing method - Google Patents

Description

  The present invention relates to a wiring board formed on a support substrate, a manufacturing method thereof, a semiconductor device in which a semiconductor chip is mounted on the wiring board, and a manufacturing method thereof.

In recent years, with the increase in the speed and integration of semiconductor devices, the density and thickness of semiconductor chips have been increased, and the wiring substrate to which the semiconductor chips are connected is similarly required to have a higher density and thickness. ing.

  In order to cope with such high density and thinning of wiring on the wiring board, in recent years, a method of forming a wiring board by a so-called build-up method has become mainstream. When forming a multilayer wiring board by the build-up method, it is formed as follows.

  First, a buildup layer made of an insulating resin layer is formed on a support substrate (core substrate) having appropriate rigidity, a via hole is formed in the buildup layer, a via plug is then formed in the via hole by a plating method, and A pattern wiring connected to the via plug is formed. Hereinafter, by repeating these steps, a multilayer wiring board by a build-up method can be formed.

Since the build-up layer (insulating resin layer) is made of a soft material such as a thermosetting epoxy resin, for example, the build-up layer has a suitable support in order to maintain the flatness of the build-up layer. The method of forming on a board | substrate was taken.
JP 2002-198462 A

  However, since there has been a demand for further reducing the thickness of the wiring board formed by using the build-up method, a wiring board having a structure in which the supporting substrate is removed, that is, a so-called coreless structure has been proposed.

  However, when the wiring board has a coreless structure, the rigidity of the wiring board is reduced. Therefore, there has been a problem that it becomes difficult to provide a process of removing a support substrate or laminating a necessary layer on a wiring substrate after the wiring substrate is peeled off from the supporting substrate and applying a process. An example of such a process will be described below.

  For example, the build-up layer has high water absorption, and there may be a concern about long-term insulation reliability when the surface is exposed, and the surface is preferably covered with a protective layer such as a solder resist layer. However, in the conventional build-up method, when forming a solder resist layer covering the surface of the build-up layer formed immediately above the support substrate, the support substrate is removed or the build-up layer is peeled off from the support substrate. There was a need.

  In this case, it is necessary to transport the wiring substrate in the middle of processing, in which the support substrate is removed and the rigidity is reduced, and there is a problem that the concern of damaging the wiring substrate is increased. In addition, when the solder resist layer is formed on the build-up layer after removing the support substrate, the flatness of the wiring substrate may be a problem because of insufficient rigidity.

  Therefore, it may be difficult to maintain good processing accuracy of the solder resist layer. Such a problem of processing accuracy of the solder resist layer becomes prominent particularly when a wiring substrate corresponding to a recent high-performance semiconductor chip with high density and high integration is formed.

  In view of this, the present invention has a general object to provide a novel and useful method of forming a wiring board that solves the above-described problems.

  A specific problem of the present invention is a wiring board that can be thinned and can handle high-density wiring, a manufacturing method thereof, a semiconductor device in which a semiconductor chip is mounted on the wiring board, and a manufacturing method thereof. Is to provide.

  According to an aspect of the present invention, a first step of forming a first solder resist layer having a first opening on a support substrate, and a portion of the support substrate exposed in the first opening. A second step of forming a first electrode; an insulating layer is formed on the first electrode and the first solder resist layer; and the insulating layer is connected to the first electrode. A third step of forming a wiring portion, a fourth step of forming a second solder resist layer having a second opening in the wiring portion, and one surface of the insulating layer is the first step The support substrate is covered with the first solder resist layer having an opening, and the other surface of the insulating layer is covered with the second solder resist layer having the second opening. And a fifth step of removing the wiring board. A method is provided.

  According to the present invention, it is possible to provide a wiring board that can be thinned and can handle high-density wiring, a manufacturing method thereof, a semiconductor device in which a semiconductor chip is mounted on the wiring board, and a manufacturing method thereof. Can do.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Example 1
FIG. 1A to FIG. 1E are diagrams showing a procedure of a method of manufacturing a wiring board according to a first embodiment of the present invention.

  First, in the step shown in FIG. 1A, a solder resist layer 102 made of a photosensitive resin material is formed on a support substrate 101 made of a conductive material such as Cu, for example, by a screen printing method. In this case, the solder resist layer 102 can be formed, for example, by laminating or applying a film-like resist material.

  Next, the solder resist layer 102 is irradiated with ultraviolet rays through a mask pattern (not shown) and exposed to pattern, thereby forming an opening 102A. The support substrate 101 is exposed from the opening 102A.

  Next, in the step shown in FIG. 1B, an electrode 103 made of, for example, Au / Ni is formed on the support substrate 101 by electroplating using the support substrate 101 as a conductive path so as to be embedded in the opening 102A. To do. The electrode made of Au / Ni means an electrode formed by laminating an Au layer and a Ni layer, which is formed so that Au is on the surface side (connection surface) when the wiring board is completed. (same as below). In this case, it is possible to form the electrode 103 by electrolytic plating when the support substrate 101 is made of a conductive material, and it is more preferable that the support substrate 101 is made of a low-resistance conductive material such as Cu.

  Next, in the step shown in FIG. 1C, an insulating layer (build-up layer) 104 made of, for example, a thermosetting epoxy resin is formed on the solder resist layer 102 and the electrode 103. Next, via holes are formed in the insulating layer 104 by, for example, a laser.

  Next, a via plug 105 is formed in the via hole, and a pattern wiring 106 connected to the via plug 105 is formed on the insulating layer 104 by, for example, a semi-additive method. In this case, it is preferable to form the via plug 105 and the pattern wiring 106 by electrolytic plating after forming a seed layer on the insulating layer 104 by electroless plating. In this way, a wiring portion including the via plug 105 and the pattern wiring 106 is formed.

  Next, in a step shown in FIG. 1D, a solder resist layer 107 is formed on the insulating layer 104 so as to cover the pattern wiring 106 by, for example, a screen printing method. Next, the solder resist layer 107 is patterned by being irradiated with ultraviolet rays through a mask pattern (not shown) and exposed to form an opening 107A. A part of the pattern wiring 106 is exposed from the opening 107A.

  Next, in the step shown in FIG. 1E, the support substrate 101 is removed by wet etching, for example, to form the wiring substrate 100.

  In the wiring substrate 100, the electrode 103 is on the side connected to an external connection device such as a mother board (so-called land side), and the pattern wiring 106 exposed from the opening 107A is, for example, a semiconductor chip. Connected. In this case, for example, a solder ball may be formed on the electrode 103. The pattern wiring 106 exposed from the opening 107A may be formed with, for example, an electrode made of Au / Ni, a solder ball, a reflow solder layer, or the like.

  This embodiment is characterized in that the solder resist layer 102 is formed on the support substrate 101 prior to the formation of the insulating layer 104. For this reason, it is possible to form a wiring board by a build-up method having a coreless structure in which both sides of the wiring board are covered with a solder resist layer.

  In this case, both sides of the insulating layer 104 can be protected by a solder resist layer, and the difference in stress applied to both sides of the insulating layer 104 is reduced, thereby producing an effect of suppressing warping of the wiring board.

  Further, in the case of this embodiment, the opening 107A is formed in a state where the solder resist layer 107 is supported by the support substrate 101. Therefore, when the opening 107A is formed, the plane of the solder resist layer 107 is formed. The degree is good. Therefore, the processing accuracy of the opening 107A is improved, and the opening 107A can be formed with a fine shape and a fine pitch.

  In recent years, semiconductor chips have been highly integrated and have high density wiring, and the connecting portion between the semiconductor chip and the wiring substrate has also been narrowed in pitch and high density wiring. The processing accuracy of the shape is required. According to the method of manufacturing a wiring board according to the present embodiment, it is possible to form a wiring board corresponding to these demands and corresponding to narrow pitch and high density wiring.

  Further, in the method for manufacturing the wiring board according to the present embodiment, the so-called coreless structure is realized by removing the support substrate while corresponding to the high-density wiring described above, and the wiring board is thinned.

  Further, in the wiring board according to the present embodiment, the electrode 103 is on an external device connection side (so-called land side) such as a mother board. Therefore, the area (opening diameter) of the opening 102A is larger than the area (opening diameter) of the opening 107A. For example, the opening diameter of the opening 107A to which the semiconductor chip is connected is about 80 μm to 100 μm, and the opening diameter of the opening 102A connected to a motherboard or the like is about 0.5 mm to 1 mm, which is large. There is a difference.

  For example, when a laser is used to form a large opening, there is a problem that takes time. In this embodiment, the patterning of the opening 102A is performed by light exposure, and the opening can be formed more quickly than in the case of a laser.

  Further, before the solder resist layer 107 is formed, a wiring substrate having a multilayer wiring structure can be formed by repeatedly performing the process shown in FIG. 1C.

  For example, as a material constituting the solder resist layers 102 and 107, an epoxy acrylic resin, an epoxy resin, and an acrylic resin can be used. Further, the patterning method of the solder resist layers 102 and 107 is not limited to the exposure / development method described above. For example, a solder resist layer in which openings are formed (patterned) may be formed by screen printing. In this case, it is possible to use materials other than the photosensitive material for the solder resist layer.

  In this embodiment, the thickness of the electrode 103 and the solder resist layer 102 is substantially the same. However, the present invention is not limited to this, and the electrode 103 can be variously used as necessary as described below. 103 can be modified or changed.

(Example 2)
2A to 2F are diagrams illustrating a method of manufacturing a wiring board according to a second embodiment of the present invention, following the procedure. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted. Further, portions not particularly described can be formed by the same method as in the first embodiment.

  First, the process shown in FIG. 2A is the same as the process shown in FIG. 1A, and the solder resist layer 102 is formed on the support substrate 101, and the opening 102 A is formed in the solder resist layer 102.

  Next, in the step shown in FIG. 2B, the support substrate 101 exposed from the opening 102A is etched to form a recess 101A.

  Next, in the step shown in FIG. 2C, similarly to the step shown in FIG. 1B of Example 1, the recess 101A and the opening of the support substrate 101 are formed by electrolytic plating using the support substrate 101 as a conductive path. An electrode 103A made of, for example, Au / Ni is formed so as to be embedded in a part of 102A. In this case, the electrode 103A can be formed by electroplating when the support substrate 101 is made of a conductive material, and more preferably, the support substrate 101 is made of a low-resistance conductive material such as Cu.

  2D to 2F, the insulating layer 104, the via plug 105, the pattern wiring 106, and the solder resist layer 107 are the same as the steps shown in FIGS. 1C to 1E of the first embodiment. The opening 107A is formed, and the support substrate 101 is removed to form the wiring substrate 100A. In the case of this example, a wiring board can be formed in the same manner as in Example 1 except that the electrode 103A is formed in the recess 101A, and the same effect as in Example 1 can be obtained.

  In the wiring board 100 </ b> A according to the present embodiment, the electrode 103 </ b> A has a structure protruding from the solder resist layer 102. For this reason, for example, when the connection part of the electrode 103A and the mother board is connected by a solder ball, the contact area between the solder ball and the electrode 103A is increased, so that the electrical connection reliability is improved.

Example 3
FIGS. 3A to 3F are diagrams illustrating the method of manufacturing the wiring board according to the third embodiment of the present invention in order. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted. Further, portions not particularly described can be formed by the same method as in the first embodiment.

  First, the process shown in FIG. 3A is the same as the process shown in FIG. 1A, and the solder resist layer 102 is formed on the support substrate 101, and the opening 102 </ b> A is formed in the solder resist layer 102.

  Next, in the step shown in FIG. 3B, an electrode height adjusting layer 103B is formed on the support substrate 101 exposed from the opening 102A by, for example, an electrolytic plating method. In this case, it is possible to form the electrode height adjusting layer 103B by electrolytic plating if the support substrate 101 is made of a conductive material, and it is more preferable if the support substrate 101 is made of a low resistance conductive material such as Cu. .

  Next, in the step shown in FIG. 3C, in the same manner as the step shown in FIG. 1B of Example 1, the electrode height is obtained by electrolytic plating using the support substrate 101 and the electrode height adjusting layer 103B as conductive paths. An electrode 103C made of, for example, Au / Ni is formed on the adjustment layer 103B.

  Next, in the steps shown in FIGS. 3D to 3F, the insulating layer 104, the via plug 105, the pattern wiring 106, and the solder resist layer 107 are the same as the steps shown in FIGS. 1C to 1E of the first embodiment. Then, the opening 107A is formed, and the support substrate 101 is removed to form the wiring substrate 100B.

  In the case of this example, in the step shown in FIG. 3F, when the support substrate 101 is removed by wet etching, the electrode height adjustment layer 103B is similarly removed. For this reason, it is preferable that the support substrate 101 and the electrode height adjustment layer 103B are made of the same material, for example, Cu or Cu alloy.

  In the case of this embodiment, it is possible to form a wiring board in the same manner as in Embodiment 1 except for the method of forming the electrode 103C, and the same effects as in Embodiment 1 can be obtained.

  In the wiring board 100 </ b> B according to the present embodiment, the electrode 103 </ b> C has a structure that is recessed from the outer surface of the solder resist layer 102.

  For this reason, the mechanical strength of the electrode 103C is improved. Further, when the electrode 103C and the connection terminal are connected by soldering, there is an effect of suppressing the outflow of the solder and the adjacent electrodes from being short-circuited. Further, when the solder ball is joined to the electrode 103C, there is an effect that the solder ball can be suitably placed.

  Further, the structure in which the electrode shown in this embodiment is recessed from the solder resist layer can be changed to the structure shown in the next embodiment.

Example 4
FIGS. 4A to 4F are diagrams illustrating a method of manufacturing a wiring board according to a fourth embodiment of the present invention, following the procedure. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted. In addition, portions not particularly described can be formed by the same method as in the third embodiment.

  First, the process shown in FIG. 4A is the same as the process shown in FIG. 3A. The solder resist layer 102 is formed on the support substrate 101, and the opening 102A is formed in the solder resist layer 102.

  Next, in the step shown in FIG. 4B, an electrode height adjusting layer 103D is formed on the support substrate 101 exposed from the opening 102A by, for example, an electrolytic plating method. In the case of Example 3, for example, the thickness of the electrode height adjustment layer 103B is thinner than the thickness of the solder resist layer 102, but in the case of this example, the thickness of the electrode height adjustment layer 103D. Is substantially the same as the thickness of the solder resist layer 102.

  Next, in the step shown in FIG. 4C, in the same manner as the step shown in FIG. 3C of Example 3, the electrode height is obtained by electrolytic plating using the support substrate 101 and the electrode height adjustment layer D as conductive paths. An electrode 103E made of, for example, Au / Ni is formed on the adjustment layer 103D.

  Next, in the steps shown in FIGS. 4D to 4F, the insulating layer 104, the via plug 105, the pattern wiring 106, and the solder resist layer 107 are the same as the steps shown in FIGS. 3D to 3F of the third embodiment. And the opening 107A is formed, and a wiring substrate 100C is formed.

  In the case of this example, similarly to the step shown in FIG. 3F of Example 3, when the support substrate 101 is removed by wet etching, the electrode height adjustment layer 103D is similarly removed. For this reason, it is preferable that the support substrate 101 and the electrode height adjustment layer 103D are made of the same material, for example, Cu.

  In the case of this example, a wiring board can be formed in the same manner as in Example 3 except for the method of forming the electrode 103E, and the same effects as in Example 3 can be obtained.

  In the wiring board 100 </ b> C according to the present embodiment, the electrode 103 </ b> E has a structure that is recessed from the outer surface of the solder resist layer 102, and the electrode 103 </ b> E has a structure that is substantially embedded in the insulating layer 104. . That is, the entire side wall surface of the electrode 103E is formed in contact with the insulating layer 104. For this reason, in addition to the effect of the third embodiment, the mechanical strength of the electrode 103C is further improved as compared with the third embodiment.

  The area of the electrode 103E is larger than the area of the opening 102A. This is because when the electrode 103E is formed by electrolytic plating, the electrode 103E grows substantially isotropically, so that there is growth in the lateral direction of the electrode. For this reason, the peripheral portion of the electrode 103E is covered with the solder resist layer 102, and the strength of the electrode 103E is improved.

  Further, in this embodiment, the case where the thickness of the electrode height adjustment layer is substantially the same as the thickness of the solder resist layer 102 has been described as an example. However, the thickness of the electrode height adjustment layer is the same as that of the solder resist layer. If the thickness is equal to or greater than the thickness of the layer 102, the same effects as those described above can be obtained.

(Example 5)
Further, for example, in the case of the above-described Examples 1 to 4, it is also possible to form a wiring board on each supporting board using a structure in which two supporting boards 101 are bonded together. The efficiency of forming the wiring board can be improved.

  FIG. 5 is a diagram showing a method of manufacturing a wiring board according to Embodiment 5 of the present invention. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.

  FIG. 5 shows a process corresponding to the process shown in FIG. Referring to FIG. 5, in this embodiment, the support substrate 101 has a structure bonded to the support substrate 101a. The support substrate 101a is formed with a solder resist layer 102a, an electrode 103a, an insulating layer 104a, a via plug 105a, a pattern wiring 106a, a solder resist layer 107a, and an opening 107b.

  The solder resist layer 101a, the electrode 103a, the insulating layer 104a, the via plug 105a, the pattern wiring 106a, the solder resist layer 107a, and the opening 107b are respectively formed in the solder resist layer 101, the electrode 103, the insulating layer 104, the via plug 105, and the pattern. It corresponds to the wiring 106, the solder resist layer 107, and the opening 107A, and can be formed in the same manner as in the first embodiment.

  Further, after the step shown in this figure, the support substrate 101 and the support substrate 101a are separated, and a step corresponding to the step shown in FIG. 1E of Example 1 is performed, and the support substrate 101 and the support substrate 101a are wetted. By removing by etching, two wiring boards can be formed.

  As described above, the structures, materials, and the like described in the embodiments are merely examples, and it is obvious that modifications and changes can be appropriately made. For example, the material constituting the electrodes 103, 103A, 103C, 103E, 103a and the like is not limited to Au / Ni. For example, Au / Ni / Cu, Au / Pd / Ni, Au / Pd / Ni / Cu, Use Au / Pd / Ni / Pd, Au / Pd / Ni / Pd / Cu, Sn-Pb / Ni, Sn-Pb / Ni / Cu, Sn-Ag / Ni, Sn-Ag / Ni / Cu, etc. Is possible. In addition, said material is described in an order from the metal layer used as the surface (outer side) when a wiring board is completed.

  Further, if necessary, for example, a reinforcing plate may be provided on the periphery of the wiring board to increase the rigidity of the wiring board.

(Example 6)
Next, an example of manufacturing a semiconductor device by mounting a semiconductor chip on the above wiring board will be described step by step with reference to FIGS. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted. In the following example, a case where a semiconductor chip is mounted on the mounting board described in the first embodiment will be described as an example. However, the semiconductor chip is also mounted on the mounting board described in the second to fifth embodiments in the same procedure. Can be mounted to manufacture a semiconductor device.

  In the method of manufacturing a semiconductor device according to this example, first, the steps shown in FIGS. 1A to 1D shown in Example 1 are performed.

  Next, in the step shown in FIG. 6A, an electrode 108 made of Au / Ni is formed on the pattern wiring 106 exposed from the opening 107A of the solder resist layer 107, for example, by sputtering, electrolytic plating, or electroless. It is formed by a plating method or the like.

  Next, in the step shown in FIG. 6B, the semiconductor chip 201 on which the semiconductor chip connection terminals (for example, solder balls) 202 are formed is connected so that the semiconductor chip connection terminals 202 and the electrodes 108 are electrically connected. Flip chip mounting. The semiconductor chip 201 is electrically connected to the pattern wiring 106 through the electrode 108.

  Next, the underfill 203 is infiltrated and cured between the semiconductor chip 201 and the solder resist layer 107, thereby ensuring insulation and reliability of the mounting portion.

  Next, in the step shown in FIG. 6C, the support substrate 101 is removed by wet etching, for example, in the same manner as in the step shown in FIG. 1E.

  Next, in the step shown in FIG. 6D, external connection terminals (for example, solder balls) 109 are formed on the electrodes 103 exposed by removing the support substrate 101. In the case of the present embodiment, since a case where a semiconductor device having a BGA (Ball Grid Array) structure is manufactured is described as an example, solder balls are formed on the electrode 103, but the present invention is not limited thereto. It is not something.

  For example, in a semiconductor device having a PGA (Pin Grid Array) structure, a pin is formed on the electrode 103 as an external connection terminal. Alternatively, an external connection terminal may be omitted, and an LGA (Land Grid Array) structure in which an electrode of a wiring board (semiconductor device) itself is used as an external connection terminal may be employed.

  Next, in the step shown in FIG. 6E, the substrate 104 and the solder resist layers 102 and 107 are cut and separated into individual pieces, whereby the semiconductor device 200 shown in FIG. 6F can be formed. In this case, a structure in which a plurality of semiconductor chips 201 are mounted is formed on the substrate 104, and then the substrate 104 (solder resist layers 102 and 107) is cut and separated into individual pieces. Can be formed. In this embodiment, only one semiconductor device is shown.

  According to the method for manufacturing a semiconductor device according to the present embodiment, it is possible to manufacture a semiconductor device that exhibits the same effects as those described in the first embodiment, can be reduced in thickness, and can handle high-density wiring. .

(Example 7)
Further, the semiconductor chip mounting method is not limited to the case described in the sixth embodiment. FIG. 7 illustrates a method for manufacturing a semiconductor device according to the seventh embodiment. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.

  In the method of manufacturing a semiconductor device according to the present embodiment, first, the steps up to FIG.

  Next, in the process shown in FIG. 7 (corresponding to the process of FIG. 6B in Example 6), the semiconductor chip 201A is mounted on the solder resist layer 107, and the semiconductor chip 201A and the electrode 108 are connected by the wire 202A. Connecting. In this case, a resin film may be inserted and bonded between the semiconductor chip 201A and the solder resist layer 107. Further, the semiconductor chip 201A is sealed with a resin layer 203A.

  After the step of FIG. 7, the semiconductor device can be manufactured in the same manner as in Example 6 by performing the steps corresponding to FIGS. 6C to 6F shown in Example 6. In this manner, the semiconductor chip can be mounted by wire bonding (the same applies to the following examples).

(Example 8)
Further, in the above-described Example 6 or Example 7, the method of forming the external connection terminal (solder ball) 109 may be changed.

  8A to 8B are diagrams illustrating a method for manufacturing a semiconductor device according to the eighth embodiment. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.

  In the method of manufacturing a semiconductor device according to this embodiment, first, the process shown in FIG. 1A of Embodiment 1 is performed.

  Next, in the step shown in FIG. 8A, the support substrate 101 exposed from the opening 102A is etched using, for example, the solder resist layer 102 as a mask to form a recess 101H.

  Next, in the step shown in FIG. 8B, external connection terminals 109 are formed so as to bury the recesses 101H by electrolytic plating such as solder using the support substrate 101 as a conductive path. Further, an electrode 103 made of, for example, Au / Ni is formed on the external connection terminal 109 by electrolytic plating in the same manner as the process shown in FIG. 1B.

  The following steps may be performed in the same manner as in Example 7 or Example 8. That is, the steps shown in FIGS. 1C to 1D and the steps shown in FIGS. 6A to 6F may be performed. Further, the process of FIG. 6B may be replaced with the process of FIG. In this case, the step of forming the external connection terminal shown in FIG. 6D is not necessary. In this way, the method / process for forming the external connection terminal may be changed.

Example 9
Further, in the above Examples 6 to 8, the semiconductor chip is mounted on the solder resist layer 107 side, but the method for manufacturing a semiconductor device according to the present invention is not limited to this. For example, as described below, the semiconductor chip may be mounted so as to be connected to an electrode exposed by removing the support substrate.

  9A to 9F are views showing a method for manufacturing a semiconductor device according to the ninth embodiment. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.

  In the method of manufacturing a semiconductor device according to the present embodiment, first, steps corresponding to the steps shown in FIGS. 1A to 1D shown in the first embodiment are performed.

  Next, in the step shown in FIG. 9A, an electrode 108F made of Au / Ni is formed on the pattern wiring 106 exposed from the opening 107A of the solder resist layer 107 by, for example, sputtering, electrolytic plating, or electroless plating. It is formed by the method.

  In this embodiment, since the semiconductor chip is mounted on the electrode 103F (corresponding to the electrode 103 in the embodiments 6 to 8), the area of the electrode 103F is smaller than that of the electrode 103 in the embodiments 6 to 8. It has become. Further, since an external connection terminal (for example, a solder ball) is formed in the electrode 108F (corresponding to the electrode 108 in the case of Examples 6 to 8) in a later process, the electrode 108F is compared with the electrode 108 of Examples 6 to 8. The area of the electrode 108F is increased. The steps so far are the same as those in Examples 6 to 8 except for the shapes of these electrodes (the solder resist openings corresponding to the electrodes).

  Next, in the step shown in FIG. 9B, the support substrate 101 is removed by, for example, wet etching in the same manner as the step shown in FIG. 1E. Here, the electrode 103F is exposed.

  Next, in the step shown in FIG. 9C, the semiconductor chip 201F on which the semiconductor chip connection terminal (eg, solder ball) 202F is formed is electrically connected to the semiconductor chip connection terminal 202F and the electrode 103F. Flip chip mounting. The semiconductor chip 201F is electrically connected to the pattern wiring 106 through the electrode 103F. That is, in this embodiment, a semiconductor chip is mounted on the side of the electrode 103F exposed by removing the support substrate 101.

  Next, the underfill 203F is infiltrated and cured between the semiconductor chip 201F and the solder resist layer 102 to ensure insulation and reliability of the mounting portion.

  Next, in the step shown in FIG. 9D, external connection terminals (solder balls) 109F are formed on the electrodes 108F. As in the case of the sixth embodiment, the formation of the external connection terminal 109F may be omitted, or a pin may be formed on the electrode 108F as an external connection terminal.

  Next, in the step shown in FIG. 9E, the substrate 104 and the solder resist layers 102 and 107 are cut and separated into individual pieces, whereby the semiconductor device 200A shown in FIG. 9F can be formed.

  According to the method for manufacturing a semiconductor device according to the present embodiment, it is possible to manufacture a semiconductor device that exhibits the same effects as those described in Embodiment 6, can be reduced in thickness, and can handle high-density wiring. . Further, the semiconductor chip may be mounted by wire bonding and resin sealing as shown in the seventh embodiment.

(Example 10)
Further, in the ninth embodiment, semiconductor chip connection terminals (for example, solder balls) for mounting a semiconductor chip may be provided on the substrate side as described below.

  10A to 10F are diagrams illustrating the method for manufacturing the semiconductor device according to the tenth embodiment. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.

  In the method of manufacturing a semiconductor device according to this embodiment, first, a process corresponding to the process shown in FIG. However, as described in the ninth embodiment, the opening 102A of the solder resist layer 102 is made smaller than that in the first embodiment in accordance with the mounting of the semiconductor chip.

  Next, in the step shown in FIG. 10A, the support substrate 101 exposed from the opening 102A is etched using, for example, the solder resist layer 102 as a mask to form a recess 101h.

  Next, in the step shown in FIG. 10B, a semiconductor chip connection terminal (eg, solder ball) 202G is formed so as to bury the recess 101h by electrolytic plating such as solder using the support substrate 101 as a conductive path. Further, an electrode 103F made of, for example, Au / Ni is formed on the semiconductor chip connection terminal 202G by electrolytic plating.

  Next, in the step shown in FIG. 10C, the insulating layer 104, the via plug 105, and the pattern wiring 106 are formed in the same manner as the step shown in FIG. 1C of the first embodiment.

  Next, in the process shown in FIG. 10D, a solder resist layer 107 having an opening 107A from which a part of the pattern wiring 106 is exposed is formed in the same manner as in the process of FIG.

  Next, an electrode 108F made of Au / Ni is formed on the pattern wiring 106 exposed from the opening 107A of the solder resist layer 107 in the same manner as in the process of FIG.

  Next, in the step shown in FIG. 10E, the support substrate 101 is removed by wet etching, for example. Here, the solder ball 202G is exposed.

  Next, in the step shown in FIG. 10F, the semiconductor chip 201G is mounted on the exposed semiconductor chip connection terminal 202G. In this case, since the semiconductor chip connection terminal is formed on the substrate side, it is not necessary to form the semiconductor chip connection terminal on the semiconductor chip side.

  Further, the underfill 203G is infiltrated and cured between the semiconductor chip 201G and the solder resist layer 102, thereby ensuring insulation and reliability of the mounting portion.

  The processes after FIG. 10F can form a semiconductor device by performing a process corresponding to the process of FIG.

  In this way, semiconductor chip connection terminals (for example, solder balls) for connecting the semiconductor chip and the substrate can be formed on the substrate side.

  In the method for manufacturing a semiconductor device shown in the sixth to tenth embodiments, the case where the wiring portion has one layer has been described as an example. However, the present invention is not limited to this. For example, the present invention can also be applied to the case of manufacturing a semiconductor device (wiring board) having a multilayer wiring structure in which wiring portions including via plugs 105 and pattern wirings 106 are stacked in multiple layers. It is clear.

  Although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the specific embodiments described above, and various modifications and changes can be made within the scope described in the claims.

  According to the present invention, it is possible to provide a wiring board that can be thinned and can handle high-density wiring, a manufacturing method thereof, a semiconductor device in which a semiconductor chip is mounted on the wiring board, and a manufacturing method thereof. Can do.

FIG. 6 is a view (No. 1) illustrating the method for manufacturing the wiring board according to the first embodiment. FIG. 6 is a diagram (No. 2) illustrating the method for manufacturing the wiring board according to the first embodiment; FIG. 6 is a diagram (No. 3) illustrating the method for manufacturing the wiring board according to the first embodiment; FIG. 6 is a diagram (No. 4) illustrating the method for manufacturing the wiring board according to the first embodiment; FIG. 6 is a diagram (No. 5) for illustrating a method of manufacturing a wiring board according to Example 1; FIG. 9 is a diagram (No. 1) illustrating a method for manufacturing a wiring board according to Example 2; FIG. 10 is a diagram (No. 2) illustrating the method for manufacturing the wiring board according to the second embodiment. FIG. 11 is a diagram (No. 3) illustrating the method for manufacturing the wiring board according to the second embodiment. FIG. 8 is a diagram (No. 4) illustrating the method for manufacturing the wiring board according to the second embodiment. FIG. 10 is a diagram (No. 5) for illustrating a method of manufacturing a wiring board according to Example 2; FIG. 6 is a diagram (No. 6) illustrating a method for manufacturing a wiring board according to Example 2; FIG. 10 is a diagram (No. 1) illustrating a method for manufacturing a wiring board according to Example 3; FIG. 10 is a second diagram illustrating the method of manufacturing the wiring board according to the third embodiment. FIG. 13 is a diagram (No. 3) illustrating the method for manufacturing the wiring board according to the third embodiment. FIG. 10 is a diagram (No. 4) illustrating the method for manufacturing the wiring board according to the third embodiment. FIG. 10 is a diagram (No. 5) for illustrating a method of manufacturing a wiring board according to Example 3; FIG. 6 is a diagram (No. 6) illustrating a method for manufacturing a wiring board according to Example 3; FIG. 10 is a diagram (No. 1) illustrating a method for manufacturing a wiring board according to Example 4; FIG. 10 is a diagram (No. 2) for illustrating a method of manufacturing a wiring board according to Example 4; FIG. 11 is a diagram (No. 3) illustrating the method for manufacturing the wiring board according to the fourth embodiment. FIG. 10 is a diagram (No. 4) for illustrating a method of manufacturing a wiring board according to Example 4; FIG. 10 is a diagram (No. 5) for illustrating a method of manufacturing a wiring board according to Example 4; FIG. 6 is a diagram (No. 6) illustrating a method for manufacturing a wiring board according to Example 4; FIG. 10 is a diagram illustrating a method for manufacturing a wiring board according to Example 5; FIG. 10A is a diagram (No. 1) illustrating a method for manufacturing a semiconductor device according to Example 6; FIG. 10 is a second diagram illustrating the method for fabricating the semiconductor device according to the sixth embodiment; FIG. 11 is a diagram (No. 3) for illustrating a method for manufacturing a semiconductor device according to Example 6; FIG. 14 is a diagram (No. 4) for illustrating a method for manufacturing a semiconductor device according to Example 6; FIG. 10 is a diagram (No. 5) for illustrating a method for manufacturing a semiconductor device according to Example 6; FIG. 6 is a diagram (No. 6) illustrating a method for manufacturing a semiconductor device according to Example 6; FIG. 10 illustrates a method for manufacturing a semiconductor device according to Example 7; FIG. 10A is a diagram (No. 1) illustrating a method for manufacturing a semiconductor device according to Example 8; FIG. 10 is a second diagram illustrating the method for fabricating the semiconductor device according to the eighth embodiment. FIG. 10A is a diagram (No. 1) illustrating a method for manufacturing a semiconductor device according to Example 9; FIG. 22 is a second diagram illustrating the method for fabricating the semiconductor device according to the ninth embodiment; FIG. 13 is a diagram (No. 3) for illustrating a method for manufacturing a semiconductor device according to Example 9; FIG. 11 is a diagram (No. 4) for illustrating a method for manufacturing a semiconductor device according to Example 9; FIG. 11 is a diagram (No. 5) for illustrating a method for manufacturing a semiconductor device according to Example 9; FIG. 16 is a diagram (No. 6) illustrating a method for manufacturing a semiconductor device according to Example 9; FIG. 18 is a diagram (No. 1) for illustrating a method for manufacturing a semiconductor device according to Example 10; FIG. 22 is a second diagram illustrating the method for fabricating the semiconductor device according to the tenth embodiment; FIG. 10 is a diagram (No. 3) for illustrating a method for manufacturing a semiconductor device according to Example 10; FIG. 11 is a diagram (No. 4) for illustrating a method for manufacturing a semiconductor device according to Example 10; FIG. 11 is a diagram (No. 5) for illustrating a method for manufacturing a semiconductor device according to Example 10; FIG. 6 is a diagram (No. 6) illustrating a method for manufacturing a semiconductor device according to Example 10;

Explanation of symbols

100, 100A, 100B, 100C Wiring substrate 101, 101a Support substrate 102, 107, 107a Solder resist layer 103, 103a, 103A, 103C, 103E Electrode 104, 104a Insulating layer 105, 105a Via plug 106, 106a Pattern wiring 102A, 107A Opening Part 201, 201F, 201G Semiconductor chip 202F, 202G Solder ball 203F, 203G Underfill

Claims (17)

A first step of forming a first solder resist layer having a first opening on a support substrate;
A second step of forming a first electrode on a portion of the support substrate exposed in the first opening;
A third step of forming an insulating layer on the first electrode and the first solder resist layer, and forming a wiring portion connected to the first electrode in the insulating layer;
A fourth step of forming a second solder resist layer having a second opening in the wiring portion;
One surface of the insulating layer is covered with the first solder resist layer having the first opening, and the other surface of the insulating layer has the second opening. And a fifth step of removing the support substrate so as to be covered with a solder resist layer. The third step includes
  Forming a via hole in the insulating layer;
  Providing a seed layer on the insulating layer, and then forming a wiring portion including a via plug provided in the via hole and a wiring pattern provided on the insulating layer by performing electroplating. The method of manufacturing a wiring board according to claim 1. In the second step, the first electrode is formed so that at least a part of the first electrode is embedded in the first opening of the first solder resist layer. A method of manufacturing a wiring board according to claim 1 or 2 . The supporting substrate is made of a conductive material, said first electrode, said one of claims 1 to 3, characterized in that it is formed by electroplating to the supporting substrate and the conductive path, wherein any one Wiring board manufacturing method. The second step includes a step of etching a portion of the support substrate exposed from the first opening to form a recess, and the first electrode is formed in the recess. The manufacturing method of the wiring board in any one of Claims 1 thru | or 4 . The second step includes a step of forming an electrode height adjustment layer in the first opening, and the first electrode is formed on the electrode height adjustment layer. 5. The method for manufacturing a wiring board according to any one of 1 to 4 . The method of manufacturing a wiring board according to claim 6, wherein the electrode height adjustment layer is removed together with the support substrate in the fifth step. The supporting substrate and the height adjustment layer manufacturing method of a wiring board according to claim 6 or 7, wherein the formed of Cu or a Cu alloy. On the wiring portion of the exposed portion in the second opening, of the claims 1 to 8, characterized in that a step of forming a second electrode, according to any one claim wiring board Manufacturing method. Repeating the third step prior to the fourth step, providing a step of forming a multilayer wiring structure in which the insulating layer and the wiring portion are laminated in a multilayer ;
The insulating layer forming one surface of the multilayer wiring structure is covered with the first solder resist layer, and the insulating layer forming the other surface of the multilayer wiring structure is covered with the second solder resist layer. It claims 1 to the 9, method of manufacturing a wiring board of any one, wherein the to be.   The method further comprises a step of etching the support substrate exposed from the first opening to form a recess after the first step, and a step of forming an external connection terminal in the recess. Item 4. A method for manufacturing a wiring board according to Item 1.   After the first step, the method further comprises a step of etching the support substrate exposed from the first opening to form a recess, and a step of forming a semiconductor chip connection terminal in the recess. The manufacturing method of the wiring board of Claim 1. Two support substrates are prepared, two of the support substrates are bonded together, and the first step, the first step are performed on each surface of the two support substrates located on the opposite side of the bonded surfaces. The method of manufacturing a wiring board according to any one of claims 1 to 12 , wherein the processing of step 2, the third step, the fourth step, and the fifth step is performed. . 14. The method of manufacturing a wiring board according to claim 13, wherein after the fourth step, the two support substrates are separated, and then the processing of the fifth step is performed. Of claims 1 to 14, a manufacturing method of a semiconductor device using the method of manufacturing the wiring board according to any one,
A method of manufacturing a semiconductor device, further comprising a mounting step of mounting a semiconductor chip so as to be electrically connected to the wiring portion through the second electrode after the fourth step. Of claims 1 to 14, a manufacturing method of a semiconductor device using the method of manufacturing the wiring board according to any one,
A method of manufacturing a semiconductor device, further comprising a mounting step of mounting a semiconductor chip so as to be electrically connected to the wiring portion through the first electrode after the fifth step. Of claims 1 to 14, a manufacturing method of a semiconductor device using the method of manufacturing the wiring board according to any one,
A method of manufacturing a semiconductor device, further comprising a mounting step of mounting a semiconductor chip so as to be electrically connected to the wiring portion through the second electrode after the fifth step.

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