TWI496243B - Method for fabricating embedded component semiconductor package - Google Patents

Description

Component embedded semiconductor package manufacturing method

The present invention relates to a method of fabricating a semiconductor package, and more particularly to a method of fabricating an element buried semiconductor package.

In recent years, with the rapid development of electronic technology, the high-tech electronics industry has come out one after another, making more humanized and better-functioning electronic products constantly innovating and designing towards light, thin, short and small trends. Currently, in a semiconductor process, a chip package carrier is one of the package components that are often used. The chip package carrier is, for example, a multilayer circuit board which is mainly composed of a plurality of circuit layers and a plurality of dielectric layers alternately stacked.

In the above multilayer circuit board, a multilayer wiring and a multilayer dielectric layer are conventionally fabricated on a core substrate, and the core substrate is a carrier having a certain thickness. As the electronic component is thinned, the thickness of the core substrate needs to be thinned to be disposed in a limited space of the electronic component. However, when the thickness of the core substrate is reduced, the thinned core substrate is insufficient in rigidity, so that it is easy to increase the difficulty in the substrate process and the packaging process and the defective rate.

In view of this, a coreless process for a multilayer circuit board has been developed, and a multilayer circuit board manufactured by the coreless process has been developed to solve the above-described packaging process. To put it simply, the so-called coreless process does not have the core substrate described above, but uses a temporary carrier as a support and builds a build-up line thereon. In general, the build-up lines of multilayer circuit boards are mostly built up or laminated. Therefore, it has the characteristics of high line density and reduced line spacing. After the build-up line process is completed, a multi-layer circuit board for the packaging process is completed by separating the carrier board and the multilayer wiring board. In the conventional coreless process, the edge of the partial carrier and the edge of the partial multilayer wiring board are first bonded with adhesive. After the multilayer wiring board is subjected to a plurality of processes (for example, etching, pressing, or laser cutting), the adhesive portion between the carrier and the multilayer wiring board is cut off to obtain a multilayer wiring board for the packaging process.

However, in the conventional coreless process, since the carrier board and the multilayer circuit board are only partially bonded by the adhesive, it is easy to cause relative movement in the above multi-pass process, or the carrier board and the multilayer circuit board are not bonded. Part of the deformation, which increases the non-core process non-performing rate.

The invention provides a method for fabricating an element embedded semiconductor package, which can simplify the process steps and improve the process yield.

The invention provides a method for fabricating an element buried semiconductor package, which comprises the following steps. First, a metal substrate is provided. Next, a metal layer is formed on the metal substrate, wherein the metal layer covers the metal substrate, and the metal layer has an upper surface and a lower surface opposite to each other and a first side surface connecting the upper surface and the lower surface. Thereafter, a first patterned photoresist layer is formed on the metal layer, wherein the first patterned photoresist layer exposes a portion of the upper surface and a portion of the lower surface of the metal layer. Then, a plurality of first pads are formed on the upper surface and the lower surface of the metal layer exposed by the first patterned photoresist layer, wherein the first patterned photoresist layer covers a second of each of the first pads Side surface. Thereafter, the first patterned photoresist layer is removed to expose the second side surface of the first pad. Thereafter, a plurality of electronic components are disposed on the first pad, and an insulating layer is further laminated on the metal layer, wherein the insulating layer covers the electronic component, the first pad, and a portion of the metal layer.

In an embodiment of the invention, the material of the metal substrate comprises aluminum or stainless steel.

In an embodiment of the invention, the above method of forming a metal layer comprises electroplating or sputtering.

In an embodiment of the invention, the metal layer is subjected to a surface treatment to form an oxide layer on the metal layer before the first patterned photoresist layer is formed.

In an embodiment of the invention, the step of forming the first patterned photoresist layer comprises the following steps. First, a photoresist layer is formed on the oxide layer, and the photoresist layer is coated with the oxide layer. Next, the photoresist layer is patterned to form a first patterned photoresist layer that exposes a portion of the oxide layer. Thereafter, the first patterned photoresist layer is used as a mask to remove the oxide layer exposed by the first patterned photoresist layer, so that the first patterned photoresist layer exposes a portion of the upper surface of the metal layer and Part of the lower surface.

In one embodiment of the invention, the method of removing the oxide layer exposed by the first patterned photoresist layer comprises an acid etching process.

In an embodiment of the invention, the method of forming the first pad comprises electroplating.

In an embodiment of the invention, the material of the first pad comprises copper or gold/nickel/copper.

In an embodiment of the invention, the method further includes forming a conductive layer on the first pad before the electronic component is disposed on the first pad, wherein the electronic component is electrically connected to the first pad through the conductive layer.

In an embodiment of the invention, the material of the conductive layer comprises a conductive adhesive or solder.

In an embodiment of the invention, the method further comprises the steps of: forming a primer on the metal layer before pressing the insulating layer on the metal layer, wherein the primer fills the gap between the first pads and covers the first layer a second side surface of the pad, an electronic component, and a portion of the upper surface, a portion of the lower surface, and the side surface of the metal layer. After pressing the insulating layer on the metal layer, the insulating layer covers the primer. In an embodiment of the invention, the material of the insulating layer comprises ABF (Ajinomoto build-up film) resin and pure glue, and the material system of the pure glue is epoxy or acrylic.

In an embodiment of the invention, the following steps are further included. First, a copper foil layer is pressed onto the insulating layer while pressing the insulating layer on the metal layer. Next, an etching process is performed to remove the copper foil layer to expose the insulating layer.

In an embodiment of the invention, the following steps are further included. First, after pressing the insulating layer on the metal layer, a plurality of blind holes are formed on the insulating layer, wherein the blind holes expose a portion of the first pads. Next, a plating seed layer is formed on the insulating layer, and the plating seed layer covers the inner wall of the blind hole and the insulating layer. Next, a second patterned photoresist layer is formed on the electroplated seed layer, wherein the second patterned photoresist layer exposes a portion of the electroplated seed layer on the insulating layer and in the blind via. Then, the second patterned photoresist layer is a plating mask, and the plurality of conductive pillars and the plurality of second pads are formed on the second patterned photoresist layer to expose the electricity. The seed layer is plated, wherein the conductive pillar is located in the blind hole, and the second pad is located on the insulating layer and a part of the second pad is connected to the conductive pillar. A portion of the second pad is electrically connected to the first pad through the conductive post. Thereafter, the second patterned photoresist layer is removed to expose a portion of the electroplated seed layer. Next, the metal substrate and the metal layer are separated. Thereafter, the metal layer and the plating seed layer on the insulating layer are removed to expose a lower surface of each of the first pads and an insulating layer.

In one embodiment of the invention, the above method of forming a blind hole includes a laser drilling method.

In one embodiment of the invention, the method of removing the metal layer and the electroplated seed layer on the insulating layer includes an etching process.

In an embodiment of the invention, the method for separating the metal substrate from the metal layer includes a detachment method.

Based on the above, the component buried semiconductor package of the present invention is formed by treating the metal substrate and the metal layer covering the metal substrate as a supporting carrier, and transmitting the patterned photoresist layer through a portion of the metal layer. To form the required pads. Then, the electronic component is placed on the pad and formed by an initial pressing to form an insulating layer covering the electronic component, the pad and the partial metal layer, thereby forming the component buried semiconductor package. Compared with the prior art, the present invention does not need to use a colloid, and can effectively reduce the process difficulty and the process steps, thereby increasing the process yield of the component embedded semiconductor package. Furthermore, the present invention forms the pads by the arrangement of the patterned photoresist layer, so the thickness of the pads can be determined by the thickness of the patterned photoresist layer. In addition, in the present invention, the electronic component and the pad are covered by the method of pressing the insulating layer at a time, so that the component-embedded semiconductor package of the present invention is fabricated. The method can have the advantage of simplifying the process and the resulting product has a thinner package thickness.

The above described features and advantages of the present invention will be more apparent from the following description.

1A to 1J are schematic cross-sectional views showing a manufacturing process of an element-embedded semiconductor package according to an embodiment of the present invention. Referring to FIG. 1A, in the embodiment, the method for fabricating the component-embedded semiconductor package includes the following steps. First, referring to FIG. 1A, a metal substrate 110 is provided. In detail, the metal substrate 110 has a substrate upper surface 112 and a substrate lower surface 114 opposite to each other and a substrate side surface 116 connecting the substrate upper surface 112 and the substrate lower surface 114. In the present embodiment, the material of the metal substrate 110 is, for example, aluminum or stainless steel.

Next, referring to FIG. 1B, a metal layer 120 is formed on the metal substrate 110, wherein the metal layer 120 completely covers the metal substrate 110. In the present embodiment, the method of forming the metal layer 120 includes an electroplating method or a sputtering method, and the manner in which the metal layer 120 is formed is not limited thereto. More specifically, the metal layer 120 covers the substrate upper surface 112, the substrate lower surface 114, and the substrate side surface 116 of the metal substrate 110, and the metal layer 120 has an upper surface 122 and a lower surface 124 opposite to each other and a connecting upper surface. 122 and a first side surface 126 of the lower surface 124. In the present embodiment, the thickness of the metal layer 120 is, for example, between 2 micrometers (μm) and 4 micrometers (μm).

Next, referring to FIG. 1C, the metal layer 120 is subjected to a surface treatment. An oxide layer 128 is formed on the metal layer 120. The material of the oxide layer 128 is, for example, copper oxide. In the present embodiment, the oxide layer 128 has a roughened surface formed by, for example, browning or blackening of a printed circuit board process. Herein, the surface treatment of the metal layer 120 is aimed at increasing the roughness of the surface of the metal layer 120 to facilitate the subsequent adhesion of the material layer (such as a photoresist layer) formed on the metal layer 120. It should be noted that the surface step is an optional step, and the user can select whether to perform the surface treatment step according to the requirements of the manufacturing process, which is not limited herein.

Next, referring to FIG. 1D, a photoresist layer 130 is formed on the oxide layer 128, wherein the photoresist layer 130 completely covers the oxide layer 128. In the present embodiment, the thickness of the photoresist layer 130 is, for example, between 4 micrometers (μm) and 20 micrometers (μm).

Next, referring to FIG. 1E, the photoresist layer 130 described above is patterned to form a first patterned photoresist layer 132 exposing the partial oxide layer 128. It should be noted that the exposed oxide layer 128 is located on a portion of the upper surface 122 and a portion of the lower surface 124 of the metal layer 120.

Next, referring to FIG. 1F, the first patterned photoresist layer 132 is used as a mask to remove the oxide layer 128 exposed by the first patterned photoresist layer 132, thereby exposing the first patterned photoresist layer 132. A portion of the upper surface 122 and a portion of the lower surface 124 of the metal layer 120 are exited. In the present embodiment, the method of removing the oxide layer 128 exposed by the first patterned photoresist layer 132 is, for example, an acid etching method.

Next, referring to FIG. 1G, a plurality of first pads 140 are formed on the upper surface 122 of the metal layer 120 exposed by the first patterned photoresist layer 132. On the lower surface 124, the first patterned photoresist layer 132 covers a second side surface 142 of each of the first pads 140. In the present embodiment, the method of forming the first pads 140 is, for example, electroplating, and the material of the first pads 140 is, for example, copper or gold/nickel/copper. More specifically, when the first pad 140 is formed, a portion of the upper surface 122 and a portion of the lower surface 124 of the metal layer 120 exposed by the first patterned photoresist layer 132 are plated as a plating seed layer. The pad 140 is on the metal layer 120, so that it is not necessary to additionally form a plating seed layer, which can effectively simplify the process steps. Moreover, since the first pad 140 is formed by the arrangement of the first patterned photoresist layer 132, the thickness of the first pad 140 can be determined by the thickness of the first patterned photoresist layer 132. Therefore, the user can form the thickness of the pad required to meet the current trend of thinning according to requirements.

Next, referring to FIG. 1H, the first patterned photoresist layer 132 is removed to expose the second side surface 142 of the first pad 140.

Next, referring to FIG. 1I, a conductive layer 170 is formed on the first pad 140, wherein the conductive layer 170 is made of a conductive adhesive or solder. Herein, the purpose of forming the conductive layer 170 is to increase the adhesion force between the subsequent electronic component 150 and the first pad 140 when disposed. It should be noted that the step of forming the conductive layer 170 is an optional step, and the user may select whether to perform the step of forming the conductive layer 170 according to the requirements of the manufacturing process, which is not limited herein.

Thereafter, referring again to FIG. 1I, a plurality of electronic components 150 are disposed on the first pads 140, wherein the electronic components 150 can be active or passive components. More specifically, the electronic component 150 of the embodiment is disposed at the first Each of the electronic components 150 is located on the adjacent first pads 140 and electrically connected to the first pads 140 through the conductive layer 170.

Finally, referring to FIG. 1J , an insulating layer 160 is pressed onto the metal layer 120 , wherein the insulating layer 160 covers the electronic component 150 , the first pad 140 , and the partial metal layer 120 . In the present embodiment, the material of the insulating layer 160 is, for example, an ABF (Ajinomoto build-up film) resin. So far, the fabrication of the component buried semiconductor package 100 has been completed.

The component buried semiconductor package 100 of the present embodiment is formed by treating the metal substrate 110 and the metal layer 120 covering the metal substrate 110 as a supporting carrier and transmitting the patterned light of the partial metal layer 120. The resist layer 132 is disposed to form the desired pads 140. Then, the electronic component 150 is placed on the pad 140 and the insulating layer 160 covering the electronic component 150, the pad 140 and the partial metal layer 120 is formed by one press-fitting to form the component buried semiconductor package 100. Compared with the prior art, the embodiment does not need to use a colloid, which can effectively reduce the process difficulty and the process steps, thereby increasing the process yield of the component buried semiconductor package 100. Moreover, in this embodiment, the pad 140 is formed by the arrangement of the patterned photoresist layer 132. Therefore, the thickness of the pad 140 can be determined by the thickness of the patterned photoresist layer 132. In addition, in this embodiment, the electronic component 150 and the pad 140 are covered by the method of pressing the insulating layer 160 once. Therefore, the method for manufacturing the component buried semiconductor package 100 of the embodiment can have a simplified process. Advantages, and subsequent products can also have a thinner package thickness.

2A-2C are schematic cross-sectional views showing a partial step of a fabrication process of a component buried semiconductor package according to an embodiment of the invention. The same reference numerals are used to denote the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the detailed description is not repeated herein.

The manufacturing process of the buried semiconductor package 100a of the present embodiment can be substantially the same as that of the buried semiconductor package 100 of the foregoing embodiment. After FIG. 1I, the electronic component 150 is disposed. After a pad 140 is attached, referring to FIG. 2A, a primer 180 is formed on the metal layer 120, wherein the primer 180 fills the gap between the first pads 140 and covers the second side surface of the first pad 140. 142. The electronic component 150 and a portion of the upper surface 122 of the metal layer 120, a portion of the lower surface 124, and the first side surface 126. In this embodiment, the material of the primer 180 is, for example, an epoxy resin and a pure rubber, and the material system of the pure rubber is epoxy or acrylic.

Then, referring to FIG. 2B, the insulating layer 160a and a copper foil layer 190 on the metal layer 120 are laminated thereon, wherein the insulating layer 160a covers the primer 180, and the insulating layer 160a is made of epoxy resin or RCC, for example. (Resin copper foil).

Finally, referring to FIG. 2C, an etching process is performed to remove the copper foil layer 190 to expose the insulating layer 160a. At this point, the component is buried. Fabrication of semiconductor package 100a.

3A-3G are cross-sectional views showing a partial step of a manufacturing process of an element-embedded semiconductor package according to another embodiment of the present invention. It should be noted here that the following embodiment follows the fabrication flow of the above embodiment and performs a subsequent process on the component buried semiconductor package 100a. Therefore, the following embodiments will be used to refer to the same or similar elements in the above-mentioned embodiments, and the same reference numerals are used to denote the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.

In this embodiment, the method for fabricating the component-embedded semiconductor package further comprises the following steps. First, after the step of FIG. 1J, that is, after the insulating layer 160 is pressed onto the metal layer 120, please refer to FIG. 3A to form a plurality of layers. The blind vias 310 are on the insulating layer 160, wherein the blind vias 310 expose a portion of the first pads 140. In the present embodiment, the method of forming the blind via 310 includes a laser drilling method.

Next, referring to FIG. 3B, a plating seed layer 320 is formed on the insulating layer 160, wherein the plating seed layer 320 covers the inner wall of the blind via 310 and the insulating layer 160.

Next, referring to FIG. 3C, a second patterned photoresist layer 330 is formed on the plating seed layer 320, wherein the second patterned photoresist layer 330 exposes a portion of the plating seed layer on the insulating layer 160 and in the blind via 310. 320.

Next, referring to FIG. 3D, the second patterned photoresist layer 330 is used as a plating mask to form a plurality of conductive pillars 340 and a plurality of second pads 350 exposed to the second patterned photoresist layer 330. On the seed layer 320. The conductive pillar 340 is located in the blind hole 310, and the second pad 350 is located in the insulating layer 160. The second and second pads 350 are connected to the conductive pads 340. The second pads 350 are electrically connected to the first pads 140 through the conductive posts 340.

In view of the above, please refer to FIG. 3E to remove the second patterned photoresist layer 330 to expose a portion of the plating seed layer 320.

Next, referring to FIG. 3F, the metal substrate 110 and the metal layer 120 are separated to form two component buried semiconductor packages. In the present embodiment, the method of separating the metal substrate 110 from the metal layer 120 includes a lift-off method.

Of course, the method of separating the metal substrate 110 from the metal layer 120 is not limited to be performed in the above manner.

Thereafter, as shown in FIG. 3G, the metal layer 120 and the plating seed layer 320 on the insulating layer 160 are removed to expose the lower surface of each of the first pads 140 and the insulating layer 160. In the present embodiment, the method of removing the metal layer 120 includes an etching method, but the invention is not limited thereto. At this point, the fabrication of the two-element embedded semiconductor package 100b is completed, and each of the component-embedded semiconductor packages 100b can be electrically connected to other electronic components via the first pads 140 and the second pads 350, respectively.

In summary, the component-embedded semiconductor package of the present invention is formed by treating the metal substrate and the metal layer covering the metal substrate as a supporting carrier and transmitting a patterned photoresist layer exposing a portion of the metal layer. The settings are made to form the required pads. Then, the electronic component is placed on the pad and formed by an initial pressing to form an insulating layer covering the electronic component, the pad and the partial metal layer, thereby forming the component buried semiconductor package. Compared with the prior art, the invention does not need to use a colloid, which can effectively reduce the process difficulty and the process steps, thereby increasing the process of the component embedded semiconductor package. rate. Furthermore, the present invention forms the pads by the arrangement of the patterned photoresist layer, so the thickness of the pads can be determined by the thickness of the patterned photoresist layer. In addition, in the present invention, the electronic component and the pad are covered by the method of pressing the insulating layer at a time, so that the method for fabricating the component-embedded semiconductor package of the present invention can have the advantages of simplifying the process, and the formed The product has a thin package thickness.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 100a, 100b‧‧‧ component embedded semiconductor package

110‧‧‧Metal substrate

112‧‧‧Top surface of the substrate

114‧‧‧The lower surface of the substrate

116‧‧‧Side side surface

120‧‧‧metal layer

122‧‧‧ upper surface

124‧‧‧ lower surface

126‧‧‧ first side surface

128‧‧‧Oxide layer

130‧‧‧Photoresist layer

132‧‧‧First patterned photoresist layer

140‧‧‧first mat

142‧‧‧ second side surface

150‧‧‧Electronic components

170‧‧‧ Conductive layer

160, 160a‧‧‧Insulation

180‧‧‧Bottom

190‧‧‧copper layer

310‧‧‧Blind hole

320‧‧‧Electroplating seed layer

330‧‧‧Second patterned photoresist layer

340‧‧‧conductive column

350‧‧‧second mat

1A to 1J are schematic cross-sectional views showing a manufacturing process of an element-embedded semiconductor package according to an embodiment of the present invention.

2A-2C are schematic cross-sectional views showing a partial step of a fabrication process of a component buried semiconductor package according to an embodiment of the invention.

3A-3G are cross-sectional views showing a partial step of a manufacturing process of an element-embedded semiconductor package according to another embodiment of the present invention.

100‧‧‧Component buried semiconductor package

120‧‧‧metal layer

122‧‧‧ upper surface

124‧‧‧ lower surface

140‧‧‧first mat

150‧‧‧Electronic components

160‧‧‧Insulation

Claims (17)

A method for fabricating an embedded semiconductor package includes: providing a metal substrate; forming a metal layer on the metal substrate, wherein the metal layer covers the metal substrate, and the metal layer has an upper surface opposite to each other Forming a first patterned photoresist layer on the metal layer with a lower surface and a first side surface connecting the upper surface and the lower surface; wherein the first patterned photoresist layer exposes a portion of the metal layer The upper surface and a portion of the lower surface; forming a plurality of first pads on the upper surface and the lower surface of the metal layer exposed by the first patterned photoresist layer, wherein the first patterned photoresist a layer covering a second side surface of each of the first pads; removing the first patterned photoresist layer to expose the second side surfaces of the first pads; and providing a plurality of electronic components And the first insulating layer; and pressing an insulating layer on the metal layer, wherein the insulating layer covers the electronic components, the first pads and a portion of the metal layer. The method of fabricating a component-embedded semiconductor package according to claim 1, wherein the material of the metal substrate comprises aluminum, stainless steel and other steel conductive metals. The method of fabricating an element-embedded semiconductor package according to claim 1, wherein the method of forming the metal layer comprises electroplating or sputtering. The component buried semiconductor as described in claim 1 The method of manufacturing the package further includes: performing a surface treatment on the metal layer to form an oxide layer on the metal layer before forming the first patterned photoresist layer, wherein the oxide layer is formed by a brown layer Or blackening treatment. The method of fabricating the component-embedded semiconductor package of claim 4, wherein the step of forming the first patterned photoresist layer comprises: forming a photoresist layer on the oxide layer, the photoresist Coating a layer of the oxide layer; patterning the photoresist layer to form the first patterned photoresist layer exposing a portion of the oxide layer; and removing the layer by using the first patterned photoresist layer as a mask The first patterned photoresist layer exposes the oxide layer such that the first patterned photoresist layer exposes a portion of the upper surface and a portion of the lower surface of the metal layer. The method of fabricating an element-embedded semiconductor package according to claim 5, wherein the method of removing the oxide layer exposed by the first patterned photoresist layer comprises an acid etching method. The method of fabricating an element-embedded semiconductor package according to claim 1, wherein the method of forming the first pads comprises electroplating. The method of fabricating a component-embedded semiconductor package according to the first aspect of the invention, wherein the material of the first pads comprises copper or gold/nickel/copper. The component buried semiconductor as described in claim 1 The method of manufacturing the package further includes: forming a conductive layer on the first pads before the electronic components are disposed on the first pads, wherein the electronic components pass through the conductive layer and the first contacts Padded connection. The method of fabricating a component-embedded semiconductor package according to claim 9, wherein the conductive layer is made of a conductive adhesive or solder. The method for fabricating a component-embedded semiconductor package according to claim 1, further comprising: forming a primer on the metal layer before pressing the insulating layer on the metal layer, wherein the bottom The glue fills the gap between the first pads and covers the second side surfaces of the first pads, the electronic components, and a portion of the metal layer, the upper surface, a portion of the lower surface, and the side a surface; and after pressing the insulating layer on the metal layer, the insulating layer covers the primer. The method for fabricating a component-embedded semiconductor package according to claim 1, wherein the material of the insulating layer comprises ABF (Ajinomoto build-up film) resin and pure glue, and the material of the pure glue is epoxy ( Epoxy) or acrylic. The method for fabricating a component-embedded semiconductor package according to claim 1, further comprising: pressing the insulating layer on the metal layer while pressing a copper foil layer on the insulating layer; An etching process is performed to remove the copper foil layer to expose the insulating layer. The manufacturing method of the component-embedded semiconductor package of claim 1, further comprising: after pressing the insulating layer on the metal layer, forming a plurality of blind holes on the insulating layer, wherein the The blind hole exposes a portion of the first pads; forming a plating seed layer on the insulating layer, the plating seed layer covering the inner walls of the blind holes and the insulating layer; forming a second patterned photoresist layer The electroplated seed layer, wherein the second patterned photoresist layer exposes a portion of the electroplated seed layer on the insulating layer and the blind holes; and the second patterned photoresist layer is a plating mask. Forming a plurality of conductive pillars and a plurality of second pads on the plating seed layer exposed by the second patterned photoresist layer, wherein the conductive pillars are located in the blind holes, and the second pads The second pad is connected to the conductive pillars, and the second pads are electrically connected to the first pads through the conductive pillars; the second patterned photoresist is removed. a layer to expose the portion of the electroplated seed layer; separating the metal substrate from the a metal layer; and removing the metal layer and the plating seed layer on the insulating layer to expose a lower surface of each of the first pads and the insulating layer. The method of fabricating a component-embedded semiconductor package according to claim 14, wherein the method of forming the blind vias comprises laser Drilling method. The method of fabricating an element buried semiconductor package according to claim 14, wherein the method of removing the metal layer and the plating seed layer on the insulating layer comprises etching. The method of fabricating an element-embedded semiconductor package according to claim 14, wherein the method of separating the metal substrate from the metal layer comprises a lift-off method.