TW201205744A - Package structure and manufacturing method thereof - Google Patents

Package structure and manufacturing method thereof Download PDF

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Publication number
TW201205744A
TW201205744A TW099124010A TW99124010A TW201205744A TW 201205744 A TW201205744 A TW 201205744A TW 099124010 A TW099124010 A TW 099124010A TW 99124010 A TW99124010 A TW 99124010A TW 201205744 A TW201205744 A TW 201205744A
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Taiwan
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layer
metal layer
wafer
metal
conductive layer
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TW099124010A
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Chinese (zh)
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TWI400783B (en
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Chia-Ching Chen
Yi-Chuan Ding
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Advanced Semiconductor Eng
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A package structure includes a substrate, a chip, a first metal layer, a second metal layer, a third metal layer and a solder resist layer. The substrate has a first surface, a second surface and at least a through hole. The chip is disposed on the substrate and located in the first surface. The first metal layer is disposed on the first surface and extends to the chip. The second metal layer is disposed on the second surface. The third metal layer covers a sidewall of the through hole and connects the first metal layer and the second metal layer. The chip is electrically connected to the third metal layer and the second metal layer via the first metal layer. The solder resist layer fills the through hole and covers the chip, at least a portion of the first metal layer, at least a portion of the second metal layer and the third metal layer.

Description

201205744 ASEK2361 -NEW-FfiSI AL-TW-20100721 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體結構及其製作方法，且特 別是有關於一種封裝結構及其製作方法。 【先前技術】 晶片封裝的目的在於保護裸露的晶片、降低晶片接點 的密度及提供晶片良好的散熱。常見的封裝方法是晶片透 過打線接合（wire bonding )或覆晶接合（flip chip b〇nding ) 的方式而t裝至-封裝載板，以使晶丨上的接點可電性連 接至封裝載板。目此u的接點分佈可藉自封裝載板重 新配置，以符合下一層級的外部元件的接點分佈。 【發明内容】 本發明提供一種封裝結構，用以封裝晶片。201205744 ASEK2361 -NEW-FfiSI AL-TW-20100721 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor structure and a method of fabricating the same, and in particular to a package structure and a method of fabricating the same. [Prior Art] The purpose of the chip package is to protect the exposed wafer, reduce the density of the wafer contacts, and provide good heat dissipation of the wafer. A common packaging method is that the wafer is mounted to the package carrier through wire bonding or flip chip b〇nding so that the contacts on the wafer can be electrically connected to the package. board. The contact distribution of the u can be reconfigured from the package carrier to conform to the contact distribution of the external components of the next level. SUMMARY OF THE INVENTION The present invention provides a package structure for packaging a wafer.

本發明提供—種封裝結構的製作方法，用以製作上述 之封裝結構。 衣丨F工I 晶片 斤本發明提出—種封裝結構，其包括一基板、 -第-金屬層、—第二金屬層、一第三金屬層及一防銲層。 基，具有彼此相封的—第〆表面與—第二表面及至少一連 :工表面與：二表面的貫孔。晶片配置於基板上且位於 山第金屬層配置於基板的第一表面上且暴露 面，其中第一金屬層延伸至晶片上。第二金 屬曰配置於基板的第二表面上且暴露出部分第二表面。第 201205744 ASEK2361-NEW-F1NAL-TW-20I0072] J金” ^蓋貫孔的内壁且連接第—金屬層與第二金屬 :曰曰片透過弟一金屬層與第三金屬層及 =部%料充/孔且包覆晶片i少部分第一金屬層、 至/ 刀弟二金屬層及第三金屬層。 本發明提出一種封裝結構的製作方法，其包括下述步 Ξ茅一 ΪΪ、。基?具有彼此相對的-第-表面與-第 I开L右至〉、—連接第—表面與第二表面的貫孔。基板上 第—表面上且暴露出部分第-表面的第- :電=位於第二表面上的第二導電層。配置一晶片於 露出的部分第-表面上。形成-圖案化電 又π 刀弟—導電層上、部分第二導電層上及部分晶 ^三形成—金屬層於未配置_化電鮮幕的第-導電 曰/、第一‘電層上。金屬層覆蓋貫孔的内壁及第一導電層 所暴露出的部分第—表面上。金屬層延伸至於晶片上，且 過金屬層與第—導電層及第二導電層電性連接。移 電ft幕及其下方之第二導電層，以暴露出部分 充^日第—表面及部分晶片。形成—防銲層以填 充貝孔且匕设晶片及部分金屬層。 行曰由於本發明是在進行基板製㈣，同時進 丁曰曰片如此—來，可以減少製程步驟。 為讓本七明之上述特徵和優點能更明顯易懂 舉實施例，並配合所賴式作詳細㈣如下。 4寸 【實施方式】 201205744 ASEK2361-NEW-F1NAL-TW-20100721 圖1是本發明之一實施例之一種封裝結構的剖面示意 ^。請參考圖1，在本實施例中，封裝結構1〇〇包括一基 一晶片140、一第一金屬層152、一第二金屬層154、 弟二金屬層丨56及一防鮮層160。 鱼—，細來說，基板11〇具有彼此相對的一第一表面ιΐ2 弟二表面丨14及至少一連接第—表面112與第二表面 的貫孔116 (圖1中僅示意地綠示—個貫孔116)。在 貫1例中，基板11G為—介電核心（dide响_)。 且Φ Γ片14〇配置於基板110上且位於第一表面112上， aa&gt;； 14〇具有—絲面142與多個位於主動面⑷上 的接點。 金屬層⑸配置於基板11〇的第一表面112上且 二：：分第一表面112,其中第一金屬層152從第一表 /由晶片14G的-側延伸至晶片⑽的主動面142 二些接點144。第二金屬層154配置於基板110的第 及^_^14上且暴露出部分第二表面⑴。第-金屬層152 則為Z屬層154為兩層水平導電圖案，而第三金屬層156 、J与兩層線路圖案之間的垂直導電通道。 第—金屬層152延伸至晶片14〇的 只知例由於 晶片140上的這些接點144 144上，因此 金屬層W及第二金屬層154==金屬層152與第三 貫孔u6且包覆晶請、至少層⑽填充 〆。卩分弟一金屬層152、至少 201205744 Α8ΕΚ2361‘ΝΕ\ν-ΡΪΝΑ[-Τν/-201〇0721 。|^为第一金屬層154及第三金屬層156。 值抑一提的是，在本實施例中，—部分未被防銲層160 所包覆之部分第-金屬層152可構成多個第—接塾172， 而-部分未被_層⑽所包覆之部分第二金屬層154可 構成夕個第—接墊174。這些第—接墊172及這些第二接 塾174適於與-外部電路（例如電路板或另一晶片）電性 連接。因此’可增加本實施例之封裝結構議的應用性。The present invention provides a method of fabricating a package structure for fabricating the package structure described above. The present invention provides a package structure comprising a substrate, a -metal layer, a second metal layer, a third metal layer and a solder resist layer. a base having a sealing surface - a second surface and a second surface and at least one connection: a working surface and a through hole of the two surfaces. The wafer is disposed on the substrate and is disposed on the first surface of the substrate and exposed on the first metal layer, wherein the first metal layer extends onto the wafer. The second metal is disposed on the second surface of the substrate and exposes a portion of the second surface. No. 201205744 ASEK2361-NEW-F1NAL-TW-20I0072] J gold" ^ Covering the inner wall of the hole and connecting the first metal layer and the second metal: the cymbal through the metal layer and the third metal layer and the Filling/hole and covering a small portion of the first metal layer, the second metal layer and the third metal layer of the wafer i. The invention provides a method for fabricating a package structure, which comprises the following steps: Having opposite-first surface and - first opening L right to 〉, a through hole connecting the first surface and the second surface. The first surface on the substrate and exposing a portion of the first surface - : a second conductive layer on the second surface. A wafer is disposed on the exposed portion of the first surface. The patterned-patterned electricity is further formed on the conductive layer, a portion of the second conductive layer, and a portion of the crystal - the metal layer is on the first conductive layer / the first 'electric layer' which is not disposed on the etched electric screen. The metal layer covers the inner wall of the through hole and a part of the first surface exposed by the first conductive layer. As for the wafer, the over metal layer is electrically connected to the first conductive layer and the second conductive layer. And a second conductive layer underneath thereof to expose a portion of the surface of the surface and a portion of the wafer. A solder mask is formed to fill the via hole and to form a wafer and a portion of the metal layer. The system (4), at the same time, can reduce the number of process steps. In order to make the above features and advantages of the present invention more obvious and easy to understand, and in accordance with the formula, the details are as follows (4). </ RTI> 201205744 ASEK2361-NEW-F1NAL-TW-20100721 Figure 1 is a cross-sectional view of a package structure according to an embodiment of the present invention. Referring to Figure 1, in the present embodiment, the package structure 1 includes a base The wafer 140, a first metal layer 152, a second metal layer 154, a second metal layer 56 and a fresh-proof layer 160. Fish-, in a nutshell, the substrate 11 has a first surface opposite to each other. Two surface turns 14 and at least one through hole 116 connecting the first surface 112 and the second surface (only schematically shown in FIG. 1 is a green through hole 116). In one example, the substrate 11G is a dielectric core ( Dide _). and Φ 〇 14〇 is placed on the substrate 110 and bit On the first surface 112, aa&gt;; 14 has a wire surface 142 and a plurality of contacts on the active surface (4). The metal layer (5) is disposed on the first surface 112 of the substrate 11〇 and the second: The surface 112, wherein the first metal layer 152 extends from the first surface/the side of the wafer 14G to the active surface 142 of the wafer (10), and the second metal layer 154 is disposed on the first and second layers of the substrate 110. A portion of the second surface (1) is exposed and exposed. The first metal layer 152 is a Z-based layer 154 having two horizontal conductive patterns and a third conductive layer between the third metal layers 156, J and the two-layer wiring pattern. The first metal layer 152 extends to the wafer 14A. Since the contacts 144 144 on the wafer 140 are present, the metal layer W and the second metal layer 154== the metal layer 152 and the third via hole u6 are coated. At least the layer (10) is filled with ruthenium.卩Different a metal layer 152, at least 201205744 Α8ΕΚ2361 'ΝΕ\ν-ΡΪΝΑ[-Τν/-201〇0721. |^ is the first metal layer 154 and the third metal layer 156. It is to be noted that, in the present embodiment, a portion of the first metal layer 152 not covered by the solder resist layer 160 may constitute a plurality of first vias 172, and a portion may not be formed by the layer (10). The portion of the second metal layer 154 that is coated may constitute a matte pad 174. These first pads 172 and these second contacts 174 are adapted to be electrically connected to an external circuit such as a circuit board or another wafer. Therefore, the applicability of the package structure of the present embodiment can be increased.

一以下將以另一實施例配合圖2 Α至圖21來詳細說明上 述實施例之封裝結構的製作方法。 圖2A至圖21為本發明之另—實施例之一種封裝結構 的製作方法的剖面示意圖。請先參考圖2八，依照本實施例 的封裝結構的製作方法，錢，提供—基板nG，其中基 ，具有彼此相對的一第—表面112與一第二表面 =，且此基板11()上已戦有—細^第―表面ιΐ2上且暴 分第一表面112的第—導電層12G及-位於第二表 面114上的第二導電層13〇。 接著’請參相2B，形成至少—連接基板ιι〇之第 一表面112與第二表面ii4的貫 曰]貝孔116。在本實施例中，Hereinafter, a method of fabricating the package structure of the above embodiment will be described in detail with reference to Fig. 2 to Fig. 21 in another embodiment. 2A through 21 are cross-sectional views showing a method of fabricating a package structure according to another embodiment of the present invention. Referring to FIG. 2, a method for fabricating a package structure according to the present embodiment provides a substrate nG having a first surface 112 and a second surface opposite to each other, and the substrate 11() The first conductive layer 12G on the first surface 112 and the second conductive layer 13 on the second surface 114 are already on the surface. Next, please refer to phase 2B to form at least a through hole 116 of the first surface 112 and the second surface ii4 of the substrate ι. In this embodiment,

Si 例如是機械式鑽孔法，但在此並不以 接著^請參考圖％，配置—晶片14〇於第一導電層 所暴^备出之基板11 〇的部分帛± ^ u 施例中，晶片uo星有一主動面刀^表夕面112上。在本實 上的接點144。/、 心2與夕個位於主動面142 201205744 ASEK2361 -NE W-FIN AL-TV/-20100721 接著，請參考圖2D，形成—雷# 導=2°、第-導電層13。所暴露出W表=第; 二導電層13〇、貫孔116内壁及晶片14〇上。 弟 接著，請參考圖犯，形成一電鍍罩幕⑽於電 =播ΪΓ輯19(3並未覆蓋位於貫孔J内: 上的電鐘種子層180。 接著，請參考圖2F，圖案化電錄罩幕19〇，以 = 2中圖案化電購192位於部分 第V電層120上方之電鐘種子層18〇上、部分第 層130上方之電鑛種子層18〇上及晶片14〇之部分= 142上方之電鑛種子層⑽上。在本實施例中，圖案化電 链^幕192可糟由形成光阻層並對光阻層曝光及顯影來加 以製作。 、接著’請參考圖2G，以圖案化電鐘罩幕190為罩幕 來進仃-電㈣程，崎未配置圖案化電鮮幕且 應第-導電層U0與第二導電層13G的電鑛種子層18〇上 形成一金屬層。 卜在本實施例之中，金屬層包括一第一金屬層152、— 第二金屬層154及一第三金屬層156。詳細來說，第一金 屬層152配置於基板110之第一表面112上方的電鍵種子 層180上’第一金屬層154配置於基板no之第二表面114 上方的電鍍種子層180上，而第三金屬層156覆蓋貫孔1]6 内壁上的電鍍種子層18〇，且連接第—金屬層152與第二 金屬層154。特別是，在本實施例中，第一金屬層152從 201205744 ASEK2361 -NEW-FINAL-T W-20100721 第-表面112經由晶片140的—側延伸至於晶片i4〇之主 動面142的這些接墊144上方的電鐘種子層18〇，且晶片 140上的這些接墊144可透過第一金屬層152與第三 層156及第二金屬層154電性連接。 然後，請參考圖2H，移除圖案化電鍍罩幕192及其 下方之部分電鑛種子層180,以暴露出部分第一表面&amp; 及晶片140的部分主動面142。再次必須說明的是，移除 φ 圖案化電鍵罩幕I92及其下方之第一導電層120與第二導 電層130的方法例如是剝離法（stdpping)，而移除電鍍 種子層180的方法例如是快速蝕刻法（❿也etching )。 接著，請同樣參考圖2H，當最初即採用第一導電層 120及第二導電層13〇時，在移除圖案化電鍍罩幕192及 其下方之部分電鍍種子層18〇以後，再圖案化第一導電層 U0及第二導電層130,以暴露出部分第一表面112及部&amp; 第二表面114。圖案化第一導電層12〇及第二導電層13〇 的方法可藉由钮刻罩幕配合钱刻來達成，其中蝕刻罩幕例 • 如是圖案化光阻。 表後’請參考圖21，形成一防銲層160以填充貫孔ία 且包覆晶片140、至少部分第一金屬層152、至少部分第二 金屬層154及第三金屬層156。至此，已大致完成封裝結 構100a的製作。 值得一提的是，在本實施例中，一部分未被防銲層160 所包覆之第一金屬層152及其下方之部分第一導電層12〇 可構成多個第一接墊172，而一部分未被防銲層160所包 201205744 AStK23&amp; 1 -NE W-FINAL-T W-20100721 覆之第二金屬層154及其下方之部分第二導電&gt; 成多個第二接墊174。這些第—接墊172 θ 174可與外部電路（例如電路板、 ς弟—接墊 構）電性連接。 # ^或另―封裝結 f 於本實施例是在基板UG上進行線路（例 如疋第-金屬層152、第二金屬層154、第三金屬芦 4作時，同時進行晶片刚的封裝製程。如此—來日，可以 :咸 100的製程步驟。此外，由於這些第-接墊 一曰乂二弟—接墊174可與外部電路（例如電路板、另 封|結構）電性連接，因此可增加本實施例 之封裝、.告構l〇〇a的應用性。 雖然本發明已以實施例揭露如上，然其並非用以限定 :月任何所屬技術領域中具有通常知識者，在不脫離 明之精神和範圍内，當可作些許之更動與潤飾，故本 χ之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖 圖1是本發明之一實施例之一種封裝結構的剖面示意 圖2Α 的制你士至圖21為本發明之另—實施例之—種封裝結構 衣作方法的剖面示意圖。 201205744 ASEK23 61 -NEW-FINAL-TW-20100721 【主要元件符號說明】 100、100a :封裝結構 110 :基板 112 :第一表面 114 :第二表面 116 :貫孔 120 :第一導電層 130 :第二導電層 ® 140 :晶片 142 :主動面 144 :接點 152 :第一金屬層 154 :第二金屬層 156 :第三金屬層 160 :防銲層 172 :第一接墊 • 174:第二接墊 180 :電鍍種子層 190 :電鍍罩幕 192 :圖案化電鍍罩幕For example, the Si is a mechanical drilling method, but the portion of the substrate 11 that is prepared by the first conductive layer is not included in the example. The wafer uo star has an active surface knife ^ on the eve 112. In this actual contact 144. /, heart 2 and eve are located on the active surface 142 201205744 ASEK2361 -NE W-FIN AL-TV/-20100721 Next, referring to FIG. 2D, a light-guide layer is formed. The exposed W table = the second; the second conductive layer 13 〇, the inner wall of the through hole 116 and the wafer 14 〇. After the brother, please refer to the figure to form a plating mask (10) in the electricity = broadcast series 19 (3 does not cover the electric clock seed layer 180 located in the through hole J: Next, please refer to Figure 2F, patterned electricity The mask is 19 〇, and the patterned electric 192 is located on the electric clock seed layer 18 上方 above the partial V electric layer 120, the electric mineral seed layer 18 上方 above the partial first layer 130, and the wafer 14 Part = 142 above the electric ore seed layer (10). In this embodiment, the patterned electric chain curtain 192 can be made by forming a photoresist layer and exposing and developing the photoresist layer. 2G, with the patterned electric clock cover 190 as a mask to enter the electric-electric (four) process, the electric current seed layer 18 of the first conductive layer U0 and the second conductive layer 13G is not disposed on the patterned electric curtain. A metal layer is formed. In the embodiment, the metal layer includes a first metal layer 152, a second metal layer 154, and a third metal layer 156. In detail, the first metal layer 152 is disposed on the substrate 110. The first metal layer 154 is disposed over the second surface 114 of the substrate no on the key seed layer 180 above the first surface 112. The seed layer 180 is plated, and the third metal layer 156 covers the plating seed layer 18〇 on the inner wall of the through hole 1]6, and connects the first metal layer 152 and the second metal layer 154. In particular, in this embodiment, The first metal layer 152 extends from the 201205744 ASEK2361 -NEW-FINAL-T W-20100721 first surface 112 through the side of the wafer 140 to the clock seed layer 18A above the pads 144 of the active surface 142 of the wafer i4, The pads 144 on the wafer 140 can be electrically connected to the third layer 156 and the second metal layer 154 through the first metal layer 152. Then, referring to FIG. 2H, the patterned plating mask 192 and the underside thereof are removed. Part of the electric ore seed layer 180 to expose a portion of the first surface &amp; and a portion of the active surface 142 of the wafer 140. Again, the φ patterned bond mask I92 and the underlying first conductive layer 120 are removed The method of the second conductive layer 130 is, for example, a stdpping method, and the method of removing the plating seed layer 180 is, for example, a rapid etching method. Next, please refer to FIG. 2H as well, when the first conductive is used first. When the layer 120 and the second conductive layer 13 are ,, moving After patterning the plating mask 192 and a portion of the plating seed layer 18 below it, the first conductive layer U0 and the second conductive layer 130 are patterned to expose a portion of the first surface 112 and the portion &amp; second surface 114. The method of patterning the first conductive layer 12A and the second conductive layer 13A can be achieved by using a button mask and a mask, wherein the etching mask is as follows: • Patterned photoresist. After the table, please refer to FIG. A solder mask layer 160 is formed to fill the vias ία and to cover the wafer 140, at least a portion of the first metal layer 152, at least a portion of the second metal layer 154, and the third metal layer 156. So far, the fabrication of the package structure 100a has been substantially completed. It should be noted that, in this embodiment, a portion of the first metal layer 152 not covered by the solder resist layer 160 and a portion of the first conductive layer 12 下方 below thereof may constitute a plurality of first pads 172, and A portion of the second metal layer 154 covered by the solder resist layer 160 is not covered by the solder mask layer 201205744 AStK23 &amp; 1 -NE W-FINAL-T W-20100721 and a portion of the second conductive layer hereinafter is formed into a plurality of second pads 174. These first pads 172 θ 174 can be electrically connected to external circuits (e.g., circuit boards, sturdy pads). In the present embodiment, the wiring is performed on the substrate UG (for example, the first metal layer 152, the second metal layer 154, and the third metal reed 4), and the wafer packaging process is simultaneously performed. So - in the coming days, you can: the process steps of salty 100. In addition, since these first pads - two pads - the pads 174 can be electrically connected to external circuits (such as circuit boards, other seals | structures), The applicability of the package and the structure of the present embodiment is increased. Although the present invention has been disclosed in the above embodiments, it is not intended to be limited: any person having ordinary knowledge in the technical field of the month, without departing from the disclosure In the spirit and scope, when a few changes and refinements can be made, the scope of protection of this section is subject to the definition of the patent application scope. [FIG. 1 is an embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 21 is a cross-sectional view showing a method of fabricating a package structure according to another embodiment of the present invention. 201205744 ASEK23 61 -NEW-FINAL-TW-20100721 [Main component symbol Description 100, 100a: package structure 110: substrate 112: first surface 114: second surface 116: through hole 120: first conductive layer 130: second conductive layer® 140: wafer 142: active surface 144: contact 152: A metal layer 154: a second metal layer 156: a third metal layer 160: a solder resist layer 172: a first pad • 174: a second pad 180: a plating seed layer 190: a plating mask 192: a patterned plating mask

Claims (1)

201205744 ASJtJC：ii6 l-NEW-FINAL-TW-20100721 七、申請專利範圍： 1. 一種封裝結構，包括： 一基板，具有彼此相對的一第一表面與一第二表面及 至少一連接該第一表面與該第二表面的貫孔； 一晶片，配置於該基板上且位於該第一表面上； 一第一金屬層，配置於該基板的該第一表面，上且暴露 出部分該第一表面，其中該第一金屬層延伸至該晶片上； 一第一金屬層，配置於該基板的該第二表面上且暴露 出部分該第二表面； 馨 一第三金屬層，覆蓋該貫孔的内壁且連接該第一金屬 層與該第二金屬層’其中該晶片透過該第一金屬層與該第 三金屬層及該第二金屬層電性連接；以及 一防鮮層，填充該貫孔且包覆該晶片、至少部分該第 一金屬層、至少部分該第二金屬層及該第三金屬層。^ 2. 如申請專利範圍第.1項所述之封裝結構，其中該晶 片具有一主動面與多個位於該主動面上的接點，^第一= 屬^延伸至該射H，且該祕料觸第—金屬層肖 · 該第三金屬層與該第二金屬層電性連接。 〃 3. 如申請專利範圍第2項所述之封裝結構，其中該第 一金屬層從該第一表面經由該晶片的—側延伸至該主動 面0 4·如申請專利範圍第1項所述之封裝結構，其中部分 未被該防銲層所包覆的該第一金屬層構成至少二第一接 墊0 12 201205744 ASEK2361 -NE W-F1NAL-TW-20100721 5.如申請專利範圍第1項所述之封I _ 未被該防銲層所包覆的該第二金屬層 °構’ 塾。 構成至少 其中 —第 部分 —接 6. —種封裝結構的製作方法，包括. 提供一基板，該基板具有彼此相對的—第— 第二表面及至少-連接該第一表面與該第二表：的 其中該基板上已形成有-位於該第一表面上且暴露出部分 該第一表面的第一導電層及一位於該第二表面上的第 電層； 、 配置-晶片於該第—導電層所暴露出的部分該第一 表面上； 形土-圖案化電鍍罩幕於部分該第一導電層上、部分 該第一導電層上及部分該晶片上； —金屬層於未配置該®案化電鑛罩幕的該第-層上’其中該金屬層覆蓋該貫孔的内 ;延;暴露出的部分該第-表面上，該金屬 電層及該第；=電片透過該金屬層與該第-導 暴露，第二導電層，以 以及 4刀該弟二表面及部分該晶片； 分該Γί層晴層，轉_貫孔且包覆該^及至少部 申明專利|巳圍第6項所述之封裝結構的製作方 i3 201205744 八 aiiKZJO hNEW-FINAL-TW-20100721 法，更包括： -矣^ ^該第—導電層所4露出的部分該第 二:成一電鍍種子層於該第1電層、該第 内===出的該第一表面、該第二導電層、該貫孔 法，=請專利範圍第6項所述之封裳結構的製作方 在移除該圖案化電鮮幕及其下 之後’進行-蝕刻製程，以移除位於該了;暮； 方的該電鑛種子層。 Μ茶化電鑛罩幕下 =如申請專概㈣6項所述之封裝結構的製作方 法二中形成該圖案化電鑛罩幕的步驟，包括： 露出:ίί電f罩幕於該第—導電層、該第-導電層所暴 面、該第二導電層及該日日日片上；以及 圖案㈣電鮮幕以形成該圖案化電錢罩幕。 法，範圍第6項所述之封農結構的製作方 :、中忒曰曰片具有一主動面與多個位於該主動面上 i盘=屬f延伸至該些接點上’且該些接點透過該金屬 白^第一‘電層與該第二導電層電性連接。 金屬二咖第1G項所述之封裝結構，其情 、1曰2 : ί:ί面;蝴晶片的一側延伸至該主動面。 .13申5月專利範圍第6項所述之封裝結構的制你士 邻2Γ部分未被該防録層所包覆之該金屬層。及^方之 部分該第-導電層構成至少—第―接塾。4其下方之 14 201205744 ASEK23 61 -NE W-FTNAL-T W-20100721 13.如申請專利範圍第6項所述之封裝結構的製作方 法，其中部分未被該防銲層所包覆之該金屬層及其下方之 部分該第二導電層構成至少一第二接墊。201205744 ASJtJC: ii6 l-NEW-FINAL-TW-20100721 7. Patent application scope: 1. A package structure comprising: a substrate having a first surface and a second surface opposite to each other and at least one of the first a through hole of the surface and the second surface; a wafer disposed on the substrate and located on the first surface; a first metal layer disposed on the first surface of the substrate, and exposing a portion of the first a surface, wherein the first metal layer extends onto the wafer; a first metal layer disposed on the second surface of the substrate and exposing a portion of the second surface; a third metal layer covering the through hole The inner wall is connected to the first metal layer and the second metal layer 'where the wafer is electrically connected to the third metal layer and the second metal layer through the first metal layer; and a fresh-proof layer is filled And coating the wafer, at least a portion of the first metal layer, at least a portion of the second metal layer, and the third metal layer. 2. The package structure of claim 1, wherein the wafer has an active surface and a plurality of contacts on the active surface, and the first = the extension extends to the shot H, and the The secret material touches the metal layer. The third metal layer is electrically connected to the second metal layer. 3. The package structure of claim 2, wherein the first metal layer extends from the first surface to the active surface via the side of the wafer. The package structure, wherein the first metal layer not covered by the solder resist layer constitutes at least two first pads 0 12 201205744 ASEK2361 -NE W-F1NAL-TW-20100721 5. As claimed in claim 1 The seal I _ is not configured by the second metal layer covered by the solder resist layer. The method of fabricating at least the first portion - the sixth package structure comprises: providing a substrate having a first surface opposite to each other and at least - connecting the first surface to the second surface: The first conductive layer on the first surface and exposing a portion of the first surface and a first electrical layer on the second surface are formed on the substrate; and the wafer is disposed on the first conductive layer a portion of the first surface exposed by the layer; a shaped earth-patterned plating mask on a portion of the first conductive layer, a portion of the first conductive layer, and a portion of the wafer; - the metal layer is not disposed On the first layer of the electric ore mask, wherein the metal layer covers the inside of the through hole; the exposed portion of the first surface, the metal layer and the first; The layer is exposed to the first conductive layer, the second conductive layer, and the surface of the second surface of the wafer and the portion of the wafer; the layer of the layer is separated from the layer, and the layer is covered and covered with at least a portion of the patent | The manufacturer of the package structure described in item 6 i3 201205744 The eight aiiKZJO hNEW-FINAL-TW-20100721 method further includes: - 矣 ^ ^ the first portion of the conductive layer 4 exposed; the second: forming a plating seed layer on the first electrical layer, the first === The first surface, the second conductive layer, and the through hole method, the manufacturer of the sealing structure described in claim 6 of the patent scope, after performing the etching and etching The process is to remove the seed layer of the electric ore located at the side; Μ茶化电矿罩下幕====================================================================================================== The surface of the first conductive layer, the second conductive layer and the day and the day; and the pattern (4) of the electric screen to form the patterned money cover. Method, the producer of the agricultural closure structure described in the sixth item: the middle cymbal has an active surface and a plurality of active disks on the active surface, the genus f extends to the contacts, and the The contact is electrically connected to the second conductive layer through the metal white first electric layer. The package structure described in Item 1G of the Metallic Coffee, 1 2: ί: 面; one side of the wafer extends to the active surface. .13 The metal structure of the encapsulation structure of the package structure described in item 6 of the May patent scope is not covered by the anti-recording layer. And the portion of the first conductive layer constitutes at least the first - first junction. 4 hereinafter, 14 201205744 ASEK23 61 -NE W-FTNAL-T W-20100721 13. The method of manufacturing the package structure according to claim 6, wherein the metal is not covered by the solder resist layer The layer and a portion thereof below the second conductive layer constitute at least one second pad. 1515
TW099124010A 2010-07-21 2010-07-21 Package structure and manufacturing method thereof TWI400783B (en)

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Cited By (2)

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TWI485861B (en) * 2013-01-04 2015-05-21 Jung Chi Hsien Rectifier diode structure
TWI496243B (en) * 2012-05-29 2015-08-11 Tripod Technology Corp Method for fabricating embedded component semiconductor package

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6495394B1 (en) * 1999-02-16 2002-12-17 Sumitomo Metal (Smi) Electronics Devices Inc. Chip package and method for manufacturing the same
JP3813402B2 (en) * 2000-01-31 2006-08-23 新光電気工業株式会社 Manufacturing method of semiconductor device
JP2003289073A (en) * 2002-01-22 2003-10-10 Canon Inc Semiconductor device and method of manufacturing semiconductor device
US6506632B1 (en) * 2002-02-15 2003-01-14 Unimicron Technology Corp. Method of forming IC package having downward-facing chip cavity
KR100601493B1 (en) * 2004-12-30 2006-07-18 삼성전기주식회사 BGA package having a bonding pad become half etching and cut plating gold lines and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI496243B (en) * 2012-05-29 2015-08-11 Tripod Technology Corp Method for fabricating embedded component semiconductor package
TWI485861B (en) * 2013-01-04 2015-05-21 Jung Chi Hsien Rectifier diode structure

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