TWI510155B - Semiconductor package structure and method for fabricating the same - Google Patents

Semiconductor package structure and method for fabricating the same Download PDF

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Publication number
TWI510155B
TWI510155B TW100114430A TW100114430A TWI510155B TW I510155 B TWI510155 B TW I510155B TW 100114430 A TW100114430 A TW 100114430A TW 100114430 A TW100114430 A TW 100114430A TW I510155 B TWI510155 B TW I510155B
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Taiwan
Prior art keywords
wafer
semiconductor package
substrate
conductive trace
package structure
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TW100114430A
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Chinese (zh)
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TW201244572A (en
Inventor
En Min Jow
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Adl Engineering Inc
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Publication date
Application filed by Adl Engineering Inc filed Critical Adl Engineering Inc
Priority to TW100114430A priority Critical patent/TWI510155B/en
Priority to CN201110158996.5A priority patent/CN102760665B/en
Publication of TW201244572A publication Critical patent/TW201244572A/en
Application granted granted Critical
Publication of TWI510155B publication Critical patent/TWI510155B/en

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Description

半導體封裝結構及其製造方法Semiconductor package structure and method of manufacturing same

本發明係有關一種半導體封裝技術，特別是一種半導體封裝結構及其製造方法。The present invention relates to a semiconductor package technology, and more particularly to a semiconductor package structure and a method of fabricating the same.

於半導體封裝製程中，由於電子產品需求朝向高功能化、訊號傳輸高速化及電路元件高密度化發展，且電子產品不斷強調輕薄短小，使得封裝密度隨之不斷提高，亦不斷縮小封裝尺寸與改良封裝技術。如何於有限的封裝空間中容納數目龐大的電子元件一直是此技術領域相當重要之課題。In the semiconductor packaging process, as the demand for electronic products is becoming more highly functional, the signal transmission is speeding up, and the circuit components are becoming more dense, and the electronic products continue to emphasize lightness and thinness, the package density is continuously increased, and the package size and improvement are continuously reduced. Packaging technology. How to accommodate a large number of electronic components in a limited package space has been a very important issue in this technical field.

本發明目的之一係提供一種半導體封裝結構及其製造方法，利用多晶片先堆疊封裝再與重新佈線層結合，其中舉例而言下層晶片之主動面係朝下直接與重新佈線層電性連接，而上層晶片係透過設置於下層晶片周圍之導電跡線與重新佈線層電性連接。One of the objectives of the present invention is to provide a semiconductor package structure and a method of fabricating the same, which utilizes a multi-wafer first stacked package and then a rewiring layer, wherein, for example, the active surface of the lower wafer is directly electrically connected to the rewiring layer downward. The upper wafer is electrically connected to the rewiring layer through conductive traces disposed around the lower wafer.

本發明目的之一係提供一種半導體封裝結構之製造方法，係包括下列步驟：提供一基板；形成一導電跡線於基板上，其中導電跡線係環繞於一第一晶片承載區域之周圍；設置一第一晶片於基板之第一晶片承載區域上，其中第一晶片之主動面係朝下與基板接觸；設置一第二晶片於第一晶片之上方並與導電跡線電性連接；形成一封裝膠體覆蓋第一晶片、第二晶片、導電跡線與基板之上表面；移除基板，其中封裝膠體之下表面係暴露出導電跡線之下表面與第一晶片之 主動面；設置一重新佈線層(redistribution layer)於封裝膠體之下表面，其中第一晶片與導電跡線係分別與重新佈線層電性連接；以及設置多個導電焊球於重新佈線層之下表面並與重新佈線層電性連接。One object of the present invention is to provide a method of fabricating a semiconductor package structure comprising the steps of: providing a substrate; forming a conductive trace on the substrate, wherein the conductive trace is wrapped around a first wafer carrying area; a first wafer is disposed on the first wafer carrying region of the substrate, wherein the active surface of the first wafer is in contact with the substrate facing downward; a second wafer is disposed above the first wafer and electrically connected to the conductive trace; forming a The encapsulant covers the first wafer, the second wafer, the conductive traces and the upper surface of the substrate; and the substrate is removed, wherein the surface under the encapsulant exposes the lower surface of the conductive trace and the first wafer An active surface; a redistribution layer is disposed on the lower surface of the encapsulant, wherein the first wafer and the conductive trace are respectively electrically connected to the rewiring layer; and the plurality of conductive solder balls are disposed under the rewiring layer The surface is electrically connected to the rewiring layer.

本發明目的之一係提供一種半導體封裝結構，係包括：一多晶片堆疊結構，包含：一第一晶片；一導電跡線設置於第一晶片周圍；一第二晶片，係設置於第一晶片之上方並與導電跡線電性連接；以及一封裝膠體覆蓋第一晶片、第二晶片與導電跡線，並使多晶片堆疊結構的下表面露出導電跡線的下表面與第一晶片的下表面；一重新佈線層設置於該多晶片堆疊結構的下表面，並與導電跡線的下表面及第一晶片電性連接；以及多個導電焊球，係設置於重新佈線層之下表面並與重新佈線層電性連接。An object of the present invention is to provide a semiconductor package structure comprising: a multi-wafer stack structure comprising: a first wafer; a conductive trace disposed around the first wafer; and a second wafer disposed on the first wafer Above and electrically connected to the conductive traces; and an encapsulant covering the first wafer, the second wafer and the conductive traces, and the lower surface of the multi-wafer stack is exposed to the lower surface of the conductive trace and the lower surface of the first wafer a surface; a rewiring layer disposed on the lower surface of the multi-wafer stack structure and electrically connected to the lower surface of the conductive trace and the first wafer; and a plurality of conductive solder balls disposed on the lower surface of the rewiring layer and Electrically connected to the rewiring layer.

以下藉由具體實施例配合所附的圖式詳加說明，當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。The purpose, technical contents, features, and effects achieved by the present invention will become more apparent from the detailed description of the appended claims.

其詳細說明如下，所述較佳實施例僅做一說明非用以限定本發明。The detailed description is as follows, and the preferred embodiment is not intended to limit the invention.

圖1A至圖1G為本發明一實施例之半導體封裝結構之製造方法的結構剖面示意圖。於本實施例中，半導體封裝結構之製造方法包括下列步驟。請參考圖1A，首先，提供一基板110。之後，如圖1B所示，於基板110上形成一導電跡線(conductive trace)120。此基板110之材質可為絕緣材料。1A to 1G are schematic cross-sectional views showing the structure of a method of fabricating a semiconductor package structure according to an embodiment of the present invention. In the present embodiment, the method of fabricating the semiconductor package structure includes the following steps. Referring to FIG. 1A, first, a substrate 110 is provided. Thereafter, as shown in FIG. 1B, a conductive trace 120 is formed on the substrate 110. The material of the substrate 110 may be an insulating material.

接續上述說明，此導電跡線120可利用電鍍、蝕刻或轉印方式所製成。此外，導電跡線120係環繞設置於基板110上之一第一晶片承載區域112之周圍。接著，請參照圖1C， 將一第一晶片130設置於基板110之第一晶片承載區域112上。特別的是，第一晶片130之下表面係朝下與基板110接觸，於一實施例中第一晶片130係主動面朝下與基板110接觸。Following the above description, the conductive traces 120 can be formed by electroplating, etching or transfer. In addition, the conductive traces 120 are disposed around one of the first wafer carrying regions 112 on the substrate 110. Next, please refer to FIG. 1C. A first wafer 130 is disposed on the first wafer carrying region 112 of the substrate 110. In particular, the lower surface of the first wafer 130 is in contact with the substrate 110 facing downwards. In one embodiment, the first wafer 130 is in active contact with the substrate 110.

接著，請參照圖1D，設置一第二晶片132於第一晶片130上方並與導電跡線120電性連接。於本實施例中，第二晶片132之主動面係朝上疊置於第一晶片130上並以打線方式利用多條導線(圖上未標)與導電跡線120電性連接。第一晶片130與第二晶片132間可利用黏著層(圖上未標)加以黏著固定。Next, referring to FIG. 1D , a second wafer 132 is disposed above the first wafer 130 and electrically connected to the conductive traces 120 . In this embodiment, the active surface of the second wafer 132 is stacked on the first wafer 130 and electrically connected to the conductive traces 120 by wire bonding (not labeled). The first wafer 130 and the second wafer 132 can be adhered and fixed by an adhesive layer (not shown).

請繼續參照圖1E，形成一封裝膠體140覆蓋第一晶片130、第二晶片132、導電跡線120以及基板110之上表面。之後，於本實施例中，設置一支撐基材150於封裝膠體140之上表面。於圖1A至圖1I所揭露為使用支撐基材150的實施例。可理解的是，於一實施例中，可省略支撐基材的使用。Referring to FIG. 1E, an encapsulant 140 is formed to cover the first wafer 130, the second wafer 132, the conductive traces 120, and the upper surface of the substrate 110. Thereafter, in the embodiment, a supporting substrate 150 is disposed on the upper surface of the encapsulant 140. An embodiment using a support substrate 150 is disclosed in FIGS. 1A-1I. It will be appreciated that in one embodiment, the use of a support substrate may be omitted.

接著，移除基板110，如圖1F所示。於封裝膠體140之下表面係暴露出導電跡線120之下表面與第一晶片130之下表面(於一實施例中，第一晶片130的下表面係為主動面)。請參照圖1G，設置一重新佈線層160(redistribution layer，RDL)於封裝膠體140之下表面。第一晶片130與導電跡線120係分別與重新佈線層160電性連接。之後，如圖1G所示，設置多個導電焊球170於重新佈線層160之下表面並與其電性連接。Next, the substrate 110 is removed, as shown in FIG. 1F. The lower surface of the conductive trace 120 and the lower surface of the first wafer 130 are exposed on the lower surface of the encapsulant 140 (in one embodiment, the lower surface of the first wafer 130 is an active surface). Referring to FIG. 1G, a redistribution layer (RDL) 160 is disposed on the lower surface of the encapsulant 140. The first wafer 130 and the conductive traces 120 are electrically connected to the rewiring layer 160, respectively. Thereafter, as shown in FIG. 1G, a plurality of conductive solder balls 170 are disposed on and electrically connected to the lower surface of the rewiring layer 160.

於不同實施例中，如圖2A與圖2B所示，第二晶片132可有不同的設置方式，例如可將第二晶片132之主動面朝下並以覆晶(flip-chip)方式與導電跡線120電性連接。其中，第二晶片132可利用一黏著層(圖上未標)疊置於第一晶片130 上，如圖2B所示，或第二晶片132懸空疊置於第一晶片130上方，如圖2A所示。第二晶片132可利用導電焊球172或凸塊(bump)與導電跡線120電性連接。In different embodiments, as shown in FIG. 2A and FIG. 2B, the second wafer 132 may have different arrangements, for example, the active surface of the second wafer 132 may face downward and be flip-chip and electrically conductive. The traces 120 are electrically connected. The second wafer 132 can be stacked on the first wafer 130 by using an adhesive layer (not labeled). Above, as shown in FIG. 2B, or the second wafer 132 is suspended over the first wafer 130, as shown in FIG. 2A. The second wafer 132 can be electrically connected to the conductive traces 120 using conductive solder balls 172 or bumps.

請參照圖3A，於一實施例中，本發明製造方法更包括提供一載具100用以承載基板110。基板110則設置於載具100上供後續製程使用，如圖3A至圖3G所示。此載具100可為一玻璃基板。基板110可為塑膠材質或是具可撓性(flexible)的板材，有助於晶片封裝完成後之移除作業。Referring to FIG. 3A, in an embodiment, the manufacturing method of the present invention further includes providing a carrier 100 for carrying the substrate 110. The substrate 110 is disposed on the carrier 100 for subsequent processing, as shown in FIGS. 3A to 3G. The carrier 100 can be a glass substrate. The substrate 110 can be made of a plastic material or a flexible sheet material to facilitate removal after the wafer package is completed.

於一實施例中，請參照圖3A至圖3F，形成導電跡線120包括下列步驟。於本實施例中，係採用電鍍方式製作導電跡線120。首先，如圖3B所示，形成一金屬層120'於基板110上。此金屬層120'可利用金屬氣相沉積製作或是此金屬層120'可為一金屬薄膜並以壓合方式設置於基板110上。除單層結構之外，金屬層120'亦可為複合膜層。接著，形成一第一圖案化光阻層122'於金屬層120'上用以定義出導電跡線120之圖案。之後，電鍍形成導電跡線120於金屬層120'上。In one embodiment, referring to FIGS. 3A-3F, forming conductive traces 120 includes the following steps. In the present embodiment, the conductive traces 120 are formed by electroplating. First, as shown in FIG. 3B, a metal layer 120' is formed on the substrate 110. The metal layer 120' may be formed by metal vapor deposition or the metal layer 120' may be a metal film and disposed on the substrate 110 in a press-fit manner. In addition to the single layer structure, the metal layer 120' may also be a composite film layer. Next, a first patterned photoresist layer 122' is formed on the metal layer 120' to define a pattern of conductive traces 120. Thereafter, electroplating forms conductive traces 120 on metal layer 120'.

於一實施例中，如圖3C所示，在電鍍形成導電跡線120後，可直接移除第一圖案化光阻層122'以及進一步移除於第一晶片承載區域112上之金屬層120'至暴露出基板110之上表面。可以理解的是，除導電跡線120下方之金屬層120’外，其餘金屬層120’在不影響電性下可選擇性移除至暴露出基板110之上表面。In one embodiment, as shown in FIG. 3C, after the conductive traces 120 are formed by electroplating, the first patterned photoresist layer 122' and the metal layer 120 further removed on the first wafer carrying region 112 may be directly removed. 'To expose the upper surface of the substrate 110. It can be understood that, except for the metal layer 120' under the conductive traces 120, the remaining metal layers 120' can be selectively removed to expose the upper surface of the substrate 110 without affecting electrical properties.

於另一實施例中，請參照圖3D至圖3F，在形成導電跡線120後與移除第一圖案化光阻層122'前，可進一步於導電跡線120之多個導電接點126'上形成一金屬最終表面處理層122。首先，形成一第二圖案化光阻層124'於第一圖案化光阻層122'與導電跡線120上。第二圖案化光阻層124'係暴露出 導電跡線120之多個導電接點126'且導電接點126'係用以讓導電跡線120與第二晶片132(如圖1E所示)電性連接。In another embodiment, referring to FIG. 3D to FIG. 3F, after forming the conductive traces 120 and before removing the first patterned photoresist layer 122', the conductive traces 126 of the conductive traces 120 may be further A metal final surface treatment layer 122 is formed thereon. First, a second patterned photoresist layer 124' is formed on the first patterned photoresist layer 122' and the conductive traces 120. The second patterned photoresist layer 124' is exposed The plurality of conductive contacts 126' of the conductive traces 120 and the conductive contacts 126' are used to electrically connect the conductive traces 120 to the second wafer 132 (shown in FIG. 1E).

接著，如圖3D與圖3E所示，於導電跡線120之導電接點126'上形成一金屬最終表面處理層122。此金屬最終表面處理層122可有助於第二晶片132(如圖1E所示)與導電跡線120之電性連接，如圖3G所示。繼續，同時移除第一圖案化光阻層122'與第二圖案化光阻層124'。之後，移除於第一晶片承載區域112上之金屬層120'至暴露出基板110之上表面。除導電跡線120下方之金屬層120’外，其餘金屬層120’在不影響電性下可選擇性移除至暴露出基板110之上表面。移除金屬層120’可藉由蝕刻方式，利用金屬最終表面處理層122為遮罩來蝕刻移除基板110之上表面的金屬層120’。可以理解的是，移除金屬層120’同時亦會移除掉部分導電跡線120，圖上並未顯示。Next, as shown in FIG. 3D and FIG. 3E, a metal final surface treatment layer 122 is formed on the conductive contacts 126' of the conductive traces 120. The metal final surface treatment layer 122 can facilitate electrical connection of the second wafer 132 (shown in FIG. 1E) to the conductive traces 120, as shown in FIG. 3G. Continuing, the first patterned photoresist layer 122' and the second patterned photoresist layer 124' are simultaneously removed. Thereafter, the metal layer 120' on the first wafer carrying region 112 is removed to expose the upper surface of the substrate 110. Except for the metal layer 120' under the conductive traces 120, the remaining metal layers 120' are selectively removed to expose the upper surface of the substrate 110 without affecting electrical properties. The removal of the metal layer 120' can etch the metal layer 120' that removes the upper surface of the substrate 110 by etching using the metal final surface treatment layer 122 as a mask. It will be appreciated that removal of the metal layer 120' also removes portions of the conductive traces 120, which are not shown.

繼續參照圖3G、圖3H與圖3I，將一第一晶片130設置於基板110之第一晶片承載區域112上。特別的是，第一晶片130之下表面係朝下與基板110接觸，而導電跡線120係環繞設置於基板110上之一第一晶片承載區域112之周圍，於一實施例中，第一晶片130的下表面為第一晶片130的主動面。With continued reference to FIGS. 3G, 3H, and 3I, a first wafer 130 is disposed on the first wafer carrying region 112 of the substrate 110. In particular, the lower surface of the first wafer 130 is in contact with the substrate 110 facing downward, and the conductive traces 120 are disposed around one of the first wafer carrying regions 112 on the substrate 110. In an embodiment, the first The lower surface of the wafer 130 is the active surface of the first wafer 130.

接著，設置一第二晶片132於第一晶片130上方並與導電跡線120電性連接。於本實施例中，第二晶片132之主動面係朝上疊置於第一晶片130上並以打線方式利用多條導線(圖上未標)與導電跡線120電性連接。第一晶片130與第二晶片132間可利用黏著層(圖上未標)加以黏著固定。繼續，形成一封裝膠體140覆蓋第一晶片130、第二晶片132、導電跡線120以及基板110之上表面。之後，設置一支撐基材150於封裝膠體140之上表面，如圖3G所示。Next, a second wafer 132 is disposed above the first wafer 130 and electrically connected to the conductive traces 120. In this embodiment, the active surface of the second wafer 132 is stacked on the first wafer 130 and electrically connected to the conductive traces 120 by wire bonding (not labeled). The first wafer 130 and the second wafer 132 can be adhered and fixed by an adhesive layer (not shown). Continuing, an encapsulant 140 is formed overlying the first wafer 130, the second wafer 132, the conductive traces 120, and the upper surface of the substrate 110. Thereafter, a support substrate 150 is disposed on the upper surface of the encapsulant 140 as shown in FIG. 3G.

接著，移除載具100與基板110，如圖3H所示。於封裝膠體140之下表面係暴露出導電跡線120之下表面與第一晶片130之下表面。請參照圖3I，設置一重新佈線層160於封裝膠體140之下表面。第一晶片130與導電跡線120係分別與重新佈線層160電性連接。之後，設置多個導電焊球170於重新佈線層160之下表面並與其電性連接。Next, the carrier 100 and the substrate 110 are removed, as shown in FIG. 3H. The lower surface of the conductive trace 120 and the lower surface of the first wafer 130 are exposed on the lower surface of the encapsulant 140. Referring to FIG. 3I, a rewiring layer 160 is disposed on the lower surface of the encapsulant 140. The first wafer 130 and the conductive traces 120 are electrically connected to the rewiring layer 160, respectively. Thereafter, a plurality of conductive solder balls 170 are disposed on and electrically connected to the lower surface of the rewiring layer 160.

於上述實施例中，支撐基材150除了可作為移除基板110或載具100時之支撐外，支撐基材150可依需要保留或進行移除。In the above embodiments, the support substrate 150 can be retained or removed as needed in addition to being supported as a substrate 110 or carrier 100.

除了上述說明電鍍形成導電跡線之方法外，本發明亦可於基板上形成一金屬層後，對金屬層進行蝕刻以形成所需之導電跡線，圖上未示。類似的，此金屬層除可利用金屬氣相沉積製作外。此金屬層亦可為一金屬薄膜並以壓合方式設置於基板上。In addition to the above-described method of electroplating to form conductive traces, the present invention may also etch a metal layer after forming a metal layer on the substrate to form a desired conductive trace, not shown. Similarly, this metal layer can be fabricated by metal vapor deposition. The metal layer may also be a metal film and disposed on the substrate in a press-fit manner.

於本發明中，設置於下層晶片周圍之導電跡線並不限定為單層結構。如圖4所示，導電跡線120亦可為導電層121與導電層123所構成。可理解的是，多層結構之導電跡線120可藉由進行重複類似前述單層結構製作之電鍍、化學氣相沉積或蝕刻等製程所達成。In the present invention, the conductive traces disposed around the underlying wafer are not limited to a single layer structure. As shown in FIG. 4, the conductive traces 120 may also be formed by the conductive layer 121 and the conductive layer 123. It can be understood that the conductive traces 120 of the multilayer structure can be achieved by performing processes such as electroplating, chemical vapor deposition or etching which are similar to the single layer structure described above.

利用上述實施例之製作方法所形成之結構如圖1G、圖2A、圖2B與圖3I所示。本發明之半導體封裝結構包括：一多晶片堆疊結構，其包含一第一晶片130；一導電跡線120，係設置於第一晶片130周圍；一第二晶片132，係設置於第一晶片130之上方並與導電跡線120電性連接，其中第二晶片132之主動面可朝上疊置於第一晶片130上以打線方式與導電跡線120電性連接(如圖1G所示)；或是第二晶片132之主動面可朝下以覆晶方式與導電跡線120電性連接(如圖2A 與圖2B所示)；以及一封裝膠體140覆蓋第一晶片130、第二晶片132、導電跡線120，並使多晶片堆疊結構的下表面露出導電跡線120的下表面與第一晶片130的下表面；一重新佈線層160設置於多晶片堆疊結構的下表面，並與導電跡線120的下表面及第一晶片130電性連接；；以及多個導電焊球170，係設置於重新佈線層160之下表面並與重新佈線層160電性連接。於一實施例中，如第一晶片130的下表面為主動面則第一晶片130直接與重新佈線層160電性連接；如第一晶片130的下表面不為主動面則第一晶片130透過導電跡線120與重新佈線層160電性連接。The structure formed by the manufacturing method of the above embodiment is as shown in FIGS. 1G, 2A, 2B, and 3I. The semiconductor package structure of the present invention comprises: a multi-wafer stack structure comprising a first wafer 130; a conductive trace 120 disposed around the first wafer 130; and a second wafer 132 disposed on the first wafer 130 Above and connected to the conductive traces 120, wherein the active surface of the second wafer 132 can be stacked on the first wafer 130 to be electrically connected to the conductive traces 120 (as shown in FIG. 1G); Or the active surface of the second wafer 132 can be electrically connected to the conductive traces 120 in a flip chip manner (see FIG. 2A). And the encapsulant 140 covers the first wafer 130, the second wafer 132, the conductive traces 120, and exposes the lower surface of the multi-wafer stack structure to the lower surface of the conductive trace 120 and the first wafer 130. a lower surface; a rewiring layer 160 is disposed on the lower surface of the multi-wafer stack structure and electrically connected to the lower surface of the conductive trace 120 and the first wafer 130; and a plurality of conductive solder balls 170 are disposed in the The lower surface of the wiring layer 160 is electrically connected to the rewiring layer 160. In one embodiment, if the lower surface of the first wafer 130 is the active surface, the first wafer 130 is directly electrically connected to the rewiring layer 160; if the lower surface of the first wafer 130 is not the active surface, the first wafer 130 is transparent. The conductive traces 120 are electrically connected to the rewiring layer 160.

請參照圖3I與圖4，於本發明中，第一晶片130的下表面為第一晶片130的主動面，第一晶片130與第二晶片132之主動面具有多個對外電性接點(圖上未標)用以與重新佈線層160或導電跡線120電性連接。重新佈線層160之上下表面亦有多個電性接點(圖上未標)。重新佈線層160之上表面的對內電性接點係與第一晶片130主動面多個對外電性接點與導電跡線120電性連接，而重新佈線層160之下表面的對外電性接點則與供外部導電焊球170電性連接。Referring to FIG. 3I and FIG. 4, in the present invention, the lower surface of the first wafer 130 is the active surface of the first wafer 130, and the active surfaces of the first wafer 130 and the second wafer 132 have a plurality of external electrical contacts ( The figure is not labeled) for electrically connecting to the rewiring layer 160 or the conductive traces 120. The upper surface of the rewiring layer 160 also has a plurality of electrical contacts (not shown). The internal electrical contacts on the upper surface of the rewiring layer 160 are electrically connected to the plurality of external contacts of the first wafer 130 and the conductive traces 120, and the external electrical properties of the lower surface of the rewiring layer 160. The contacts are electrically connected to the external conductive solder balls 170.

於不同實施例中，於第一晶片130與第二晶片132間可設置黏著層(圖上未標)固定，如圖1G、圖2B與圖3I所示。於一實施例中，第二晶片132亦可懸空設置於第一晶片130之上方。In different embodiments, an adhesive layer (not shown) may be disposed between the first wafer 130 and the second wafer 132, as shown in FIGS. 1G, 2B and 3I. In an embodiment, the second wafer 132 can also be suspended above the first wafer 130.

於不同實施例中，一支撐基材150可設置於封裝膠體140之上方，如圖1G與3I。此支撐基材150除了可供半導體封裝結構於製作時提供支撐外，亦可用以加強半導體封裝結構之結構強度。於一實施例中，若支撐基材150使用的為具有EMI遮蔽效果之材料時。此支撐基材150即可作為半導體封裝結構中對EMI之屏障。支撐基材150之結構並不限於平板 狀覆蓋於封裝膠體140上。支撐基材150亦可具有圖案化設計以獲得較佳之EMI屏障效果。於本發明中，是否使用支撐基材可依使用者之需要進行選擇。In various embodiments, a support substrate 150 can be disposed over the encapsulant 140, such as FIGS. 1G and 3I. In addition to providing support for the semiconductor package structure during fabrication, the support substrate 150 can also be used to enhance the structural strength of the semiconductor package structure. In one embodiment, the support substrate 150 is made of a material having an EMI shielding effect. This support substrate 150 serves as a barrier to EMI in a semiconductor package structure. The structure of the support substrate 150 is not limited to a flat plate. The cover is covered on the encapsulant 140. The support substrate 150 can also have a patterned design to achieve a better EMI barrier effect. In the present invention, whether or not the support substrate is used can be selected according to the needs of the user.

根據上述說明，本發明之特徵在於晶片堆疊前於下層晶片周圍製作導電跡線，此導電跡線供上層晶片與重新佈線層電性連接用。導電跡線的製作可用多種方式，如直接轉印、電鍍或蝕刻等。導電跡線除了可為單層結構外亦可為多層結構，可因應上層晶片需要提供不同變化。In accordance with the above description, the present invention is characterized in that a conductive trace is formed around the underlying wafer prior to wafer stacking, the conductive trace for electrically connecting the upper wafer to the rewiring layer. Conductive traces can be fabricated in a variety of ways, such as direct transfer, plating, or etching. In addition to being a single layer structure, the conductive traces may also have a multi-layer structure, which may vary depending on the needs of the upper layer wafer.

綜合上述說明，本發明之半導體封裝結構及其製造方法，利用多晶片先堆疊封裝再與重新佈線層結合，其中下層晶片之主動面係朝下直接與重新佈線層電性連接，而上層晶片係透過設置於下層晶片周圍之導電跡線與與重新佈線層電性連接。In summary, the semiconductor package structure and the method of fabricating the same according to the present invention utilize a multi-wafer first stacked package and then a rewiring layer, wherein the active surface of the lower wafer is directly electrically connected to the rewiring layer downward, and the upper wafer system is The electrical wiring is electrically connected to the rewiring layer through a conductive trace disposed around the lower wafer.

以上所述之實施例僅係為說明本發明之技術思想及特點，其目的在使熟習此項技藝之人士能夠瞭解本發明之內容並據以實施，當不能以之限定本發明之專利範圍，即大凡依本發明所揭示之精神所作之均等變化或修飾，仍應涵蓋在本發明之專利範圍內。The embodiments described above are merely illustrative of the technical spirit and the features of the present invention, and the objects of the present invention can be understood by those skilled in the art, and the scope of the present invention cannot be limited thereto. That is, the equivalent variations or modifications made by the spirit of the present invention should still be included in the scope of the present invention.

100‧‧‧載具100‧‧‧ Vehicles

110‧‧‧基板110‧‧‧Substrate

112‧‧‧第一晶片承載區域112‧‧‧First wafer carrying area

120‧‧‧導電跡線120‧‧‧conductive traces

120’‧‧‧金屬層120’‧‧‧metal layer

121‧‧‧導電層121‧‧‧ Conductive layer

122’‧‧‧第一圖案化光阻層122'‧‧‧First patterned photoresist layer

122‧‧‧金屬最終表面處理層122‧‧‧Metal final surface treatment layer

123‧‧‧導電層123‧‧‧ Conductive layer

124'‧‧‧第二圖案化光阻層124'‧‧‧Second patterned photoresist layer

126’‧‧‧導電接點126'‧‧‧Electrical contacts

130‧‧‧第一晶片130‧‧‧First chip

132‧‧‧第二晶片132‧‧‧second chip

140‧‧‧封裝膠體140‧‧‧Package colloid

150‧‧‧支撐基材150‧‧‧Support substrate

160‧‧‧重新佈線層160‧‧‧Rewiring layer

170‧‧‧導電焊球170‧‧‧ Conductive solder balls

172‧‧‧導電焊球172‧‧‧Electrical solder balls

圖1A、圖1B、圖1C、圖1D、圖1E、圖1F與圖1G為本發明實施例之剖面示視圖。1A, 1B, 1C, 1D, 1E, 1F, and 1G are cross-sectional views of an embodiment of the present invention.

圖2A與圖2B為本發明不同實施例之剖面示視圖。2A and 2B are cross-sectional views of different embodiments of the present invention.

圖3A、圖3B、圖3C、圖3D、圖3E、圖3F、圖3G、圖3H與圖3I為本發明實施例之剖面示視圖。3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H and 3I are cross-sectional views of an embodiment of the present invention.

圖4為本發明不同實施例之剖面示視圖。Figure 4 is a cross-sectional view of a different embodiment of the present invention.

110‧‧‧基板110‧‧‧Substrate

112‧‧‧第一晶片承載區域112‧‧‧First wafer carrying area

120‧‧‧導電跡線120‧‧‧conductive traces

130‧‧‧第一晶片130‧‧‧First chip

132‧‧‧第二晶片132‧‧‧second chip

140‧‧‧封裝膠體140‧‧‧Package colloid

150‧‧‧支撐基材150‧‧‧Support substrate

160‧‧‧重新佈線層160‧‧‧Rewiring layer

170‧‧‧導電焊球170‧‧‧ Conductive solder balls

Claims (18)

一種半導體封裝結構之製造方法，係包含下列步驟：提供一基板；形成一導電跡線(conductive trace)於該基板上，其中該導電跡線係環繞於一第一晶片承載區域之周圍；設置一第一晶片於該基板之該第一晶片承載區域上，其中該第一晶片之下表面係朝下與該基板接觸；設置一第二晶片於該第一晶片之上方並與該導電跡線電性連接；形成一封裝膠體覆蓋該第一晶片、該第二晶片、該導電跡線與該基板之上表面；移除該基板，其中該封裝膠體之下表面係暴露出該導電跡線之下表面與該第一晶片之下表面；設置一重新佈線層(redistribution layer)於該封裝膠體之下表面，其中該第一晶片與該導電跡線係分別與該重新佈線層電性連接；以及設置多個導電焊球於該重新佈線層之下表面並與該重新佈線層電性連接。 A method of fabricating a semiconductor package structure includes the steps of: providing a substrate; forming a conductive trace on the substrate, wherein the conductive trace surrounds a first wafer carrying area; a first wafer is disposed on the first wafer carrying region of the substrate, wherein a lower surface of the first wafer is in contact with the substrate downward; a second wafer is disposed above the first wafer and electrically connected to the conductive trace Forming an encapsulant covering the first wafer, the second wafer, the conductive trace and the upper surface of the substrate; removing the substrate, wherein the underlying surface of the encapsulant is exposed to the conductive trace a surface and a lower surface of the first wafer; a redistribution layer is disposed on the lower surface of the encapsulant, wherein the first wafer and the conductive trace are electrically connected to the rewiring layer, respectively; A plurality of conductive solder balls are electrically connected to the lower surface of the rewiring layer and to the rewiring layer. 如請求項1所述之半導體封裝結構之製造方法，其中更包含一載具用以承載該基板。 The method of fabricating a semiconductor package structure according to claim 1, further comprising a carrier for carrying the substrate. 如請求項1所述之半導體封裝結構之製造方法，其中形成該導電跡線的步驟包含：形成一金屬層於該基板上；形成一第一圖案化光阻層於該金屬層上定義出該導電跡線之圖案；電鍍形成該導電跡線於該金屬層上；移除該第一圖案化光阻層；以及移除該第一晶片承載區域之該金屬層至暴露出該基板之上表面。 The method of fabricating a semiconductor package structure according to claim 1, wherein the forming the conductive trace comprises: forming a metal layer on the substrate; forming a first patterned photoresist layer on the metal layer to define the a pattern of conductive traces; electroplating to form the conductive traces on the metal layer; removing the first patterned photoresist layer; and removing the metal layer of the first wafer carrying region to expose the upper surface of the substrate . 如請求項3所述之半導體封裝結構之製造方法，其中於移除該第一圖案化光阻層步驟前更包含：形成一第二圖案化光阻層於該第一圖案化光阻層與該導電跡線上，其中該第二圖案化光阻層係暴露出該導電跡線之多個導電接點且該些導電接點係用以讓該導電跡線與該第二晶片電性連接；形成一金屬最終表面處理層於該導電跡線之該些導電接點上；以及同時移除該第一圖案化光阻層與該第二圖案化光阻層。 The method of fabricating a semiconductor package structure according to claim 3, further comprising: forming a second patterned photoresist layer on the first patterned photoresist layer before the step of removing the first patterned photoresist layer The conductive traces, wherein the second patterned photoresist layer exposes a plurality of conductive contacts of the conductive traces and the conductive contacts are used to electrically connect the conductive traces to the second wafer; Forming a metal final surface treatment layer on the conductive contacts of the conductive trace; and simultaneously removing the first patterned photoresist layer and the second patterned photoresist layer. 如請求項3所述之半導體封裝結構之製造方法，其中該金屬層為一金屬薄膜，係以壓合方式設置於該基板上。 The method of fabricating a semiconductor package structure according to claim 3, wherein the metal layer is a metal film disposed on the substrate in a press-fit manner. 如請求項1所述之半導體封裝結構之製造方法，其中形成該導電跡線的步驟包含：形成一金屬層於該基板上；以及對該金屬層進行蝕刻以形成該導電跡線。 The method of fabricating a semiconductor package structure according to claim 1, wherein the forming the conductive trace comprises: forming a metal layer on the substrate; and etching the metal layer to form the conductive trace. 如請求項6所述之半導體封裝結構之製造方法，其中該金屬層為一金屬薄膜，係以壓合方式設置於該基板上。 The method of fabricating a semiconductor package structure according to claim 6, wherein the metal layer is a metal film disposed on the substrate in a press-fit manner. 如請求項1所述之半導體封裝結構之製造方法，其中於移除該基板步驟前更包含設置一支撐基材於該封裝膠體之上表面。 The method of fabricating a semiconductor package structure according to claim 1, wherein the step of removing the substrate further comprises disposing a support substrate on an upper surface of the encapsulant. 如請求項1所述之半導體封裝結構之製造方法，其中該第二晶片之主動面可朝上疊置於該第一晶片上以打線方式與該導電跡線電性連接；或是該第二晶片之主動面可朝下以覆晶方式與該導電跡線電性連接。 The method of manufacturing the semiconductor package structure of claim 1, wherein the active surface of the second wafer is electrically stacked on the first wafer to be electrically connected to the conductive trace; or the second The active surface of the wafer can be electrically connected to the conductive trace in a flip chip direction downward. 如請求項1所述之半導體封裝結構之製造方法，其中該第一晶片的下表面為該第一晶片的主動面。 The method of fabricating a semiconductor package structure according to claim 1, wherein a lower surface of the first wafer is an active surface of the first wafer. 如請求項1所述之半導體封裝結構之製造方法，其中該第一晶片透過該導電跡線與該重新佈線層電性連接。 The method of fabricating a semiconductor package structure according to claim 1, wherein the first wafer is electrically connected to the rewiring layer through the conductive trace. 一種半導體封裝結構，係包含： 一多晶片堆疊結構，包含：；一第一晶片；一導電跡線，係設置於該第一晶片周圍；一第二晶片，係設置於該第一晶片之上方並與該導電跡線電性連接；以及一封裝膠體覆蓋該第一晶片、該第二晶片與該導電跡線，並使該多晶片堆疊結構的下表面露出該導電跡線的下表面與該第一晶片的下表面；一重新佈線層，設置於該多晶片堆疊結構的下表面，並與該導電跡線的下表面及該第一晶片電性連接；以及多個導電焊球，係設置於該重新佈線層之下表面並與該重新佈線層電性連接。 A semiconductor package structure comprising: a multi-wafer stack structure comprising: a first wafer; a conductive trace disposed around the first wafer; a second wafer disposed over the first wafer and electrically connected to the conductive trace Connecting; and an encapsulant covering the first wafer, the second wafer and the conductive trace, and exposing a lower surface of the multi-wafer stack structure to a lower surface of the conductive trace and a lower surface of the first wafer; a rewiring layer disposed on the lower surface of the multi-wafer stack structure and electrically connected to the lower surface of the conductive trace and the first wafer; and a plurality of conductive solder balls disposed on the lower surface of the rewiring layer And electrically connected to the rewiring layer. 如請求項12所述之半導體封裝結構，其中一黏著層設置該第一晶片與該第二晶片間。 The semiconductor package structure of claim 12, wherein an adhesive layer is disposed between the first wafer and the second wafer. 如請求項12所述之半導體封裝結構，其中該第二晶片之主動面可朝上疊置於該第一晶片上以打線方式與該導電跡線電性連接；或是該第二晶片之主動面可朝下以覆晶方式與該導電跡線電性連接。 The semiconductor package structure of claim 12, wherein the active surface of the second wafer is electrically stacked on the first wafer to be electrically connected to the conductive trace; or the active of the second wafer The surface can be electrically connected to the conductive trace in a flip chip manner. 如請求項12所述之半導體封裝結構，其中一支撐基材設置於該封裝膠體之上表面。 The semiconductor package structure of claim 12, wherein a support substrate is disposed on the upper surface of the encapsulant. 如請求項15所述之半導體封裝結構，其中該支撐基材之材質係為EMI遮蔽材料。 The semiconductor package structure of claim 15, wherein the material of the support substrate is an EMI shielding material. 如請求項12所述之半導體封裝結構，其中該第一晶片的下表面為該第一晶片的主動面。 The semiconductor package structure of claim 12, wherein the lower surface of the first wafer is an active surface of the first wafer. 如請求項12所述之半導體封裝結構，其中該第一晶片透過該導電跡線與該重新佈線層電性連接。 The semiconductor package structure of claim 12, wherein the first wafer is electrically connected to the rewiring layer through the conductive trace.
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TWI580079B (en) * 2013-12-26 2017-04-21 新世紀光電股份有限公司 Light emitting diode package structure and light emitting diode module
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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201025554A (en) * 2008-12-24 2010-07-01 Powertech Technology Inc Multiple flip-chip package

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2591772Y (en) * 2002-12-26 2003-12-10 威盛电子股份有限公司 Chip package structure
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CN101958253A (en) * 2009-07-14 2011-01-26 日月光半导体制造股份有限公司 Packaging technique and packaging structure

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201025554A (en) * 2008-12-24 2010-07-01 Powertech Technology Inc Multiple flip-chip package

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