CN101958253A - Packaging technique and packaging structure - Google Patents

Packaging technique and packaging structure Download PDF

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Publication number
CN101958253A
CN101958253A CN2009101522826A CN200910152282A CN101958253A CN 101958253 A CN101958253 A CN 101958253A CN 2009101522826 A CN2009101522826 A CN 2009101522826A CN 200910152282 A CN200910152282 A CN 200910152282A CN 101958253 A CN101958253 A CN 101958253A
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China
Prior art keywords
chip
semiconductor substrate
packing colloid
encapsulating structure
primer
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Pending
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CN2009101522826A
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Chinese (zh)
Inventor
沈启智
陈仁川
潘彦良
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Publication date
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Priority to CN2009101522826A priority Critical patent/CN101958253A/en
Publication of CN101958253A publication Critical patent/CN101958253A/en
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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Abstract

The invention discloses a packaging technique and a packaging structure. According to the packaging technique, firstly a semiconductor substrate is configured on a carrier, the surface of which is provided with an adhesive layer, and is engaged with the carrier through the adhesive layer; then a chip is combined with the semiconductor substrate in an inverted way, and a first primer is formed between the chip and the semiconductor substrate to coat a plurality of first conductive bumps on the bottom of the chip; after that, a first packaging colloid is formed on the semiconductor substrate and at least coats the lateral surface of the chip and the first primer; finally, the semiconductor substrate, together with the chip on the semiconductor substrate and the first packaging colloid, is separated from the adhesive layer on the carrier to form an array packaging structure. According to the invention, the semiconductor substrate can be thin, and the packaging thickness can be reduced.

Description

Packaging technology and encapsulating structure
Technical field
The present invention relates to a kind of semiconductor technology and structure thereof, and particularly relate to a kind of packaging technology and encapsulating structure.
Background technology
Along with the progress of semiconductor and encapsulation technology, the making of microcomponents such as microcomputer electric component or photoelectric cell is also marched toward the stage of wafer-class encapsulation by early stage wafer-level package, reduces packaging cost and light, thin, short, little purpose to reach.Specifically, wafer-class encapsulation is to be the object of encapsulation process with wafer (wafer), and its main purpose is in the packaging technology of facilitating chip, to save time and cost.After the production of integrated circuits on the wafer is finished, just can directly carry out packaging technology to the full wafer wafer, thereafter carry out the action of wafer cutting (wafer saw) again, forming a plurality of chip packing-bodies respectively, and the chip packing-body that completes can be installed on the circuit base plate.
In general, before making integrated circuit on the wafer, can carry out thinning technology to wafer usually, make the less thick of wafer.On wafer, make in the process of integrated circuit, can comprise corresponding respectively each chip bonding area that is engaged on the wafer of mode that a plurality of chips are engaged with flip-chip.Owing to adopt flip-chip joining technique joint chip to the technological ability on the wafer to still have its limiting value at present, therefore when employed wafer thickness during less than the limiting value of its technological ability, in the process of carrying out the flip-chip joint, the situation of fragmentation takes place easily, produce yield and reduce.
Summary of the invention
The invention provides a kind of encapsulating structure, it has thin semiconductor substrate, can reduce package thickness.
The invention provides a kind of packaging technology, in order to make above-mentioned encapsulating structure.
The present invention proposes a kind of packaging technology.At first, the configuring semiconductor substrate is on carrier, and wherein loader surface has adhesion coating, and semiconductor substrate is engaged to carrier via adhesion coating.Then, on semiconductor substrate, and form first primer between chip and semiconductor substrate, with a plurality of first conductive projections of coating chip bottom with flip-chip mode joint chip.Afterwards, form first packing colloid on semiconductor substrate.First packing colloid is the side and first primer of coating chip at least.At last, make semiconductor substrate together with the adhesion coating on chip on it and first packing colloid disengaging carrier, to form array encapsulation structure.
In an embodiment of the present invention, above-mentioned packaging technology also be included in the configuring semiconductor substrate on carrier after, the grinding semiconductor substrate is reduced to below 4 mils (mil) thickness of semiconductor substrate.
In an embodiment of the present invention, above-mentioned first primer is with applied on semiconductor substrate before semiconductor substrate engages at chip.
In an embodiment of the present invention, above-mentioned first primer be chip be received between chip and the semiconductor substrate after semiconductor substrate engages.
In an embodiment of the present invention, above-mentioned first packing colloid end face of coating chip also.
In an embodiment of the present invention, above-mentioned first packing colloid exposes the end face of chip.
In an embodiment of the present invention, above-mentioned removes after carrier and the adhesion coating, also comprises the cutting array encapsulation structure, to form chip packaging unit.Chip packaging unit comprise chip with and the base board unit of pairing semiconductor substrate, wherein the side of the side of first packing colloid and semiconductor substrate trims in fact.
In an embodiment of the present invention, above-mentioned packaging technology also comprises with flip-chip mode joint chip encapsulation unit on circuit base plate.
In an embodiment of the present invention, above-mentioned packaging technology also comprises and forms second packing colloid on circuit base plate, and second packing colloid side of coating chip encapsulation unit at least.
In an embodiment of the present invention, above-mentioned packaging technology also is included in and forms before second packing colloid, forms second primer between chip packaging unit and circuit base plate, with a plurality of second conductive projections of coating chip encapsulation unit bottom.
In an embodiment of the present invention, above-mentioned second packing colloid end face of coating chip encapsulation unit also.
In an embodiment of the present invention, above-mentioned second packing colloid exposes the end face of chip packaging unit.
The present invention also proposes a kind of encapsulating structure, and it comprises semiconductor substrate, chip, first primer and first packing colloid.Semiconductor substrate has upper surface, and wherein the thickness of semiconductor substrate is below 8 mils.Chip configuration is on the upper surface of semiconductor substrate, and the bottom of chip has a plurality of first conductive projections.First primer is disposed between semiconductor substrate and the chip, to coat these first conductive projections.First packing colloid is disposed on the semiconductor substrate, and the side and first primer of coating chip at least.
In an embodiment of the present invention, the thickness of above-mentioned semiconductor substrate is below 4 mils.
In an embodiment of the present invention, above-mentioned first packing colloid end face of coating chip also.
In an embodiment of the present invention, above-mentioned first packing colloid exposes the end face of chip.
In an embodiment of the present invention, above-mentioned encapsulating structure also comprises circuit base plate.Circuit base plate is disposed on the lower surface of semiconductor substrate with respect to upper surface.
In an embodiment of the present invention, above-mentioned encapsulating structure also comprises second packing colloid.Second packing colloid is disposed on the circuit base plate, and coats the side of first packing colloid and semiconductor substrate at least.
In an embodiment of the present invention, above-mentioned encapsulating structure also comprises second primer.Second primer is disposed between semiconductor substrate and the circuit base plate, with a plurality of second conductive projections on the lower surface that coats semiconductor substrate.
In an embodiment of the present invention, above-mentioned second packing colloid end face of coating chip and first packing colloid also.
In an embodiment of the present invention, above-mentioned second packing colloid exposes the end face of the chip and first packing colloid.
In an embodiment of the present invention, above-mentioned semiconductor substrate is a silicon substrate.
In an embodiment of the present invention, the side of the first above-mentioned packing colloid and the side of semiconductor substrate trim in fact.
Based on above-mentioned, because the thinner thickness of semiconductor substrate of the present invention (for example being that 8 mils are following), therefore chip is engaged on the semiconductor substrate in the flip-chip mode, and coats and when forming encapsulating structure, this encapsulating structure has thin package thickness via packing colloid.In addition, because semiconductor substrate of the present invention is to support by carrier, in the time of therefore can preventing that chip join is to semiconductor substrate, the situation of semiconductor substrate generation fragmentation.In addition, owing to be first, therefore can increase the intensity of semiconductor substrate relatively via cutting again after the packing colloid packaged semiconductor substrate, to prevent the situation of semiconductor substrate generation fragmentation, can reduce the degree of difficulty of subsequent technique, help to promote and produce yield, and be suitable for a large amount of productions.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Figure 1A is the generalized section of a kind of encapsulating structure of embodiments of the invention.
Figure 1B is the generalized section of a kind of encapsulating structure of another embodiment of the present invention.
Fig. 1 C is the generalized section of a kind of encapsulating structure of another embodiment of the present invention.
Fig. 2 is the making flow chart of a kind of encapsulating structure of embodiments of the invention.
Fig. 3 A to Fig. 3 G illustrates the generalized section of a kind of packaging technology of embodiments of the invention.
Fig. 4 A to Fig. 4 B illustrates formation first primer of another embodiment of the present invention and the generalized section of joint chip.
Fig. 5 A to Fig. 5 B illustrates the generalized section of formation first packing colloid of two different embodiment of the present invention.
The chip packaging unit flip-chip that Fig. 6 A illustrates another embodiment of the present invention is engaged to the generalized section of circuit base plate.
The chip packaging unit flip-chip that Fig. 6 B illustrates another embodiment of the present invention is engaged to the generalized section of circuit base plate.
Description of reference numerals
100a～100c: encapsulating structure 110: semiconductor substrate
110a: upper surface 110b: lower surface
Conductive projection 114 in 112: the second: straight-through silicon wafer perforation structure
120: 122: the first conductive projections of chip
140: the first packing colloids of 130: the first primers
150: circuit base plate 152: soldered ball
170: the second primers of 160: the second packing colloids
200: carrier 210: adhesion coating
250: base board unit 260: array encapsulation structure
270: chip packaging unit 300: the injecting glue device
400: thermal head 500: half tone
601～607: step
Embodiment
Figure 1A is the generalized section of a kind of encapsulating structure of embodiments of the invention.Please refer to Figure 1A, encapsulating structure 100a comprises semiconductor substrate 110, chip 120, first primer 130 and first packing colloid 140.
Semiconductor substrate 110 for example is a silicon substrate, and it has upper surface 110a, and wherein the thickness of semiconductor substrate 110 is below 8 mils, for example is below 4 mils, even can be 2 mils.Chip 120 is disposed on the upper surface 110a of semiconductor substrate 110, and the bottom of chip 120 has a plurality of first conductive projections 122.First primer 130 is disposed between semiconductor substrate 110 and the chip 120, to coat these first conductive projections 122.First packing colloid 140 is disposed on the semiconductor substrate 110, and the end face of the side of coating chip 120, first primer 130 and chip 120, and wherein the side of the side of first packing colloid 140 and semiconductor substrate 110 trims in fact.
What deserves to be mentioned is, in the present embodiment, semiconductor substrate 110 is to adopt straight-through silicon wafer perforation (Through-Silicon Via, TSV) technology comes to electrically connect with chip 120, wherein straight-through silicon wafer puncturing technique for example is the passage in chip or wafer internal production conduction, to form vertical straight-through silicon wafer perforation structure 114, the density maximum that it can make chip 120 pile up at three-dimensional, the overall dimension minimum, therefore the signal between semiconductor substrate 110 and the chip 120 just can transmit up and down by straight-through silicon wafer perforation structure 114, but lift elements speed, reduce signal delay and power consumption.
In addition, the encapsulating structure 100a of present embodiment also comprises circuit base plate 150, second packing colloid 160 and second primer 170.Circuit base plate 150 is disposed on the lower surface 110b of semiconductor substrate 110 with respect to upper surface 110a, and the bottom of circuit base plate 150 has a plurality of soldered balls 152, and wherein circuit base plate 150 for example is a printed circuit board (PCB).Second packing colloid 160 is disposed on the circuit base plate 150, and coats the side of first packing colloid 140 and semiconductor substrate 110, and the end face of first packing colloid 140.Second primer 170 is disposed between semiconductor substrate 110 and the circuit base plate 150, with a plurality of second conductive projections 112 on the lower surface 110b that coats semiconductor substrate 110.
In this mandatory declaration be; in the present embodiment; dispose second primer 170 between semiconductor substrate 110 and the circuit base plate 150; with second conductive projection 112 on the lower surface 110b that coats semiconductor substrate 110; but in other embodiments; also can there be second primer 170; that is to say; do not dispose second primer 170 between semiconductor substrate 110 and the circuit base plate 150; second conductive projection 112 on the lower surface 110b of semiconductor substrate 110 then coats by second packing colloid 160; still belong to the adoptable technical scheme of the present invention, do not break away from the scope of institute of the present invention desire protection.
In addition; the present invention does not limit the position and the form of first packing colloid 140 and second packing colloid 160; though first packing colloid 140 that reaches mentioned herein is embodied as the end face of side, first primer 130 and the chip 120 of coating chip 120; and second packing colloid 160 is embodied as the side that coats first packing colloid 140 and semiconductor substrate 110 at least; but known other can reach the structural design of protection chip 120; still belong to the adoptable technical scheme of the present invention, do not break away from the scope of institute of the present invention desire protection.
Below will utilize two embodiment that first packing colloid 140 of two kinds of encapsulating structure 100b～100c and first packing colloid 140 that second packing colloid 160 is different from encapsulating structure 100a and the design of second packing colloid 160 are described.
Figure 1B is the generalized section of a kind of encapsulating structure of another embodiment of the present invention.Please refer to Figure 1B, in the present embodiment, the encapsulating structure 100b of Figure 1B is similar to the encapsulating structure 100a of Figure 1A, only the two main difference part is: first packing colloid 140 exposes the end face of chip 120, and the end face of second packing colloid, 160 coating chips 120 and first packing colloid 140, wherein the side of the side of first packing colloid 140 and this semiconductor substrate 110 trims in fact.
Fig. 1 C is the generalized section of a kind of encapsulating structure of another embodiment of the present invention.Please refer to Fig. 1 C, in the present embodiment, the encapsulating structure 100c of Fig. 1 C is similar to the encapsulating structure 100a of Figure 1A, only the two main difference part is: first packing colloid 140 exposes the end face of chip 120, and second packing colloid 160 also exposes the end face of the chip 120 and first packing colloid 140, and wherein the side of the side of first packing colloid 140 and this semiconductor substrate 110 trims in fact.Because first packing colloid 140 and second packing colloid 160 all expose the end face of chip 120, therefore can improve the area of dissipation and the task performance of chip 120.In other words, encapsulating structure 100c has preferred radiating effect.
In brief, because the thickness of the semiconductor substrate 110 of present embodiment is below 8 mils, for example be below 4 mils, even can be 2 mils, therefore chip 120 and circuit base plate 150 are disposed at respectively on the upper surface 110a and lower surface 110b of semiconductor substrate 110, and when forming encapsulating structure 100a (or encapsulating structure 100b, 100c) by first packing colloid 140 and second packing colloid, 160 coating chips 120, semiconductor substrate 110 and circuit base plate 150, this encapsulating structure 100a (or encapsulating structure 100b, 100c) has the package thickness that approaches.In addition, when first packing colloid 140 exposes the end face of chip 120, and second packing colloid 160 can improve the area of dissipation and the task performance of chip 120 when also exposing the end face of chip 120, makes encapsulating structure 100c have preferred radiating effect.
In addition, the present invention also provides the packaging technology of making above-mentioned encapsulating structure.Fig. 2 is the making flow chart of a kind of encapsulating structure of embodiments of the invention.Fig. 3 A to Fig. 3 G illustrates the generalized section of a kind of packaging technology of embodiments of the invention.
At first, shown in step S601 and Fig. 3 A, configuring semiconductor substrate 110 is on carrier 200, and wherein the surface of carrier 200 has adhesion coating 210, and semiconductor substrate 110 is engaged to carrier 200 via adhesion coating 210, and wherein semiconductor substrate for example is a silicon substrate.
In the present embodiment, the generation type of adhesion coating 210 for example is to coat on the carrier 200 by method of spin coating (spincoating).In addition, before being disposed at semiconductor substrate 110 on the adhesion coating 210, also comprising the perforate (not illustrating) that in semiconductor substrate 110, forms earlier high-aspect-ratio (aspect ratio), and in perforate, insert conductor material (not illustrating).Then, on semiconductor substrate 110 configuration adhesion coatings 210, and the upper surface 110a of grinding (grinding) semiconductor substrate 110, the thickness of semiconductor substrate 110 is reduced to below 8 mils, for example be below 4 mils, even can be 2 mils, with thinning semiconductor substrate 110, and exposing conductor material in the perforate, the electric conducting material in this perforate and the perforate constitutes straight-through silicon wafer perforation structure 114.
Then; shown in step S602 and Fig. 3 B and Fig. 3 C; form first primer 130 between chip 120 and semiconductor substrate 110 by injecting glue device 300; and by thermal head 400 with flip-chip mode joint chip 120 on semiconductor substrate 110; a plurality of first conductive projections 122 of first primer, 130 coating chips, 120 bottoms wherein; in order to the electrical connection between the straight-through silicon wafer perforation structure 114 of first conductive projection 122 and the semiconductor substrate 110 of protection chip 120, and avoid the aqueous vapor intrusion and cause damage.
Specifically, in the present embodiment, if the size of chip 120 and chip 120 corresponding to the size of the base board unit on the semiconductor substrate 110 250 comparatively near the time, the ratio that for example is chip 120 sizes and base board unit 250 sizes is between 95% to 100%, after chip 120 flip-chips are engaged on the semiconductor substrate 110, spacing between adjacent two chips 120 is less, therefore can shown in Fig. 3 B, form first primer 130 earlier after on the semiconductor substrate 110, joint chip 120 shown in Fig. 3 C makes first conductive projection 122 of first primer, 130 coating chips 120 on semiconductor substrate 110 for another example.
In another embodiment, when if the size of chip 120 and chip 120 differ greatly corresponding to the size of the base board unit on the semiconductor substrate 110 250, the ratio that for example is chip 120 sizes and base board unit 250 sizes was smaller or equal to 95% o'clock, after chip 120 flip-chips are engaged on the semiconductor substrate 110, spacing between adjacent two chips 120 is bigger, therefore optionally adopts the step of Fig. 3 B to Fig. 3 C.Perhaps, can be shown in Fig. 4 A, first joint chip 120 is inserted first primer 130 between semiconductor substrate 110 and chip 120, for another example with first conductive projection 122 of coating chip 120 after on the semiconductor substrate 110 shown in Fig. 4 B.In other words, can optionally adjust according to the dimensional ratios of the base board unit 250 on chip 120 and the semiconductor substrate 110 and form first primer 130 and joint chip 120 steps, above-mentioned only for illustrating, not as limit.
Then, shown in step S603 and Fig. 3 D, form first packing colloid 140 on semiconductor substrate 110, wherein first packing colloid 140 side and first primer 130 of coating chip 120 at least.In the present embodiment, forming the method for first packing colloid 140 on semiconductor substrate 110 for example is compression moulding (molding), and first packing colloid 140 can cover the end face of side, first primer 130 and the chip 120 of chip 120 by the mode of compression moulding.In another embodiment, shown in Fig. 5 A, first packing colloid 140 also can cover the side and first primer 130 of chip 120 by the mode of compression moulding, but exposes the end face of chip 120, to improve the area of dissipation and the task performance of chip 120.
Certainly, forming the method for first packing colloid 140 on semiconductor substrate 110 and also can adopt other modes, for example is print process (printing).Please refer to Fig. 5 B,, make the side and first primer 130 of first packing colloid, 140 coating chips 120 by the mode of half tone 500 with printing.In other words, first packing colloid 140 does not cover the end face of chip 120, that is to say, first packing colloid 140 exposes the end face of chip 120, can improve the area of dissipation and the task performance of chip 120.
Then, shown in step S604 and Fig. 3 E, make semiconductor substrate 110 together with the adhesion coating 210 on chip on it 120 and first packing colloid, the 140 disengaging carriers 200, to form array encapsulation structure 260.In the present embodiment, for example be the adhesion coating 210 that mode with heating and pressurizing makes semiconductor substrate 110 break away from the carriers 200 together with the chip on it 120 and first packing colloid 140, and expose a plurality of second conductive projections 112 in semiconductor substrate 110 bottoms.
Then, shown in step S605 and Fig. 3 F, cutting array encapsulation structure 260, to form a plurality of chip packaging units 270 (only schematically illustrate among Fig. 3 F one as represent), wherein chip packaging unit 270 comprise chip 120 with and the base board unit 250 of pairing semiconductor substrate 110.In the present embodiment, the method for cutting array encapsulation structure 260 is cutting first packing colloids 140 and semiconductor substrate 110, the side of first packing colloid 140 and the side of semiconductor substrate 110 is trimmed in fact, and form chip packaging unit 270.
Then, shown in step S606-S607 and Fig. 3 G, with flip-chip mode joint chip encapsulation unit 270 on circuit base plate 150.And, form second packing colloid 160 on circuit base plate 150 and form a plurality of soldered balls 152, wherein the side and the end face of second packing colloid, 160 coating chip encapsulation units 270 in the bottom of circuit base plate 150.
Specifically, present embodiment is gone forward in circuit base plate 150 at formation second packing colloid 160, can form second primer 170 earlier between chip packaging unit 270 and circuit base plate 150, with second conductive projection 112 of coating chip encapsulation unit 270 bottoms.In the present embodiment, circuit base plate 150 for example is a printed circuit board (PCB).So far, roughly finish the making of the encapsulating structure 100a of Figure 1A.
Similarly, second packing colloid 160 also can adopt the encapsulation form as first packing colloid 140, the semiconductor substrate 110 that meaning is promptly worked as Fig. 5 A adopts the semiconductor substrate 110 employing print processes of compression mouldings or Fig. 5 B and first packing colloid 140 is covered thereon, and after finishing step as above-mentioned Fig. 3 E and Fig. 3 F, second packing colloid 160 can coat first packing colloid 140 and the side of semiconductor substrate 110 and the end face of the chip 120 and first packing colloid 140, and finish the making of encapsulating structure 100b, please refer to Figure 1B.Perhaps, second packing colloid 160 also can only coat the side of first packing colloid 140 and semiconductor substrate 110, meaning i.e. second packing colloid 160 exposes the end face of first packing colloid 140 and chip 120, and finishes the making of encapsulating structure 100c, please refer to Fig. 1 C.
In this mandatory declaration be, the present invention does not limit joint chip encapsulation unit 270 in circuit base plate 150 and the order that forms second primer 170, though be that first joint chip encapsulation unit 270 is behind circuit base plate 150 in the present embodiment, insert second primer 170 again between circuit base plate 150 and chip packaging unit 270, but in other embodiments, can also form second primer 170 earlier behind circuit base plate 150, again chip packaging unit 270 is engaged on the circuit base plate 150, makes second primer 170 coat second conductive projection 112.Certainly, in other embodiments, also can there be second primer 170, that is to say, joint chip encapsulation unit 270 is after circuit base plate 150, can be formed directly in second packing colloid 160 covering the side and the end face of chip packaging unit 270, second conductive projection 112 that this moment, second packing colloid 160 also can coating chip encapsulation unit 270 bottoms please refer to Fig. 6 A.In addition, in another embodiment, also second primer 170 can only be arranged and do not have second packing colloid 160, that is to say, only have second primer 170 to coat second conductive projection 112, and the side of chip packaging unit 270 and end face all do not have the coating of second packing colloid 160, please refer to Fig. 6 B.In other words, second primer 170 optionally fills between chip packaging unit 270 and the circuit base plate 150, and second packing colloid 160 coating chip encapsulation unit 270 optionally.
In brief, because the semiconductor substrate 110 of present embodiment can be reduced to below 8 mils by the mode of grinding, for example be below 4 mils, even can be 2 mils, therefore chip 120 is engaged on the semiconductor substrate 110 in the flip-chip mode, and coat and when forming chip packaging unit 270 via cutting, this chip packaging unit 270 has thin package thickness by first packing colloid 140.In addition, this chip packaging unit 270 is engaged to circuit base plate 150 in the flip-chip mode, and coat when forming encapsulating structure 100a (or encapsulating structure 100b, 100c) by second packing colloid 160, this encapsulating structure 100a (or encapsulating structure 100b, 100c) has the package thickness that approaches.In addition, because semiconductor substrate 110 is to support by carrier 200, in the time of therefore can preventing that chip 120 flip-chips are engaged on the semiconductor substrate 110, the situation of fragmentation takes place in semiconductor substrate 110.Moreover, owing to be earlier via cutting again after first packing colloid, 140 packaged semiconductor substrate 110, therefore can increase the intensity of semiconductor substrate 110 relatively, to prevent that semiconductor substrate 110 from the situation of fragmentation taking place, can reduce the degree of difficulty of subsequent technique, help to promote and produce yield, and be suitable for a large amount of productions.
In sum, because the thickness of semiconductor substrate of the present invention can be reduced to below 8 mils, for example be below 4 mils, even can be to 2 mils, therefore chip and circuit base plate are disposed at respectively on the upper surface and lower surface of semiconductor substrate, and when forming encapsulating structure by packing colloid coating chip, semiconductor substrate and circuit base plate, this encapsulating structure has thin package thickness.In addition, when packing colloid exposes the end face of chip, can improve the area of dissipation and the task performance of chip, make encapsulating structure have preferred radiating effect.In addition,, therefore can increase the intensity of semiconductor substrate relatively,, help to promote and produce yield, and be suitable for a large amount of productions to reduce the degree of difficulty of subsequent technique because the making of encapsulating structure is earlier via cutting after the packing colloid packaged semiconductor substrate again.
Though the present invention discloses as above with embodiment; right its is not in order to limit the present invention; those of ordinary skill in the technical field under any; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking appended claim.

Claims (23)

1. packaging technology comprises:
The configuring semiconductor substrate is on carrier, and wherein this loader surface has adhesion coating, and this semiconductor substrate is engaged to this carrier via this adhesion coating;
On this semiconductor substrate, and form first primer between this chip and this semiconductor substrate with flip-chip mode joint chip, to coat a plurality of first conductive projections of this chip bottom;
Form first packing colloid on this semiconductor substrate, this first packing colloid coats side and this first primer of this chip at least; And
Make this semiconductor substrate break away from this adhesion coating on this carrier, to form array encapsulation structure together with this chip on it and this first packing colloid.
2. packaging technology as claimed in claim 1, also be included in the configuration this semiconductor substrate on this carrier after, grind this semiconductor substrate, the thickness of this semiconductor substrate is reduced to below 4 mils.
3. packaging technology as claimed in claim 1, wherein this first primer is with applied on this semiconductor substrate before this semiconductor substrate engages at this chip.
4. packaging technology as claimed in claim 1, wherein this first primer be this chip be received between this chip and this semiconductor substrate after this semiconductor substrate engages.
5. packaging technology as claimed in claim 1, wherein this first packing colloid also coats the end face of this chip.
6. packaging technology as claimed in claim 1, wherein this first packing colloid exposes the end face of this chip.
7. packaging technology as claimed in claim 1 wherein removes after this carrier and this adhesion coating, also comprises:
Cut this array encapsulation structure, forming chip packaging unit, this chip packaging unit comprise this chip with and the base board unit of pairing this semiconductor substrate, wherein the side of the side of this first packing colloid and this semiconductor substrate trims in fact.
8. packaging technology as claimed in claim 7 also comprises in the flip-chip mode engaging this chip packaging unit on circuit base plate.
9. packaging technology as claimed in claim 8 comprises also forming second packing colloid on this circuit base plate that this second packing colloid coats the side of this chip packaging unit at least.
10. packaging technology as claimed in claim 8 also comprises forming second primer between this chip packaging unit and this circuit base plate, to coat a plurality of second conductive projections of this chip packaging unit bottom.
11. packaging technology as claimed in claim 9, wherein this second packing colloid also coats the end face of this chip packaging unit.
12. packaging technology as claimed in claim 9, wherein this second packing colloid exposes the end face of this chip packaging unit.
13. an encapsulating structure comprises:
Semiconductor substrate has upper surface, and wherein the thickness of this semiconductor substrate is below 8 mils;
Chip is disposed on this upper surface of this semiconductor substrate, and the bottom of this chip has a plurality of first conductive projections;
First primer is disposed between this semiconductor substrate and this chip, to coat a plurality of first conductive projections; And
First packing colloid is disposed on this semiconductor substrate, and coats side and this first primer of this chip at least.
14. encapsulating structure as claimed in claim 13, wherein the thickness of this semiconductor substrate is below 4 mils.
15. encapsulating structure as claimed in claim 13, wherein this first packing colloid also coats the end face of this chip.
16. encapsulating structure as claimed in claim 13, wherein this first packing colloid exposes the end face of this chip.
17. encapsulating structure as claimed in claim 13 also comprises circuit base plate, is disposed on the lower surface of this semiconductor substrate with respect to this upper surface.
18. encapsulating structure as claimed in claim 17 also comprises second packing colloid, is disposed on this circuit base plate, and coats the side of this first packing colloid and this semiconductor substrate at least.
19. encapsulating structure as claimed in claim 17 also comprises second primer, is disposed between this semiconductor substrate and this circuit base plate, with a plurality of second conductive projections on this lower surface that coats this semiconductor substrate.
20. encapsulating structure as claimed in claim 19, wherein this second packing colloid also coats the end face of this chip and this first packing colloid.
21. encapsulating structure as claimed in claim 19, wherein this second packing colloid exposes the end face of this chip and this first packing colloid.
22. encapsulating structure as claimed in claim 13, wherein this semiconductor substrate is a silicon substrate.
23. encapsulating structure as claimed in claim 13, wherein the side of the side of this first packing colloid and this semiconductor substrate trims in fact.
CN2009101522826A 2009-07-14 2009-07-14 Packaging technique and packaging structure Pending CN101958253A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102651325A (en) * 2012-04-27 2012-08-29 江阴长电先进封装有限公司 Package method of two-dimensionally distributed coreless adapter plate
CN102760665A (en) * 2011-04-26 2012-10-31 群成科技股份有限公司 Semiconductor package structure and manufacturing method thereof
CN104795369A (en) * 2014-01-17 2015-07-22 矽品精密工业股份有限公司 Layer structure for mounting semiconductor device and method for manufacturing the same
CN114400208A (en) * 2022-01-07 2022-04-26 广东气派科技有限公司 Substrate design method for preventing underfill from overflowing

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102760665A (en) * 2011-04-26 2012-10-31 群成科技股份有限公司 Semiconductor package structure and manufacturing method thereof
CN102760665B (en) * 2011-04-26 2015-12-16 群成科技股份有限公司 Substrate-free semiconductor packaging structure and manufacturing method thereof
CN102651325A (en) * 2012-04-27 2012-08-29 江阴长电先进封装有限公司 Package method of two-dimensionally distributed coreless adapter plate
CN102651325B (en) * 2012-04-27 2014-07-09 江阴长电先进封装有限公司 Package method of two-dimensionally distributed coreless adapter plate
CN104795369A (en) * 2014-01-17 2015-07-22 矽品精密工业股份有限公司 Layer structure for mounting semiconductor device and method for manufacturing the same
CN114400208A (en) * 2022-01-07 2022-04-26 广东气派科技有限公司 Substrate design method for preventing underfill from overflowing
CN114400208B (en) * 2022-01-07 2022-12-27 广东气派科技有限公司 Substrate design method for preventing underfill from overflowing

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Application publication date: 20110126