CN102044447B - Packaging technology and packaging structure - Google Patents

Packaging technology and packaging structure Download PDF

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Publication number
CN102044447B
CN102044447B CN200910174057.2A CN200910174057A CN102044447B CN 102044447 B CN102044447 B CN 102044447B CN 200910174057 A CN200910174057 A CN 200910174057A CN 102044447 B CN102044447 B CN 102044447B
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Prior art keywords
semiconductor element
packing colloid
chip
semiconductor elements
plate
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CN200910174057.2A
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CN102044447A (en
Inventor
沈启智
陈仁川
潘彦良
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention relates to a packaging technology and a packaging structure. The packaging technology is as follows: a bearing plate is provided on which an adhesive layer is arranged; a plurality of first semiconductor elements are arranged on the adhesive layer; then a first packaging colloid is formed on the bearing plate, covers the side walls of the first semiconductor elements and fills gaps among the first semiconductor elements so as to enable the first semiconductor elements and the first packaging colloid to form a chip array plate; then a plurality of second semiconductor elements are respectively jointed on the first semiconductor elements in an inverted manner; a second packaging colloid is formed on the chip array plate, at least covers the side walls of the second semiconductor elements and fill gaps among the second semiconductor elements; the array plate and the adhesive layer are separated; then the second packaging colloid and the first packaging colloid are cut along the gaps among the second semiconductor elements.

Description

Packaging technology and encapsulating structure
Technical field
The present invention relates to a kind of packaging technology and encapsulating structure, and particularly relate to and a kind of large chip is disposed at packaging technology and encapsulating structure on the little chip.
Background technology
In information society now, the user all pursues high-speed, high-quality, polyfunctional electronic product.With regard to product appearance, the design of electronic product is to stride forward towards light, thin, short, little trend.Therefore, Electronic Encapsulating Technology develops such as multi-chip package technology such as stacked chip packages.
The mode that stacked chip packages utilizes vertical stacking with a plurality of chip packages in same encapsulating structure, so packaging density can be promoted so that the packaging body miniaturization, and can utilize three-dimensional stacking mode to shorten the path of the signal transmission between the chip, promoting the speed of signal transmission between the chip, and can be with the chip portfolio of difference in functionality in same packaging body.
The manufacture method of known stacked chip packages be first with a plurality of flip-chip bond to wafer; then along the gap cut crystal between these chips; to form a plurality of chip stack structures; again chip stack structure is disposed at afterwards and also forms in the circuit board packing colloid on the wiring board, with the protection chip stack structure.
Because being the mode by cut crystal, the manufacture method of known stacked chip packages forms a plurality of chip stack structures, therefore, in chip stack structure, certainly will be greater than the size that is engaged to the flip-chip on the wafer by the size of the formed chip of cut crystal.Therefore, the manufacture method of known stacked chip packages can only form small-size chips is disposed at encapsulating structure on the large size chip.
In addition, known technology is for reducing the integral thickness of stacked chip packages, can be with before flip-chip bond to be to the wafer, and first grinding wafers is to reduce the thickness of wafer.Yet at present the flip-chip bonded technology still has the limiting value on the technological ability, therefore, when employed wafer thickness during less than the limiting value of its technological ability, in the process of carrying out flip-chip bonded, the situation of fragmentation occurs easily, so that the technique yield reduces.In addition, the wafer that thickness is little easily breaks in cutting technique, so that the technique yield reduces.
Summary of the invention
The invention provides a kind of packaging technology, can make by the mutual stacking encapsulating structure that forms of the chip of various sizes, and the technique yield is high.
The invention provides a kind of encapsulating structure, it is disposed at large size chip on the small-size chips.
For specifically describing content of the present invention, at this a kind of packaging technology is proposed as described below.At first, provide loading plate, dispose adhesion coating on the loading plate.Then, a plurality of the first semiconductor elements are disposed on the adhesion coating, and the first semiconductor element is separated from one another and see through respectively adhesion coating is fixed on the loading plate.Then, form the first packing colloid at loading plate, the first packing colloid covers the sidewall of the first semiconductor element and fills up gap between the first semiconductor element, so that the first semiconductor element and the first packing colloid formation chip array plate.Afterwards, with on a plurality of the second semiconductor elements difference flip-chip bonded to the first semiconductor elements.Then, form the second packing colloid at the chip array plate, the second packing colloid covers at least the sidewall of the second semiconductor element and fills up gap between the second semiconductor element.Then, separating chips array board and adhesion coating.Afterwards, cut the second packing colloid and the first packing colloid along the gap between the second semiconductor element, to form a plurality of chip packaging units.
In an embodiment of the present invention, the first above-mentioned semiconductor element has a plurality of straight-through silicon wafer perforation structures, and packaging technology also is included in and forms after the chip array plate, and the grinding chip array board is with the thinned chip array board and expose the end face of the straight-through silicon wafer perforation structure of the first semiconductor element.
In an embodiment of the present invention, the method for above-mentioned grinding chip array board comprises the grinding chip array board until the thickness of chip array plate is less than or equal in fact 4 Mills.
In an embodiment of the present invention, above-mentioned packaging technology also is included in and forms after the chip array plate, on the first semiconductor element, form respectively a plurality of the first primers separated from one another, wherein each first primer covers the part around the first corresponding semiconductor element of the first corresponding semiconductor element and the first packing colloid, and with the second semiconductor element respectively on flip-chip bonded to the first semiconductor element time, a plurality of conductive projections of each second semiconductor element engage with corresponding the first semiconductor element by the first corresponding primer.
In an embodiment of the present invention, above-mentioned packaging technology also comprises chip packaging unit is disposed on the circuit base plate, so that the first semiconductor element electric and structural connection line substrate.
In an embodiment of the present invention, above-mentioned packaging technology also is included on the circuit base plate and forms the second primer, so that the second primer is between the first semiconductor element of chip packaging unit and circuit base plate and coat a plurality of conductive projections of the first semiconductor element.
In an embodiment of the present invention, above-mentioned packaging technology also is included in and forms the 3rd packing colloid on the circuit base plate, and the 3rd packing colloid covers the sidewall of chip packaging unit at least.
For specifically describing content of the present invention, propose a kind of encapsulating structure at this and comprise the first semiconductor element, the first packing colloid, the second semiconductor element and the second packing colloid.The first packing colloid coats the sidewall of the first semiconductor element.The second semiconductor element is disposed on the first semiconductor element and part the first packing colloid, and the size of the second semiconductor element is greater than the size of the first semiconductor element.The second packing colloid covers sidewall and first packing colloid of the second semiconductor element at least, and wherein the first packing colloid and the second packing colloid are each self-forming.
In an embodiment of the present invention, the sidewall of the first above-mentioned packing colloid trims in the sidewall of the second packing colloid.
In an embodiment of the present invention, first end face towards the second semiconductor element of the first above-mentioned packing colloid trims the second end face towards the second semiconductor element in the first semiconductor element.
In an embodiment of the present invention, the thickness of the first above-mentioned packing colloid equals in fact the thickness of the first semiconductor element.
In an embodiment of the present invention, the second above-mentioned semiconductor element has a plurality of conductive projections between the second semiconductor element and the first semiconductor element, and encapsulating structure also comprises primer, it is disposed between the second semiconductor element and the first semiconductor element and between the second semiconductor element and the first packing colloid, to coat the conductive projection of the second semiconductor element.
In an embodiment of the present invention, the thickness of the first above-mentioned semiconductor element is less than or equal in fact 4 Mills.
In an embodiment of the present invention, the second above-mentioned packing colloid also covers the end face away from the first semiconductor element of the second semiconductor element.
In an embodiment of the present invention, the second above-mentioned packing colloid exposes the end face away from the first semiconductor element of the second semiconductor element.
In an embodiment of the present invention, dispose a plurality of conductive projections on the bottom surface away from the second semiconductor element of the first above-mentioned semiconductor element.
In an embodiment of the present invention, above-mentioned encapsulating structure also comprises circuit base plate, and the first semiconductor element is disposed on the circuit base plate, and conductive projection is between the first semiconductor element and circuit base plate.
In an embodiment of the present invention, above-mentioned encapsulating structure also comprises primer, and it is disposed between the first semiconductor element and the circuit base plate, with the coated with conductive projection.
In an embodiment of the present invention, above-mentioned encapsulating structure also comprises the 3rd packing colloid, and it is disposed on the circuit base plate, and covers at least the sidewall of the first packing colloid and the sidewall of the second packing colloid.
Based on above-mentioned, the present invention can make by the mutual stacking encapsulating structure that forms of the chip of various sizes.In addition, because the second packing colloid can be strengthened the quite little chip array plate of thickness, therefore can firmly link the second whole semiconductor elements and the first whole semiconductor elements, and can form in the process of chip packaging unit in the mode with cutting, avoid the chip array plate cracked, thus the lifting process yield.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate accompanying drawing to be described in detail below.
Description of drawings
Figure 1A～Fig. 1 I illustrates the profile of the packaging technology of the embodiment of the invention.
Fig. 2 A～Fig. 2 D illustrates the profile of the packaging technology of another embodiment of the present invention.
Description of reference numerals
100,200: encapsulating structure
110: loading plate
120: adhesion coating
130: the first semiconductor elements
132: conductive projection
134,142,164,172, W, W1: sidewall
136,144,166: end face
138: perforate
140: the first packing colloids
150,190: primer
160: the second semiconductor elements
162: conductive projection
168,182: the bottom surface
170,210: the second packing colloids
180: circuit base plate
220, M: the 3rd packing colloid
A: chip array plate
C1, C2: chip packaging unit
D: electric conducting material
G1, G2: gap
I: insulating barrier
S: soldered ball
T, T1, T2: thickness
V: straight-through silicon wafer perforation structure
Embodiment
Figure 1A～Fig. 1 I illustrates the profile of the packaging technology of the embodiment of the invention.
At first, please refer to Figure 1A, loading plate 110 is provided, the shape of loading plate 110 and large I are similar in appearance to wafer.Dispose adhesion coating 120 on the loading plate 110.Then, a plurality of the first semiconductor elements 130 are disposed on the adhesion coating 120, and these the first semiconductor elements 130 are separated from one another and see through respectively adhesion coating 120 and be fixed on the loading plate 110.In the present embodiment, a plurality of conductive projections 132 of the first chip 130 can be embedded in the adhesion coating 120.
Specifically, in the present embodiment, before being disposed at the first semiconductor element 130 on the adhesion coating 120, can in the first semiconductor element 130, form first the perforate 138 of a plurality of high-aspect-ratios, and form insulating barrier I at the inwall of perforate 138, then, in each perforate 138, insert electric conducting material D, and insulating barrier I is separated between the inwall of electric conducting material D and perforate 138, afterwards, just forms conductive projection 132 at each electric conducting material D.
Then, please refer to Figure 1B, for example form the first packing colloid 140 with printing (printing) or the mode of pressing mold (molding) at loading plate 110, wherein the first packing colloid 140 covers the sidewall 134 of the first semiconductor element 130 and fills up clearance G 1 between the first semiconductor element 130, so that the first semiconductor element 130 and the first packing colloid 140 formation chip array plate A.Particularly, in the present embodiment, chip array plate A refers to the platy structure that is made of the first packing colloid 140 and the first whole semiconductor elements 130.
Afterwards, please refer to Fig. 1 C, in the present embodiment, but grinding chip array board A, with thinned chip array board A and expose electric conducting material D.In the present embodiment, but grinding chip array board A until the thickness T of chip array plate A is less than or equal in fact 4 Mills.In the present embodiment, electric conducting material D, insulating barrier I and perforate 138 can consist of straight-through silicon wafer perforation (Through-Silicon Via, TSV) structure V.
By as can be known aforementioned, the first semiconductor element 130 is to adopt straight-through silicon wafer perforation (Through-SiliconVia, TSV) technology to come to be electrically connected with conductive projection 132 and other chips (not illustrating) that will be stacked in afterwards on the first semiconductor element 130.Straight-through silicon wafer puncturing technique for example is at chip or wafer internal production conductive channel, and to form vertical straight-through silicon wafer perforation structure V, it can make the first semiconductor element 130 minimize in stacking density maximization and the overall dimension of three-dimensional.Therefore, the first semiconductor element 130 and will be stacked in afterwards signal between other chips on the first semiconductor element 130 and can see through straight-through silicon wafer perforation structure V and transmit up and down is to reduce the signal transmission path length between the chip and to reduce signal delay and power consumption.
Then, please refer to Fig. 1 D, in the present embodiment, can form a plurality of primers separated from one another 150 in the mode of for example putting glue or screen printing on chip array plate A, wherein each primer 150 covers the part around the first corresponding semiconductor element 130 of the first corresponding semiconductor element 130 and the first packing colloid 140.Specifically, each primer 150 not only covers the first corresponding semiconductor element 130 fully, also covers the part around the first corresponding semiconductor element 130 of the first packing colloid 140.In other words, primer 150 in the projected area on the loading plate 110 greater than the projected area of the first semiconductor element 130 on loading plate 110.The material of primer 150 comprises non-conductive joint glue (non-contactpaste, NCP1) or non-conductive junction film (non-contact film, NCF1).
Then, please refer to Fig. 1 E, with a plurality of the second semiconductor elements 160 respectively on flip-chip bonded to the first semiconductor elements 130, so that a plurality of conductive projections 162 of each second semiconductor element 160 engage with the straight-through silicon wafer perforation structure V of corresponding the first semiconductor element 130 by corresponding primer 150.In the present embodiment, the second semiconductor element 160 in the projected area on the loading plate 110 greater than the projected area of the first semiconductor element 130 on loading plate 110.In other words, the size of the second semiconductor element 160 is greater than the size of the first semiconductor element 130.
Afterwards; please refer to Fig. 1 F; for example form the second packing colloid 170 with printing or the mode of pressing mold at chip array plate A; the second packing colloid 170 optionally cover the sidewall 164 of the second semiconductor element 160 and the second semiconductor element 160 away from the end face 166 of the first semiconductor element 130 of correspondence and fill up clearance G 2 between the second semiconductor element 160, to protect the second semiconductor element 160.It should be noted that, because the second packing colloid 170 fills up the clearance G 2 between the second semiconductor element 160, therefore, the second packing colloid 170 can be strengthened the quite little chip array plate A of thickness, firmly to link the second whole semiconductor elements 160 and the first whole semiconductor elements 130.In addition, in other embodiments, can insert mode between the second semiconductor element 160 and the chip array plate A by the second packing colloid 170 that makes part, replace the step that forms primer 150.
Then, please refer to Fig. 1 G, separating chips array board A and adhesion coating 120.Afterwards, please be simultaneously with reference to Fig. 1 G and Fig. 1 H, along clearance G 2 cutting the second packing colloid 170 and the first packing colloids 140 between the second semiconductor element 160, to form a plurality of chip packaging unit C1.
By as can be known aforementioned, the present embodiment chip array plate A that first a plurality of the first semiconductor element 130 usefulness the first packing colloids 140 is formed by connecting, again a plurality of the second semiconductor elements 160 are disposed at respectively afterwards on the first semiconductor element 130 of chip array plate A and with 170 connections of the second packing colloid, then cut the first packing colloid 140 and the second packing colloid 170 and form a plurality of chip packaging unit C1.In other words, the present embodiment utilizes the first packing colloid 140 to fix with the second packing colloid 170 and is connected the first semiconductor element 130 and the second semiconductor element 160, afterwards again by cutting the first packing colloid 140 and the second packing colloid 170 forms a plurality of chip packaging unit C1.
Thus, the present embodiment can not be subject to the size relationship of the first semiconductor element 130 and the second semiconductor element 160, that is the present embodiment size that can make the first semiconductor element 130 more than or equal to or less than the chip packaging unit C1 of the size of the second semiconductor element 160.In other words, the present embodiment can make by the mutual stacking encapsulating structure that forms of the chip of various sizes.In addition, because the second packing colloid 170 can be strengthened the quite little chip array plate A of thickness, therefore can form in the process of chip packaging unit C1 in the mode with cutting, avoid chip array plate A cracked, thus the lifting process yield.
Then, please be simultaneously with reference to Fig. 1 H and Fig. 1 I, in the present embodiment, can form primer 190 at circuit base plate 180 (for example printed circuit board (PCB)), and chip packaging unit C1 can be disposed on the circuit base plate 180, so that the first semiconductor element 130 can see through conductive projection 132 electrically with structural connection line substrates 180, and make primer 190 conductive projection 132 to coat the first semiconductor element 130 between the first semiconductor element 130 of chip packaging unit C1 and circuit base plate 180.
Please refer to Fig. 1 I, in the present embodiment, for example form the 3rd packing colloid M with printing or the mode of pressing mold at circuit base plate 180, the 3rd packing colloid M can cover the sidewall W of chip packaging unit C1 and the end face 166 of the second semiconductor element 160.Specifically, the 3rd packing colloid M of part is positioned on the part of covering end face 166 of the second packing colloid 170, and in other words, the 3rd packing colloid M covers the end face 166 of the second semiconductor element 160 indirectly.In the embodiment that other do not illustrate, the 3rd packing colloid M can cover the sidewall W of chip packaging unit C1 and expose the part of the covering end face 166 of the second packing colloid 170.
In addition, in other embodiments, can insert by the 3rd packing colloid M that makes part the mode between the first semiconductor element 130 and the circuit base plate 180, replace the step that forms primer 190.In addition, be electrically connected to other electronic component for making chip packaging unit C1 can see through circuit base plate 180, can form a plurality of soldered ball S in the bottom surface 182 away from chip packaging unit C1 of circuit base plate 180, and soldered ball S and circuit base plate 180 electric connections.At this moment, tentatively finish the encapsulating structure 100 of the present embodiment.
Below will introduce in detail the encapsulating structure 100 of Fig. 1 I.
Please refer to Fig. 1 I, the encapsulating structure 100 of the present embodiment comprises the first semiconductor element 130, the first packing colloid 140, the second semiconductor element 160 and the second packing colloid 170.In the present embodiment, the thickness T 2 of the first semiconductor element 130 is less than or equal in fact 4 Mills, and for instance, the thickness T 2 of the first semiconductor element 130 is essentially 2 Mills.
The first packing colloid 140 coats the sidewall 134 of the first semiconductor element 130.In the present embodiment, the end face 144 towards the second semiconductor element 160 of the first packing colloid 140 can trim the end face 136 towards the second semiconductor element 160 in the first semiconductor element 130, and the thickness T 1 of the first packing colloid 140 can equal in fact the thickness T 2 of the first semiconductor element 130.
The second semiconductor element 160 is disposed on the first semiconductor element 130 and part the first packing colloid 140, and the size of the second semiconductor element 160 is greater than the size of the first semiconductor element 130.In other words, the second semiconductor element 160 towards the area of the bottom surface 168 of the first semiconductor element 130 area greater than the end face 136 of the first semiconductor element 130.
It should be noted that, the encapsulating structure 100 of the present embodiment be with larger-size chip configuration on the less chip of size, therefore, encapsulating structure 100 can be suitable for being used in the encapsulating structure that the large size chips such as memory chip is disposed on the small-size chips such as compute chip.In addition, because the thickness T 2 less (for example being less than or equal to 4 Mills) of first semiconductor element 130 of the present embodiment, therefore can reduce the integral thickness of encapsulating structure 100.
The second packing colloid 170 covers the sidewall 164 of the second semiconductor element 160, end face 166 and first packing colloid 140 away from the first semiconductor element 130 of the second semiconductor element 160, wherein the first packing colloid 140 and the second packing colloid 170 can be each self-forming, and the sidewall 142 of the first packing colloid 140 can trim the sidewall 172 in the second packing colloid 170.
In the present embodiment, dispose a plurality of conductive projections 162 on the bottom surface 168 of the second semiconductor element 160, to be electrically connected to the first semiconductor element 130.Be protection conductive projection 162, can be configuring primer 150 between the second semiconductor element 160 and the first semiconductor element 130 and between the second semiconductor element 160 and the first packing colloid 140, so that primer 150 coated with conductive projections 162.In addition, in other embodiments, also can be without primer 150, also can make part the second packing colloid 170 be filled between the second semiconductor element 160 and the first semiconductor element 130 and between the second semiconductor element 160 and the first packing colloid 140 and needn't configure primer 150.
In the present embodiment, the first semiconductor element 130 is configurable on circuit base plate 180, so that a plurality of conductive stud of the first semiconductor element 130 certainly 132 are electrically connected to circuit base plate 180.Determine 132 for the protection conductive stud, can between the first semiconductor element 130 and circuit base plate 180, configure primer 190, so that primer 190 coated with conductive projections 132.
In addition, in the present embodiment, can be at circuit base plate 180 configurations the 3rd packing colloid M, the 3rd packing colloid M covers the sidewall 142 of the first packing colloid 140, the sidewall 172 of the second packing colloid 170 and the end face 166 away from the first semiconductor element 130 of the second semiconductor element 160.Specifically, the 3rd packing colloid M of part is positioned on the part of end face 166 of covering the second semiconductor element 160 of the second packing colloid 170, and in other words, the 3rd packing colloid M covers end face 166 indirectly.In other embodiments, the 3rd packing colloid M can cover the sidewall 142 of the first packing colloid 140 and the sidewall 172 of the second packing colloid 170, and exposes the part of end face 166 of covering second semiconductor element 160 of the second packing colloid 170.In addition, in other embodiments, also can be without primer 190, part the 3rd packing colloid M is filled between the first semiconductor element 130 and the circuit base plate 180 and primer 190 needn't be configures.
In addition, may be configured with a plurality of soldered ball S on the bottom surface 182 away from the first semiconductor element 130 of circuit base plate 180, soldered ball S and circuit base plate 180 are electrically connected, and circuit base plate 180 can be electrically connected to through soldered ball S other electronic component (for example wiring board).
Fig. 2 A～Fig. 2 D illustrates the profile of the packaging technology of another embodiment of the present invention.
In the present embodiment; can carry out first the technique of Figure 1A～Fig. 1 E; afterwards; please refer to Fig. 2 A; form the second packing colloid 210 at chip array plate A; the second packing colloid 210 optionally covers the sidewall 164 of the second semiconductor element 160 and exposes the end face 166 away from the first semiconductor element 130 of correspondence of the second semiconductor element 160, and fills up the clearance G 2 between the second semiconductor element 160, to protect the second semiconductor element 160.
Then, please refer to Fig. 2 B, separating chips array board A and adhesion coating 120.Afterwards, please be simultaneously with reference to Fig. 2 B and Fig. 2 C, along clearance G 2 cutting the second packing colloid 170 and the first packing colloids 140 between the second semiconductor element 160, to form a plurality of chip packaging unit C2.Then, in the present embodiment, can form primer 190 at circuit base plate 180.
Then, please be simultaneously with reference to Fig. 2 C and Fig. 2 D, in the present embodiment, chip packaging unit C2 can be disposed on the circuit base plate 180, so that the first semiconductor element 130 see through conductive projection 132 electrically with structural connection line substrates 180, and make primer 190 conductive projection 132 to coat the first semiconductor element 130 between the first semiconductor element 130 of chip packaging unit C2 and circuit base plate 180.
Please refer to Fig. 2 D, in the present embodiment, can form the end face 166 that the 3rd packing colloid 220, the three packing colloids 220 can cover the sidewall W1 of chip packaging unit C2 and expose the second semiconductor element 160 at circuit base plate 180.At this moment, tentatively finish the encapsulating structure 200 of the present embodiment.In addition, in the embodiment that other do not illustrate, the 3rd packing colloid 220 can cover the sidewall W1 of chip packaging unit C2 and the end face 166 of the second semiconductor element 160.
Below will introduce in detail the structure division of the encapsulating structure 200 of Fig. 2 D.
Please refer to Fig. 2 D, the encapsulating structure 200 of the present embodiment is similar to the encapsulating structure 100 of Fig. 1 I, both difference parts be the second packing colloid 210 of encapsulating structure 200 and the 3rd packing colloid 220 jointly expose the second semiconductor element 160 end face 166.Therefore, the end face 166 that encapsulating structure 200 can see through the second semiconductor element 160 conducts to external environment with the heat that the first semiconductor element 130 and the second semiconductor element 160 produce when the running, and then the radiating efficiency of lifting encapsulating structure 200.
In sum, the present invention utilizes first the first packing colloid to fix with the second packing colloid and is connected the first semiconductor element and the second semiconductor element, afterwards again by cutting the first packing colloid and the second packing colloid forms a plurality of chip packaging units.Therefore, the present invention can make by the mutual stacking encapsulating structure that forms of the chip of various sizes.In addition, because the second packing colloid can be strengthened the quite little chip array plate of thickness, therefore can firmly link the second whole semiconductor elements and the first whole semiconductor elements, and can form in the process of chip packaging unit in the mode with cutting, avoid the chip array plate cracked, thus the lifting process yield.
Although the present invention discloses as above with embodiment; so it is not to limit the present invention; those of ordinary skill in the technical field under any; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, therefore protection scope of the present invention defines and is as the criterion when looking appended claim.

Claims (6)

1. packaging technology comprises:
Loading plate is provided, disposes adhesion coating on this loading plate;
A plurality of the first semiconductor elements are disposed on this adhesion coating, and these a plurality of first semiconductor elements are separated from one another and see through respectively this adhesion coating is fixed on this loading plate, wherein respectively this first semiconductor element has a plurality of straight-through silicon wafer perforation structures;
Form the first packing colloid at this loading plate, this first packing colloid covers the sidewall of these a plurality of the first semiconductor elements and fills up gap between these a plurality of first semiconductor elements, so that these a plurality of first semiconductor elements and this first packing colloid form the chip array plate;
After forming this chip array plate, grind this chip array plate, with this chip array plate of thinning and expose the respectively end face of these a plurality of straight-through silicon wafer perforation structures of this first semiconductor element;
A plurality of the second semiconductor elements are distinguished flip-chip bonded to these a plurality of first semiconductor elements of this chip array plate, so that this end joined of a plurality of conductive projections of this second semiconductor element and these a plurality of straight-through silicon wafer perforation structures of corresponding respectively this first semiconductor element respectively, wherein this second semiconductor element in the projected area on this loading plate greater than the projected area of this first semiconductor element on this loading plate;
Form the second packing colloid at this chip array plate, this second packing colloid covers at least the sidewall of these a plurality of the second semiconductor elements and fills up gap between these a plurality of second semiconductor elements;
Separate this chip array plate and this adhesion coating; And
Cut this second packing colloid and this first packing colloid along the gap between these a plurality of second semiconductor elements, to form a plurality of chip packaging units.
2. packaging technology as claimed in claim 1, the method for wherein grinding this chip array plate comprises:
Grind this chip array plate until the thickness of this chip array plate is less than or equal in fact 4 Mills.
3. packaging technology as claimed in claim 1 also comprises:
After forming this chip array plate, on these a plurality of first semiconductor elements, form respectively a plurality of the first primers separated from one another, wherein respectively this first primer covers the part around this corresponding the first semiconductor element of this corresponding first semiconductor element and this first packing colloid, and should be a plurality of the second semiconductor elements when flip-chip bonded are to this a plurality of first semiconductor elements respectively, respectively a plurality of conductive projections of this second semiconductor element by this corresponding first primer with corresponding this first semiconductor element joint.
4. packaging technology as claimed in claim 1 also comprises:
This chip packaging unit is disposed on the circuit base plate, so that this first semiconductor element electric and structural this circuit base plate that is connected.
5. packaging technology as claimed in claim 4 also comprises:
Form the second primer at this circuit base plate, so that this second primer is between this first semiconductor element of this chip packaging unit and this circuit base plate and coat a plurality of conductive projections of this first semiconductor element.
6. packaging technology as claimed in claim 4 also comprises:
Form the 3rd packing colloid at this circuit base plate, the 3rd packing colloid covers the sidewall of this chip packaging unit at least.
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