CN102044447B - Packaging technology and packaging structure - Google Patents

Packaging technology and packaging structure Download PDF

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CN102044447B
CN102044447B CN 200910174057 CN200910174057A CN102044447B CN 102044447 B CN102044447 B CN 102044447B CN 200910174057 CN200910174057 CN 200910174057 CN 200910174057 A CN200910174057 A CN 200910174057A CN 102044447 B CN102044447 B CN 102044447B
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semiconductor element
encapsulant
plurality
chip
semiconductor
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CN102044447A (en )
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沈启智
陈仁川
潘彦良
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日月光半导体制造股份有限公司
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    • HELECTRICITY
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    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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Abstract

本发明涉及一种封装工艺及封装结构。 The present invention relates to a packaging structure and packaging process. 该封装工艺如下所述。 The packaging process as described below. 首先,提供承载板,承载板上配置有粘着层。 First, a carrier plate, adhesive layer disposed on the carrier sheet. 接着,将多个第一半导体元件配置于粘着层上。 Next, a plurality of first semiconductor elements disposed on the adhesive layer. 然后,在承载板上形成第一封装胶体,第一封装胶体覆盖第一半导体元件的侧壁并填满第一半导体元件之间的间隙,以使第一半导体元件与第一封装胶体形成芯片阵列板。 Then, a first encapsulant on the carrier plate, a first sidewall of the first encapsulant covering the semiconductor element and fill the gap between the first semiconductor element to the first element and the first semiconductor chip array formed encapsulant board. 之后,将多个第二半导体元件分别倒装接合至第一半导体元件上。 Thereafter, the plurality of second semiconductor elements are flip-chip bonded onto the first semiconductor element. 接着,在芯片阵列板上形成第二封装胶体,第二封装胶体至少覆盖第二半导体元件的侧壁并填满第二半导体元件之间的间隙。 Next, a second encapsulant in chip array plate, the second encapsulant covering at least a sidewall of the second semiconductor element and fill the gap between the second semiconductor element. 然后,分离芯片阵列板与粘着层。 Then, the separation chip array panel and the adhesive layer. 之后,沿着第二半导体元件之间的间隙切割第二封装胶体与第一封装胶体。 Thereafter, along the gap between the second semiconductor element with a first cutting a second encapsulant encapsulant.

Description

封装工艺及封装结构技术领域 Packaging and packaging process TECHNICAL FIELD

[0001] 本发明涉及一种封装工艺及封装结构,且特别是涉及一种将大芯片配置于小芯片上的封装工艺及封装结构。 [0001] The present invention relates to a packaging structure and packaging process, and in particular relates to a large chip disposed on the small chip packaging structure and packaging process.

背景技术 Background technique

[0002] 在现今的资讯社会中,使用者均追求高速度、高品质、多功能性的电子产品。 [0002] In today's information society, users are pursuing high speed, high quality and versatility of electronic products. 就产品外观而言,电子产品的设计是朝向轻、薄、短、小的趋势迈进。 On product appearance, the electronic product design is toward light, thin, short, small tendency to move. 因此,电子封装技术发展出诸如堆叠式芯片封装等多芯片封装技术。 Thus, the electronic packaging technology, such as stacked multi-chip package technology chip packaging.

[0003] 堆叠式芯片封装利用垂直堆叠的方式将多个芯片封装于同一封装结构中,如此可提升封装密度以使封装体小型化,且可利用立体堆叠的方式缩短芯片之间的信号传输的路径长度,以提升芯片之间信号传输的速度,并可将不同功能的芯片组合于同一封装体中。 [0003] The stacked chip package using the plurality of vertically stacked manner in the same chip package in a package structure, so the packing density can be improved so that the size of the package, and may utilize a perspective manner shorten signal transmission between stacked chips the path length to improve the speed of signal transmission between chips, and combinations of the different functions of the chip in the same package.

[0004] 已知的堆叠式芯片封装的制作方法是先将多个倒装芯片接合至晶片上,然后沿这些芯片之间的间隙切割晶片,以形成多个芯片堆叠结构,之后再将芯片堆叠结构配置于线路板上并在线路板上形成封装胶体,以保护芯片堆叠结构。 [0004] Known stacked chip package production method is flip-chip bonded to the first plurality of the wafer, and then dicing the wafer along the gap between the chips, a plurality of chips to form a stack structure, and then after the chip stack structure is disposed on the circuit board and the circuit board forming an encapsulant to protect the chip stack structure.

[0005] 由于已知的堆叠式芯片封装的制作方法是通过切割晶片的方式来形成多个芯片堆叠结构,因此,在芯片堆叠结构中,由切割晶片所形成的芯片的尺寸势必大于接合至晶片上的倒装芯片的尺寸。 [0005] Since it is known a stacked chip package fabrication method for a plurality of chip stacking structure is formed by means of dicing the wafer, and therefore, the chip stack structure, the size of the chip formed by the cutting of wafer to wafer bonded bound greater than on the size of the flip chip. 因此,已知的堆叠式芯片封装的制作方法只能形成将小尺寸芯片配置于大尺寸芯片上的封装结构。 Thus, the known method for fabricating a stacked chip package can be formed small size of the chip is disposed on the large chip size package structure.

[0006] 此外,已知技术为减少堆叠式芯片封装的整体厚度,会在将倒装芯片接合至晶片上之前,先研磨晶片,以减少晶片的厚度。 [0006] In addition, the prior art to reduce the overall thickness of the stacked chip package, prior to flip chip will be bonded to the wafer, the first wafer is polished to reduce the thickness of the wafer. 然而,目前倒装接合技术仍有工艺能力上的极限值,因此,当所使用的晶片厚度小于其工艺能力的极限值时,在进行倒装接合的过程中,容易发生破片的情形,以致于工艺良率降低。 However, the current limit value on the flip-chip bonding technique is still the ability to process, and therefore, when the thickness of the wafer used in less than the limit of its ability to process, the process of performing flip-chip bonding, a situation prone to fragmentation, so that the process yields lower. 此外,厚度小的晶片在切割工艺中容易破裂,以致于工艺良率降低。 Further, a small thickness is easily broken in the wafer cutting process, so as to reduce the process yield.

发明内容 SUMMARY

[0007] 本发明提供一种封装工艺,可制作由各种尺寸的芯片相互堆叠而成的封装结构,且工艺良率高。 [0007] The present invention provides a packaging process may be made of various sizes made of mutually chip stack package, and the process is good rate.

[0008] 本发明提供一种封装结构,其将大尺寸芯片配置于小尺寸芯片上。 [0008] The present invention provides a package structure, a large size chip is disposed on a small chip size.

[0009]为具体描述本发明的内容,在此提出一种封装工艺如下所述。 [0009] The present invention is specifically described in this paper proposes a packaging process as described below. 首先,提供承载板,承载板上配置有粘着层。 First, a carrier plate, adhesive layer disposed on the carrier sheet. 接着,将多个第一半导体元件配置于粘着层上,且第一半导体元件彼此分离并分别透过粘着层固定于承载板上。 Next, the plurality of semiconductor elements disposed on the first adhesive layer and the first semiconductor element are separated from each other through the adhesive layer and fixed to the carrier plate. 然后,在承载板上形成第一封装胶体,第一封装胶体覆盖第一半导体元件的侧壁并填满第一半导体元件之间的间隙,以使第一半导体元件与第一封装胶体形成芯片阵列板。 Then, a first encapsulant on the carrier plate, a first sidewall of the first encapsulant covering the semiconductor element and fill the gap between the first semiconductor element to the first element and the first semiconductor chip array formed encapsulant board. 之后,将多个第二半导体元件分别倒装接合至第一半导体元件上。 Thereafter, the plurality of second semiconductor elements are flip-chip bonded onto the first semiconductor element. 接着,在芯片阵列板上形成第二封装胶体,第二封装胶体至少覆盖第二半导体元件的侧壁并填满第二半导体元件之间的间隙。 Next, a second encapsulant in chip array plate, the second encapsulant covering at least a sidewall of the second semiconductor element and fill the gap between the second semiconductor element. 然后,分离芯片阵列板与粘着层。 Then, the separation chip array panel and the adhesive layer. 之后,沿着第二半导体元件之间的间隙切割第二封装胶体与第一封装胶体,以形成多个芯片封装单J Li ο Thereafter, along the gap between the second semiconductor element with a first cutting a second encapsulant encapsulant, to form a plurality of single chip packages J Li ο

[0010] 在本发明的实施例中,上述的第一半导体元件具有多个直通硅晶穿孔结构,且封装工艺还包括在形成芯片阵列板之后,研磨芯片阵列板,以薄化芯片阵列板并露出第一半导体元件的直通硅晶穿孔结构的端面。 [0010] In an embodiment of the present invention, said first semiconductor element having a plurality of through silicon via structure, and further comprising a packaging process, after forming the chip array plate, the polishing chip array panel, to thin chip array plate and TSV exposed end surfaces of the first semiconductor element structure.

[0011] 在本发明的实施例中,上述的研磨芯片阵列板的方法包括研磨芯片阵列板直到芯片阵列板的厚度实质上小于或等于4密尔。 [0011] In an embodiment of the present invention, the above-described polishing methods include polishing chip array chip array plate until the plate thickness of the chip array plate is substantially equal to or less than 4 mils.

[0012] 在本发明的实施例中,上述的封装工艺还包括在形成芯片阵列板之后,在第一半导体元件上分别形成多个彼此分离的第一底胶,其中各第一底胶覆盖对应的第一半导体元件以及第一封装胶体的围绕对应的第一半导体元件的部分,且在将第二半导体元件分别倒装接合至第一半导体元件上时,各第二半导体元件的多个导电凸块通过对应的第一底胶而与对应的第一半导体元件接合。 [0012] In an embodiment of the present invention, the above-mentioned packaging process further comprising, after forming the chip array plate, a plurality of first primer separated from each other on the first semiconductor element, respectively, wherein each of the first to cover the corresponding primer a first semiconductor element and a semiconductor element corresponding to a first portion surrounding a first encapsulant, and when the second semiconductor element are flip-chip bonded onto the first semiconductor element, a plurality of conductive projections each second semiconductor element engagement with the corresponding blocks of the first semiconductor element corresponding to the first primer. [0013] 在本发明的实施例中,上述的封装工艺还包括将芯片封装单元配置于线路基板上,以使第一半导体元件电性与结构性连接线路基板。 [0013] In an embodiment of the present invention, the above process further comprises packaging the chip package on a circuit substrate unit is disposed so that the first semiconductor element is electrically connected to the circuit substrate structured.

[0014] 在本发明的实施例中,上述的封装工艺还包括在线路基板上形成第二底胶,以使第二底胶位于芯片封装单元的第一半导体元件与线路基板之间并包覆第一半导体元件的多个导电凸块。 [0014] In an embodiment of the present invention, the above-mentioned packaging process line further comprises a second circuit board for forming the primer, the second primer is located such that the cells of the first chip package and the circuit board between the semiconductor element and cover a first plurality of conductive bumps of the semiconductor element.

[0015] 在本发明的实施例中,上述的封装工艺还包括在线路基板上形成第三封装胶体,第三封装胶体至少覆盖芯片封装单元的侧壁。 [0015] In an embodiment of the present invention, the above-mentioned packaging process further comprises forming a third circuit board for online encapsulant, the third encapsulant covering at least a sidewall of the chip package unit.

[0016] 为具体描述本发明的内容,在此提出一种封装结构包括第一半导体元件、第一封装胶体、第二半导体元件以及第二封装胶体。 [0016] The detailed description of the present invention, a package structure proposed here comprises a first semiconductor element, a first encapsulant, a second semiconductor element, and a second encapsulant. 第一封装胶体包覆第一半导体元件的侧壁。 A first sidewall of the first encapsulant covering the semiconductor element. 第二半导体元件配置于第一半导体元件与部分第一封装胶体上,且第二半导体元件的尺寸大于第一半导体元件的尺寸。 A second semiconductor element disposed on a first portion of the first semiconductor element and the encapsulant, and the size of the second semiconductor element is larger than that of the first semiconductor element. 第二封装胶体至少覆盖第二半导体元件的侧壁以及第一封装胶体,其中第一封装胶体与第二封装胶体为各自成型。 Second encapsulant covering at least a first sidewall and a second semiconductor element encapsulant, wherein the first encapsulant and the second encapsulant are each formed.

[0017] 在本发明的实施例中,上述的第一封装胶体的侧壁切齐于第二封装胶体的侧壁。 [0017] In an embodiment of the present invention, the sidewall of the first encapsulant is cut flush to a sidewall of the second encapsulant.

[0018] 在本发明的实施例中,上述的第一封装胶体的朝向第二半导体元件的第一顶面切齐于第一半导体元件的朝向第二半导体元件的第二顶面。 [0018] In an embodiment of the present invention, the first top surface of the encapsulant of the first semiconductor element towards the second cut flush to the top surface of the second semiconductor element towards the second semiconductor element to the first.

[0019] 在本发明的实施例中,上述的第一封装胶体的厚度实质上等于第一半导体元件的厚度。 [0019] In an embodiment of the present invention, the thickness of the first encapsulant is substantially equal to the thickness of the first semiconductor element.

[0020] 在本发明的实施例中,上述的第二半导体元件具有位于第二半导体元件与第一半导体元件之间的多个导电凸块,且封装结构还包括底胶,其配置于第二半导体元件与第一半导体元件之间以及第二半导体元件与第一封装胶体之间,以包覆第二半导体元件的导电凸块。 [0020] In an embodiment of the present invention, the above-described second semiconductor element having a plurality of conductive bumps located on the second semiconductor element and between the first semiconductor element, and the package structure further comprises a primer, which is disposed on the second between the first semiconductor element and the semiconductor element and the second semiconductor element and the first encapsulant, so as to cover the conductive bump of the second semiconductor element.

[0021] 在本发明的实施例中,上述的第一半导体元件的厚度实质上小于或等于4密尔。 [0021] In an embodiment of the present invention, the thickness of the first semiconductor element is substantially equal to or less than 4 mils.

[0022] 在本发明的实施例中,上述的第二封装胶体还覆盖第二半导体元件的远离第一半导体元件的顶面。 [0022] In an embodiment of the present invention, the above-described second encapsulant also covers the top surface of the first semiconductor element remote from the second semiconductor element.

[0023] 在本发明的实施例中,上述的第二封装胶体暴露出第二半导体元件的远离第一半导体元件的顶面。 [0023] In an embodiment of the present invention, the above-described second encapsulant to expose the top surface of the first semiconductor element remote from the second semiconductor element.

[0024] 在本发明的实施例中,上述的第一半导体元件的远离第二半导体元件的底面上配置有多个导电凸块。 [0024] In an embodiment of the present invention, the configuration of the second semiconductor element remote from the bottom surface of the first semiconductor element has a plurality of conductive bumps. [0025] 在本发明的实施例中,上述的封装结构还包括线路基板,第一半导体元件配置于线路基板上,且导电凸块位于第一半导体元件与线路基板之间。 [0025] In an embodiment of the present invention, the above-described package structure further comprises a wiring substrate, a first semiconductor element is disposed on the circuit substrate and the conductive bumps located between the first semiconductor element and the wiring substrate.

[0026] 在本发明的实施例中,上述的封装结构还包括底胶,其配置于第一半导体元件与线路基板之间,以包覆导电凸块。 [0026] In an embodiment of the present invention, the above-described package structure further comprises a primer, which is disposed between the first semiconductor element and the circuit substrate to cover the conductive bumps.

[0027] 在本发明的实施例中,上述的封装结构还包括第三封装胶体,其配置于线路基板上,并至少覆盖第一封装胶体的侧壁与第二封装胶体的侧壁。 [0027] In an embodiment of the present invention, the above-described package structure further comprises a third encapsulant, disposed on a circuit board, and covers at least the sidewalls of the first encapsulant and the second encapsulant.

[0028] 基于上述,本发明可制得由各种尺寸的芯片相互堆叠而成的封装结构。 [0028] Based on the above, the present invention can be prepared by a variety of chip size package structure formed by stacking one another. 此外,由于第二封装胶体可强化厚度相当小的芯片阵列板,故可稳固地连结全部的第二半导体元件以及全部的第一半导体元件,并可在以切割的方式形成芯片封装单元的过程中,避免芯片阵列板碎裂,从而提升工艺良率。 Furthermore, the process may be reinforced since the thickness of the second encapsulant relatively small chip array plate, it can be firmly connected to all of the second semiconductor element and all of the first semiconductor element, and may be formed in a manner to cut a chip package unit , to avoid chipping chip array panel, thereby improving process yield.

[0029] 为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合附图作详细说明如下。 [0029] In order to make the above features and advantages of the invention more comprehensible, several embodiments accompanied with figures are described in detail below.

附图说明 BRIEF DESCRIPTION

[0030] 图IA〜图II绘示本发明实施例的封装工艺的剖面图。 [0030] FIG IA~ II FIG schematic sectional view showing a packaging process embodiment of the present invention embodiment.

[0031] 图2A〜图2D绘示本发明另一实施例的封装工艺的剖面图。 [0031] FIG 2A~ FIG. 2D illustrates a cross-sectional view of a package according to another embodiment of the process of the present invention.

[0032] 附图标记说明 [0032] REFERENCE NUMERALS

[0033] 100、200 :封装结构 [0033] 100, 200: packaging structure

[0034] 110:承载板 [0034] 110: the carrier plate

[0035] 120 :粘着层 [0035] 120: adhesive layer

[0036] 130 :第一半导体元件 [0036] 130: a first semiconductor element

[0037] 132:导电凸块 [0037] 132: conductive bump

[0038] 134、142、164、172、W、Wl :侧壁 [0038] 134,142,164,172, W, Wl: sidewall

[0039] 136、144、166 :顶面 [0039] 136,144,166: a top surface

[0040] 138 :开孔 [0040] 138: Hole

[0041] 140 :第一封装胶体 [0041] 140: a first encapsulant

[0042] 150、190:底胶 [0042] 150, 190: primer

[0043] 160 :第二半导体元件 [0043] 160: a second semiconductor element

[0044] 162:导电凸块 [0044] 162: conductive bump

[0045] 168、182:底面 [0045] 168,182: a bottom surface

[0046] 170、210 :第二封装胶体 [0046] 170,210: a second encapsulant

[0047] 180 :线路基板 [0047] 180: circuit board

[0048] 220、M :第三封装胶体 [0048] 220, M: a third encapsulant

[0049] A :芯片阵列板 [0049] A: a chip array panel

[0050] C1、C2:芯片封装单元 [0050] C1, C2: a chip package unit

[0051] D :导电材料 [0051] D: a conductive material

[0052] G1、G2:间隙 [0052] G1, G2: gap

[0053] I :绝缘层 [0053] I: insulating layer

[0054] S :焊球[0055] T、T1、T2:厚度 [0054] S: ball [0055] T, T1, T2: thickness

[0056] V :直通硅晶穿孔结构 [0056] V: TSV structure

具体实施方式 detailed description

[0057] 图IA〜图II绘示本发明实施例的封装工艺的剖面图。 [0057] FIG IA~ II FIG schematic sectional view showing a packaging process embodiment of the present invention embodiment.

[0058] 首先,请参照图1A,提供承载板110,承载板110的形状与大小可相似于晶片。 [0058] First, referring to FIG. 1A, the carrier plate 110, the shape and size carrier plate 110 may be similar to the wafer. 承载板Iio上配置有粘着层120。 Iio upper carrier plate adhesion layer 120 is disposed. 接着,将多个第一半导体元件130配置于粘着层120上,且这些第一半导体元件130彼此分离并分别透过粘着层120固定于承载板110上。 Next, a plurality of first semiconductor element 130 is disposed on the adhesive layer 120, and the first semiconductor element 130 and are separated from each other through the adhesive layer 120 is fixed to the carrier plate 110. 在本实施例中,第一芯片130的多个导电凸块132可埋于粘着层120中。 In the present embodiment, 130 a first plurality of chip conductive bumps 132 may be buried in the adhesive layer 120. [0059] 详细而言,在本实施例中,在将第一半导体元件130配置于粘着层120上之前,可先在第一半导体元件130中形成多个高深宽比的开孔138,并在开孔138的内壁上形成绝缘层I,然后,在各开孔138中填入导电材料D,且绝缘层I分隔于导电材料D与开孔138的内壁之间,之后,才在各导电材料D上形成导电凸块132。 [0059] Specifically, in the present embodiment, prior to the first semiconductor element 130 is disposed on the adhesive layer 120, the first plurality of apertures may be a high aspect ratio 138 formed in the first semiconductor element 130, and the inner wall of the opening 138 is formed on the insulating layer I, and then, the conductive material filled in each opening 138 D, and the partition insulating layer I electrically conductive material D between the inner wall of the opening 138, only after each of the electrically conductive material the conductive bumps 132 are formed on D.

[0060] 然后,请参照图1B,例如以印刷(printing)或是压模(molding)的方式在承载板110上形成第一封装胶体140,其中第一封装胶体140覆盖第一半导体元件130的侧壁134并填满第一半导体元件130之间的间隙G1,以使第一半导体元件130与第一封装胶体140形成芯片阵列板A。 [0060] Then, referring to Figure 1B, for example, print (Printing) or die (Molding) manner as the first encapsulant 140 is formed on the carrier plate 110, wherein the first encapsulant 140 covers the first semiconductor element 130 side wall 134 and fills the gap G1 between the first semiconductor element 130, so that the first semiconductor element 130 and the first encapsulant 140 formed in a chip array panel A. 具体而言,在本实施例中,芯片阵列板A是指由第一封装胶体140以及全部的第一半导体元件130所构成的板状结构。 Specifically, in the present embodiment, a chip array plate A plate-like structure refers to the first encapsulant 140 and all of the first semiconductor element 130 constituted.

[0061] 之后,请参照图1C,在本实施例中,可研磨芯片阵列板A,以薄化芯片阵列板A并暴露出导电材料D。 After [0061], Referring to Figure 1C, in the present embodiment, the polishing chip array panel A, to thin chip array plate and expose the conductive material D. A 在本实施例中,可研磨芯片阵列板A直到芯片阵列板A的厚度T实质上小于或等于4密尔。 In the present embodiment, the chip array can be ground until the thickness of the plate A T A chip array plate is substantially equal to or less than 4 mils. 在本实施例中,导电材料D、绝缘层I与开孔138可构成直通硅晶穿孔(Through-SiIicon Via, TSV)结构V。 In the present embodiment, the conductive material D, the insulating layer I and the apertures 138 may be configured TSV (Through-SiIicon Via, TSV) structure V.

[0062] 由前述可知,第一半导体元件130是采用直通娃晶穿孔(Through-SiliconVia,TSV)技术来与导电凸块132以及之后将堆叠于第一半导体元件130上的其他芯片(未绘示)电性连接。 [0062] apparent from the foregoing, a first semiconductor element 130 is a straight-through baby TSV (Through-SiliconVia, TSV) techniques (not shown with the conductive bumps 132 and then the other chips stacked on the first semiconductor element 130 ) is electrically connected. 直通硅晶穿孔技术例如是在芯片或晶片内部制作导电通道,以形成垂直的直通硅晶穿孔结构V,其可使第一半导体元件130在三维方向的堆叠密度最大化且外形尺寸最小化。 TSV technology is produced, for example, a chip or wafer conductive vias inside, to form a vertical structure of the TSV V, which allows a first semiconductor element 130 are stacked in three dimensions to maximize density and minimize the dimensions. 因此,第一半导体元件130与之后将堆叠于第一半导体元件130上的其他芯片之间的信号可透过直通硅晶穿孔结构V来上下传递,以减少芯片之间的信号传输路径长度并减少信号延迟及功率消耗。 Thus, after the first semiconductor element 130 and the stacked signals between the first semiconductor chip on the other permeable element 130 TSV structures V to pass up and down to reduce the length of the signal transmission path between the chip and to reduce signal delay and power consumption.

[0063] 接着,请参照图1D,在本实施例中,可在芯片阵列板A上以例如点胶或网板印刷的方式形成多个彼此分离的底胶150,其中各底胶150覆盖对应的第一半导体元件130以及第一封装胶体140的围绕对应的第一半导体元件130的部分。 [0063] Next, referring to 1D, the embodiment in the present embodiment, for example, may be 150 to dispensing or screen printing formed of a plurality of separated from each other on the chip primer array panel A, in which each of the cover 150 corresponding to the primer 130 surrounds a portion of the first semiconductor element 130 corresponds to a first semiconductor element 140 and the first encapsulant. 详细而言,每一个底胶150不但完全覆盖对应的第一半导体元件130,还覆盖第一封装胶体140的围绕对应的第一半导体元件130的部分。 Specifically, each of a primer corresponding to 150 not only completely covers the first semiconductor element 130, also covers partially surround the first semiconductor element 130 corresponds to a first encapsulant 140. 换言之,底胶150在承载板110上的投影面积大于第一半导体元件130在承载板110上的投影面积。 In other words, the projected area of ​​150 primer on the carrier plate 110 is greater than the projected area of ​​the first semiconductor element 130 on the carrier plate 110. 底胶150的材料包括非导电性接合胶(non-contactpaste,NCPI)或非导电性接合膜(non-contact film, NCF1)。 Underfill material 150 includes a non-conductive bonding adhesive (non-contactpaste, NCPI) or non-conductive bonding film (non-contact film, NCF1).

[0064] 然后,请参照图1E,将多个第二半导体元件160分别倒装接合至第一半导体元件130上,以使各第二半导体元件160的多个导电凸块162通过对应的底胶150而与对应的第一半导体元件130的直通硅晶穿孔结构V接合。 [0064] Then, referring to 1E, the plurality of second semiconductor elements 160 are flip-chip bonded to the first semiconductor element 130, a second semiconductor element to the respective plurality of conductive bumps 160 through 162 corresponding primer 150 is engaged with TSV structure V corresponding to the first semiconductor element 130. 在本实施例中,第二半导体元件160在承载板Iio上的投影面积大于第一半导体元件130在承载板110上的投影面积。 In the present embodiment, the projected area of ​​the second semiconductor element 160 on the carrier plate Iio is larger than the projected area of ​​the first semiconductor element 130 on the carrier plate 110. 换言之,第二半导体元件160的尺寸大于第一半导体元件130的尺寸。 In other words, the size of the second semiconductor element 160 is greater than the size of the first semiconductor element 130.

[0065] 之后,请参照图1F,例如以印刷或是压模的方式在芯片阵列板A上形成第二封装胶体170,第二封装胶体170可选择性地覆盖第二半导体元件160的侧壁164以及第二半导体元件160的远离对应的第一半导体元件130的顶面166并填满第二半导体元件160之间的间隙G2,以保护第二半导体元件160。 After [0065] Please refer to 1F, a stamp or a printing example in the second embodiment of the encapsulant 170 formed on the chip array panel A, a second side wall 160 of the encapsulant 170 may selectively cover the second semiconductor element 164, and the top surface 166 of the first semiconductor element remote from the second semiconductor element 160 corresponds to 130 and 160 to fill a gap between the second semiconductor element G2, in order to protect the second semiconductor element 160. 值得注意的是,由于第二封装胶体170填满第二半导体元件160之间的间隙G2,因此,第二封装胶体170可强化厚度相当小的芯片阵列板A,以稳固地连结全部的第二半导体元件160以及全部的第一半导体元件130。 Notably, since the gap between the semiconductor element 160 of the second encapsulant 170 fills the second G2, and therefore, the second encapsulant 170 may be relatively small thickness of the reinforcing plate chip array A, firmly coupled to all of the second the semiconductor element 160, and all of the first semiconductor element 130. 此外,在其他实施例中,可通过使部分的第二封装胶体170填入第二半导体元件160与芯片阵列板A之间的方式,来取代形成底胶150的步骤。 Further, in other embodiments, by the second portion of the encapsulant 170 filled in the second embodiment between the semiconductor element 160 and the chip array panel A, instead of step 150 of forming the primer.

[0066] 然后,请参照图1G,分离芯片阵列板A与粘着层120。 [0066] Then, referring to FIG. 1G, A separation chip array panel 120 and the adhesive layer. 之后,请同时参照图IG与图1H,沿着第二半导体元件160之间的间隙G2切割第二封装胶体170与第一封装胶体140,以形成多个芯片封装单元Cl。 Thereafter, referring to FIG. IG and 1H, the semiconductor element along the second gap G2 between the second encapsulant 160 cut the first encapsulant 170 and 140 to form a plurality of chip packaging cells Cl.

[0067] 由前述可知,本实施例先将多个第一半导体元件130用第一封装胶体140连接而成芯片阵列板A,之后再将多个第二半导体元件160分别配置于芯片阵列板A的第一半导体元件130上并用第二封装胶体170连接,然后切割第一封装胶体140与第二封装胶体170而形成多个芯片封装单元Cl。 [0067] From the foregoing, the present first embodiment, a plurality of the first semiconductor element 130 is connected with a first encapsulant 140 from chip array panel A, then after a plurality of second semiconductor elements 160 are arranged in a chip array panel A a first semiconductor element 130 and the second encapsulant 170 is connected with, and then cutting the first encapsulant 140 and the second encapsulant 170 is formed a plurality of chip packaging cells Cl. 换言之,本实施例利用第一封装胶体140与第二封装胶体170来固定并连接第一半导体元件130与第二半导体元件160,之后再通过切割第一封装胶体140与第二封装胶体170来形成多个芯片封装单元Cl。 In other words, the present embodiment utilizes a first encapsulant 140 and the second encapsulant 170 is fixed to the first semiconductor element and the connection 130 and the second semiconductor element 160, after cutting through the first encapsulant 140 and the second encapsulant 170 formed a plurality of chip packaging cells Cl.

[0068] 如此一来,本实施例不会受限于第一半导体元件130与第二半导体元件160的尺寸关系,亦即本实施例可制作第一半导体元件130的尺寸大于或等于或小于第二半导体元件160的尺寸的芯片封装单元Cl。 [0068] Thus, the present embodiment is not limited to the size relationship between the first semiconductor element 130 and the second semiconductor element 160, i.e., a first embodiment of the present embodiment can be fabricated semiconductor element 130 is greater than or equal to the size of or smaller than the first Cl second semiconductor chip package unit size element 160. 换言之,本实施例可制得由各种尺寸的芯片相互堆叠而成的封装结构。 In other words, cases of various sizes can be prepared by a chip stack package structure formed by another embodiment. 此外,由于第二封装胶体170可强化厚度相当小的芯片阵列板A,故可在以切割的方式形成芯片封装单元Cl的过程中,避免芯片阵列板A碎裂,从而提升工艺良率。 Further, since the second encapsulant 170 may be relatively small thickness of the reinforcing plate A chip array, it can be cut in the process in a manner of forming a chip package unit Cl, avoiding fragmentation chip array panel A, thereby improving process yield.

[0069] 接着,请同时参照图IH与图II,在本实施例中,可在线路基板180(例如印刷电路板)上形成底胶190,并可将芯片封装单元Cl配置于线路基板180上,以使第一半导体元件130可透过导电凸块132电性与结构性连接线路基板180,并使底胶190位于芯片封装单元Cl的第一半导体元件130与线路基板180之间以包覆第一半导体元件130的导电凸块132。 [0069] Then, referring to FIG. FIG IH II, in the present embodiment, a primer may be formed on the circuit board 190 in 180 (e.g., a printed circuit board), and the Cl chip package unit 180 is disposed on the circuit substrate , so that the first semiconductor element 130 through the conductive bumps 132 may be electrically connected to circuit board 180 and structural, primer and the first semiconductor element 190 of the chip package and the circuit unit 130 Cl between the substrate 180 to cover a first semiconductor element 130 is electrically conductive bump 132.

[0070] 请参照图II,在本实施例中,例如以印刷或是压模的方式在线路基板180上形成第三封装胶体M,第三封装胶体M可覆盖芯片封装单元Cl的侧壁W以及第二半导体元件160的顶面166。 [0070] Referring to FIG. II, in the present embodiment, for example, printing or a stamp is formed on the third encapsulant M circuit board 180, a third encapsulant may cover the chip package unit M Cl sidewall W and the top surface 166 of the second semiconductor element 160. 详细而言,部分的第三封装胶体M位于第二封装胶体170的覆盖顶面166的部分上,换言之,第三封装胶体M间接覆盖第二半导体元件160的顶面166。 Specifically, the third encapsulant portion M is located on the top surface of the cover portion 166 of the second encapsulant 170, in other words, the third encapsulant M indirectly covering the second semiconductor element 160, a top surface 166. 在其他未绘示的实施例中,第三封装胶体M可覆盖芯片封装单元Cl的侧壁W并暴露出第二封装胶体170的覆盖顶面166的部分。 In other embodiments not shown in the embodiment, the third encapsulant may cover the chip package unit M Cl sidewall W 166 and partially cover the top surface of the second encapsulant 170 is exposed.

[0071] 另外,在其他实施例中,可通过使部分的第三封装胶体M填入第一半导体元件130与线路基板180之间的方式,来取代形成底胶190的步骤。 [0071] Further, in other embodiments, the encapsulant can be obtained by the third embodiment M filled portion between the first semiconductor element 130 and circuit board 180, instead of step 190 of forming the primer. 此外,为使芯片封装单元Cl可透过线路基板180电性连接至其他的电子元件,可在线路基板180的远离芯片封装单元Cl的底面182上形成多个焊球S,且焊球S与线路基板180电性连接。 Furthermore, the chip package units is Cl may be connected to other electronic components through the electric circuit board 180, a plurality of solder balls may be formed on the bottom surface 182 remote from the S-chip package substrate 180 cell line Cl, and S and solder balls line 180 is electrically connected to the substrate. 此时,已初步完成本实施例的封装结构100。 At this time, it has been initially completed package structure 100 of the present embodiment.

[0072] 以下将详细介绍图II的封装结构100。 [0072] The following describes a package structure 100 of FIG detail II.

[0073] 请参照图II,本实施例的封装结构100包括第一半导体元件130、第一封装胶体140、第二半导体元件160以及第二封装胶体170。 [0073] Referring to FIG. II, package embodiment 100 of the present embodiment includes a first semiconductor element 130, a first encapsulant 140, a second semiconductor element 160 and the second encapsulant 170. 在本实施例中,第一半导体元件130的厚度T2实质上小于或等于4密尔,举例来说,第一半导体元件130的厚度T2实质上为2密尔。 In the present embodiment, the thickness T2 of the first semiconductor element 130 is substantially equal to or less than 4 mils, for example, a first semiconductor element 130 has a thickness T2 substantially 2 mils.

[0074] 第一封装胶体140包覆第一半导体元件130的侧壁134。 [0074] The sidewall of the first encapsulant 140 covers the first semiconductor element 130, 134. 在本实施例中,第一封装胶体140的朝向第二半导体元件160的顶面144可切齐于第一半导体元件130的朝向第二半导体元件160的顶面136,且第一封装胶体140的厚度Tl实质上可等于第一半导体元件130的厚度T2。 In the present embodiment, the first encapsulant 140 toward the top surface 144 of the second semiconductor element 160 may be cut flush with the first semiconductor element towards the second semiconductor element 160, a top surface 136 of the 130, and the first encapsulant 140 the thickness Tl may be substantially equal to the thickness T2 of the first semiconductor element 130.

[0075] 第二半导体元件160配置于第一半导体元件130与部分第一封装胶体140上,且第二半导体元件160的尺寸大于第一半导体元件130的尺寸。 [0075] The size of the second semiconductor element 160 is disposed on the first portion of the first semiconductor element 130 and the encapsulant 140, and the second semiconductor element 160 is greater than the size of the first semiconductor element 130. 换言之,第二半导体元件160 的朝向第一半导体元件130的底面168的面积大于第一半导体元件130的顶面136的面积。 In other words, the second semiconductor element 160 toward the first area of ​​the bottom 168 of the semiconductor element 130 is greater than the area of ​​the top surface of the first semiconductor element 136 130.

[0076] 值得注意的是,本实施例的封装结构100是将尺寸较大的芯片配置于尺寸较小的芯片上,因此,封装结构100可适于用在将存储器芯片等大尺寸芯片配置于运算芯片等小尺寸芯片上的封装结构中。 [0076] Notably, the present package structure 100 of the embodiment is larger chip size small size disposed on the chip, therefore, the package structure 100 may be adapted for use in a large-sized memory chip arranged on the chip arithmetic chip packaging structure on the other small size chip. 此外,由于本实施例的第一半导体元件130的厚度T2较小(例如小于或等于4密尔),故可降低封装结构100的整体厚度。 Further, since the thickness of the first semiconductor element 130 of the present embodiment T2 is small (e.g., less than or equal to 4 mils), it can reduce the overall thickness of the package structure 100.

[0077] 第二封装胶体170覆盖第二半导体元件160的侧壁164、第二半导体元件160的远离第一半导体元件130的顶面166以及第一封装胶体140,其中第一封装胶体140与第二封装胶体170可为各自成型,且第一封装胶体140的侧壁142可切齐于第二封装胶体170的侧壁172。 [0077] The second encapsulant 170 covers the sidewalls 164,160 of the second semiconductor element, the semiconductor element 160 away from the second to the first semiconductor element 130, a top surface 166 and a first encapsulant 140, wherein the first and the second encapsulant 140 two encapsulant 170 may be individually formed, and the first encapsulant sidewall 142140 can cut flush to a sidewall of the second encapsulant of 172,170.

[0078] 在本实施例中,第二半导体元件160的底面168上配置有多个导电凸块162,以电性连接至第一半导体元件130。 [0078] In the present embodiment, the bottom surface of the second semiconductor element 160 is provided with a plurality of conductive bumps 162, to be electrically connected to the first semiconductor element 130 168. 为保护导电凸块162,可在第二半导体元件160与第一半导体元件130之间以及第二半导体元件160与第一封装胶体140之间配置底胶150,以使底胶150包覆导电凸块162。 To protect the conductive bumps 162, and may be disposed between the first encapsulant 160 and the second semiconductor element 140 between the first semiconductor element 160 and second semiconductor element 130 primer 150, 150 so that the primer-coated conductive bump block 162. 此外,在其他实施例中,亦可无底胶150,亦即可使部分第二封装胶体170填充于第二半导体元件160与第一半导体元件130之间以及第二半导体元件160与第一封装胶体140之间而毋须配置底胶150。 Further, in other embodiments, adhesive 150 may also be bottomless, i.e. make part of the second encapsulant 170 is filled between the second semiconductor element 160 and second semiconductor element 130 and the first package 160 and a first semiconductor element colloid 140 disposed between without primer 150.

[0079] 在本实施例中,第一半导体元件130可配置于线路基板180上,以使第一半导体元件130的多个导电凸决132电性连接至线路基板180。 [0079] In the present embodiment, the first semiconductor element 130 may be disposed on the circuit board 180, semiconductor element such that a first plurality of conductive bumps 130 decision circuit 132 is electrically connected to the substrate 180. 为保护导电凸决132,可在第一半导体元件130与线路基板180之间配置底胶190,以使底胶190包覆导电凸块132。 To protect the conductive protrusion 132 must be disposed between the first semiconductor element 130 and circuit board 180 primer 190, 190 so that the primer coated conductive bump 132.

[0080] 此外,在本实施例中,可在线路基板180上配置第三封装胶体M,第三封装胶体M覆盖第一封装胶体140的侧壁142、第二封装胶体170的侧壁172与第二半导体元件160的远离第一半导体元件130的顶面166。 [0080] Further, in the present embodiment, a third encapsulant may be disposed on a circuit board 180 M, M third encapsulant covering the first encapsulant 140 in the sidewall 142, second sidewall 172 and the encapsulant 170 a second semiconductor element 160 away from the top surface 166 of the first semiconductor element 130. 详细而言,部分的第三封装胶体M位于第二封装胶体170的覆盖第二半导体元件160的顶面166的部分上,换言之,第三封装胶体M是间接覆盖顶面166。 Specifically, the third encapsulant M portion of the second part is located on the second encapsulant 170 covers the top surface 166 of the semiconductor element 160, in other words, the third encapsulant M is indirectly covers the top surface 166. 在其他实施例中,第三封装胶体M可以覆盖第一封装胶体140的侧壁142以及第二封装胶体170的侧壁172,并暴露出第二封装胶体170的覆盖第二半导体元件160的顶面166的部分。 In other embodiments, the third encapsulant M encapsulant may cover the first sidewall 140 and second sidewall 172 142 encapsulant 170, and exposes a second encapsulant 170 covers the top of the second semiconductor element 160 166 of the face portion. 此外,在其他实施例中,亦可无底胶190,亦即可使部分第三封装胶体M填充于第一半导体元件130与线路基板180之间而毋须配置底胶190。 Further, in other embodiments, no primer 190 can, i.e. the third portion encapsulant can fill in and without M primer 190 disposed between the first semiconductor element 130 and circuit board 180.

[0081] 另外,线路基板180的远离第一半导体元件130的底面182上可配置有多个焊球S,焊球S与线路基板180电性连接,且线路基板180可透过焊球S电性连接至其他的电子元件(例如线路板)。 [0081] Further, the line remote from the substrate 180 on the bottom surface of the first semiconductor element 182 130 may be configured with a plurality of solder balls S, S and solder ball 180 is electrically connected to the circuit substrate, and the wiring substrate 180 via solder balls may be electrically S connected to other electronic components (e.g., circuit board).

[0082] 图2A〜图2D绘示本发明另一实施例的封装工艺的剖面图。 [0082] FIG 2A~ FIG. 2D illustrates a cross-sectional view of a package according to another embodiment of the process of the present invention.

[0083] 在本实施例中,可先进行图IA〜图IE的工艺,之后,请参照图2A,在芯片阵列板A上形成第二封装胶体210,第二封装胶体210可选择性地覆盖第二半导体元件160的侧壁164并暴露出第二半导体兀件160的远离对应的第一半导体兀件130的顶面166,且填满第二半导体元件160之间的间隙G2,以保护第二半导体元件160。 [0083] In the present embodiment, the process may be performed first IE FIG IA~ FIG. Thereafter, referring to FIG. 2A, the second encapsulant 210 formed on the chip array panel A, a second encapsulant 210 is selectively covered a second semiconductor element side walls 164,160 and expose the second member away from the corresponding semiconductor Wu Wu first semiconductor element 130, a top 160 of the surface 166, and fills the second gap G2 between the semiconductor element 160, in order to protect the first the second semiconductor element 160.

[0084] 然后,请参照图2B,分离芯片阵列板A与粘着层120。 [0084] Then, referring to Figure 2B, panel A separation chip array 120 and the adhesive layer. 之后,请同时参照图2B与图2C,沿着第二半导体元件160之间的间隙G2切割第二封装胶体170与第一封装胶体140,以形成多个芯片封装单元C2。 Thereafter, referring to FIGS. 2B and 2C, the cut 160 along a second gap G2 between the second semiconductor element 170 and the first encapsulant encapsulant 140 to form a plurality of chip packaging cell C2. 接着,在本实施例中,可在线路基板180上形成底胶190。 Next, in the present embodiment, a primer may be formed in the substrate 190 on line 180.

[0085] 接着,请同时参照图2C与图2D,在本实施例中,可将芯片封装单元C2配置于线路基板180上,以使第一半导体元件130透过导电凸块132电性与结构性连接线路基板180,并使底胶190位于芯片封装单元C2的第一半导体元件130与线路基板180之间以包覆第一半导体兀件130的导电凸块132。 [0085] Next, referring to FIG. 2C and FIG. 2D Meanwhile, in the present embodiment, the chip package unit C2 may be disposed on the circuit board 180, so that the first semiconductor element 130 through the electrically conductive bumps 132 and Structure connecting lines between the substrate 180, and a first semiconductor element 190 primer located in cell C2 chip package 130 and the circuit substrate 180 coated with a conductive bump of the first semiconductor 130 132 Wu.

[0086] 请参照图2D,在本实施例中,可在线路基板180上形成第三封装胶体220,第三封装胶体220可覆盖芯片封装单元C2的侧壁Wl并暴露出第二半导体元件160的顶面166。 [0086] Referring to Figure 2D, in the present embodiment, the third encapsulant 220 may be formed on the circuit board 180, a third encapsulant 220 may cover the sidewalls of the chip package Wl cell C2 and a second semiconductor element 160 is exposed the top surface 166. 此时,已初步完成本实施例的封装结构200。 At this time, it has been initially completed package structure 200 of the present embodiment. 此外,在其他未绘示的实施例中,第三封装胶体220可覆盖芯片封装单元C2的侧壁Wl以及第二半导体元件160的顶面166。 Further, in another not shown embodiment, the third encapsulant 220 may cover the side walls of the cell C2 Wl chip package and a second semiconductor element 160, a top surface 166.

[0087] 以下将详细介绍图2D的封装结构200的结构部分。 [0087] The following describes the structure of FIG. 2D portion of the package structure 200 in detail.

[0088] 请参照图2D,本实施例的封装结构200与图II的封装结构100相似,两者的差异之处在于封装结构200的第二封装胶体210与第三封装胶体220共同暴露出第二半导体元件160的的顶面166。 [0088] Referring to Figure 2D, a package structure package structure 200 of the present embodiment and FIG. II 100 is similar, and the difference therebetween is that the package structure 210 of the second encapsulant 200 and the third encapsulant 220 is exposed on a common a second semiconductor element 160 of the top surface 166. 因此,封装结构200可透过第二半导体元件160的顶面166将第一半导体元件130与第二半导体元件160在运作时所产生的热传导至外界环境,进而提升封装结构200的散热效率。 Thus, the package structure 200 may be a first semiconductor element 166 through the top surface 130 of the second conductive semiconductor element 160 and the second heat generated during the operation of the semiconductor element 160 to the outside environment, and thus enhance the heat dissipation efficiency of the package structure 200.

[0089] 综上所述,本发明先利用第一封装胶体与第二封装胶体来固定并连接第一半导体元件与第二半导体元件,之后再通过切割第一封装胶体与第二封装胶体来形成多个芯片封装单元。 [0089] In summary, the present invention is first fixed and connected to the first semiconductor element and the second semiconductor element with a first encapsulant and the second encapsulant, after cutting through the first encapsulant and the second encapsulant formed a plurality of chip packaging units. 因此,本发明可制得由各种尺寸的芯片相互堆叠而成的封装结构。 Accordingly, the present invention can be prepared by a variety of chip size package structure formed by stacking one another. 此外,由于第二封装胶体可强化厚度相当小的芯片阵列板,故可稳固地连结全部的第二半导体元件以及全部的第一半导体元件,并可在以切割的方式形成芯片封装单元的过程中,避免芯片阵列板碎裂,从而提升工艺良率。 Furthermore, the process may be reinforced since the thickness of the second encapsulant relatively small chip array plate, it can be firmly connected to all of the second semiconductor element and all of the first semiconductor element, and may be formed in a manner to cut a chip package unit , to avoid chipping chip array panel, thereby improving process yield.

[0090] 虽然本发明已以实施例披露如上,然其并非用以限定本发明,任何所属技术领域中普通技术人员,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,故本发明的保护范围当视所附的权利要求所界定为准。 [0090] While the invention has been disclosed in the above embodiments, they are not intended to limit the invention, any ordinary skilled in the art, without departing from the spirit and scope of the present disclosure, may make various omissions, substitutions and retouch, so the scope of the invention as defined by the appended depending claims.

Claims (6)

  1. 1. 一种封装工艺,包括: 提供承载板,该承载板上配置有粘着层; 将多个第一半导体元件配置于该粘着层上,且该多个第一半导体元件彼此分离并分别透过该粘着层固定于该承载板上,其中各该第一半导体元件具有多个直通硅晶穿孔结构; 在该承载板上形成第一封装胶体,该第一封装胶体覆盖该多个第一半导体元件的侧壁并填满该多个第一半导体元件之间的间隙,以使该多个第一半导体元件与该第一封装胶体形成芯片阵列板; 在形成该芯片阵列板之后,研磨该芯片阵列板,以薄化该芯片阵列板并露出各该第一半导体元件的该多个直通硅晶穿孔结构的端面; 将多个第二半导体元件分别倒装接合至该芯片阵列板之该多个第一半导体元件上,以使各该第二半导体元件的多个导电凸块与对应的各该第一半导体元件的该多个直通硅晶穿孔结构的该端面接 A packaging process, comprising: providing a carrier plate, the carrier plate is arranged an adhesive layer; and a first plurality of semiconductor elements disposed on the adhesive layer, and the plurality of first semiconductor elements are separated from each other and through the adhesive layer is fixed on the carrier plate, wherein each of the first semiconductor element having a plurality of through silicon via structure; forming a first encapsulant on the carrier plate, the first encapsulant covering the plurality of first semiconductor elements to fill the gap between the side wall and a first plurality of the semiconductor element, so that the plurality of semiconductor elements formed in a first plate and the first array chip encapsulant; after forming the panel array of chips, grinding the chip array plate, to thin the chip array plate and expose each of the end surface of the first semiconductor element through a plurality of perforations structure of a silicon crystal; a plurality of second semiconductor elements are flip-chip bonded to the plurality of plates of the array chips the end face of the plurality of perforations through the crystal structure of a silicon on a semiconductor element, such that each of the second semiconductor element of each of the plurality of first semiconductor element and the corresponding conductive bumps contact ,其中该第二半导体元件于该承载板上的投影面积大于该第一半导体元件于该承载板上的投影面积; 在该芯片阵列板上形成第二封装胶体,该第二封装胶体至少覆盖该多个第二半导体元件的侧壁并填满该多个第二半导体元件之间的间隙; 分离该芯片阵列板与该粘着层;以及沿着该多个第二半导体元件之间的间隙切割该第二封装胶体与该第一封装胶体,以形成多个芯片封装单元。 Wherein the projected area of ​​the second semiconductor element to the carrier plate of the first semiconductor element is larger than the projection area of ​​the carrier plate; forming a second encapsulant in chip array plate, the second encapsulant covering at least the a plurality of second semiconductor elements to fill the gap between the side wall and a second of the plurality of semiconductor elements; the chip array plate with the adhesive layer was separated; and the cutting along the gap between the plurality of second semiconductor elements the first and second encapsulant encapsulant, to form a plurality of chip packaging units.
  2. 2.如权利要求I所述的封装工艺,其中研磨该芯片阵列板的方法包括: 研磨该芯片阵列板直到该芯片阵列板的厚度实质上小于或等于4密尔。 2. The packaging process according to claim I, wherein the method of grinding the chip array panel comprising: grinding the chip array panel plate until the thickness of the chip array is substantially equal to or less than 4 mils.
  3. 3.如权利要求I所述的封装工艺,还包括: 在形成该芯片阵列板之后,在该多个第一半导体元件上分别形成多个彼此分离的第一底胶,其中各该第一底胶覆盖对应的该第一半导体元件以及该第一封装胶体的围绕对应的该第一半导体元件的部分,且在将该多个第二半导体元件分别倒装接合至该多个第一半导体元件上时,各该第二半导体元件的多个导电凸块通过对应的该第一底胶而与对应的该第一半导体元件接合。 Wherein each of the first substrate after forming the array of the chip plate, forming a first primer separated from each other in the plurality of the first plurality of semiconductor elements, respectively: packaging process as claimed in claim I, further comprising the first semiconductor element and the gum surrounding the corresponding covering the first semiconductor element corresponds to a first portion of the encapsulant, and in the plurality of second semiconductor elements are flip-chip bonded to the plurality of first semiconductor elements when the semiconductor element of each of the first plurality of conductive bumps of the second semiconductor element by the corresponding first primer with the corresponding engagement.
  4. 4.如权利要求I所述的封装工艺,还包括: 将该芯片封装单元配置于线路基板上,以使该第一半导体元件电性与结构性连接该线路基板。 Said packaging process I as claimed in claim, further comprising: the chip package unit is disposed on the circuit substrate so that the first semiconductor element is electrically connected to circuit board and the structural.
  5. 5.如权利要求4所述的封装工艺,还包括: 在该线路基板上形成第二底胶,以使该第二底胶位于该芯片封装单元的该第一半导体元件与该线路基板之间并包覆该第一半导体元件的多个导电凸块。 Is formed between the second primer on the circuit substrate such that the second primer located in the first element of the semiconductor chip package and the circuit board unit: 5. The packaging process according to claim 4, further comprising and encapsulating the plurality of conductive bumps of the first semiconductor element.
  6. 6.如权利要求4所述的封装工艺,还包括: 在该线路基板上形成第三封装胶体,该第三封装胶体至少覆盖该芯片封装单元的侧壁。 6. The packaging process according to claim 4, further comprising: a third encapsulant is formed on the circuit board, the third encapsulant covering at least a sidewall of the chip package unit.
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