CN219677250U - Integrated chip packaging structure and electronic product - Google Patents
Integrated chip packaging structure and electronic product Download PDFInfo
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- CN219677250U CN219677250U CN202320234262.9U CN202320234262U CN219677250U CN 219677250 U CN219677250 U CN 219677250U CN 202320234262 U CN202320234262 U CN 202320234262U CN 219677250 U CN219677250 U CN 219677250U
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- 238000004806 packaging method and process Methods 0.000 title abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 158
- 239000000853 adhesive Substances 0.000 claims abstract description 16
- 230000001070 adhesive effect Effects 0.000 claims abstract description 16
- 239000000463 material Substances 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims description 28
- 238000000465 moulding Methods 0.000 claims description 6
- 150000001875 compounds Chemical class 0.000 claims description 3
- 239000005022 packaging material Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 21
- 230000008054 signal transmission Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 8
- 239000012778 molding material Substances 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 238000012536 packaging technology Methods 0.000 description 3
- 238000005476 soldering Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000007723 die pressing method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model discloses an integrated chip packaging structure and an electronic product. The integrated chip packaging structure comprises a substrate, wherein a groove is formed in the substrate, and extends from the surface of the substrate to the inside of the substrate; an off-substrate chip located outside the substrate and disposed on a surface of the substrate; the substrate inner chip is positioned in the groove and is electrically connected with the substrate outer chip; the plastic package material or the adhesive material is positioned on the surface of the substrate and is filled between the chip outside the substrate and the substrate. The utility model realizes multi-chip interconnection based on the substrate slotting design, can improve the signal transmission speed between chips, and has simple process and high yield; and a rewiring layer is not required to be added, so that the cost is low, and the packaging size is small.
Description
Technical Field
The utility model relates to an integrated chip packaging structure, and also relates to an electronic product comprising the integrated chip packaging structure, belonging to the technical field of chip packaging.
Background
The traditional chip packaging technology is that after each chip is packaged separately, the chips are respectively attached to a printed circuit board, and electric signal connection between the chips is realized through the printed circuit board. However, this chip packaging technology has failed to meet the transmission requirements of high-speed signals. More advanced chip packaging technology is needed to achieve higher signal transmission speed, and integrated chip packaging structures are being developed.
The existing integrated chip packaging structure mainly has two implementation modes: one is to stack a plurality of chips up and down, and the lower chip package has solder balls that can be soldered to the upper chip package. The process of this implementation is relatively complex and places significant restrictions on the package design. Another is that in a package structure, a plurality of chips are packaged in a stacked manner, in which a interposer chip having metal through holes is used as a carrier for other chips, and the other chips are connected to the interposer chip through solder balls. The cost of the implementation mode is high, and the process yield is not ideal.
In chinese patent application No. 201610541089.1, a package structure containing embedded chips and flip chip interconnects is disclosed. Wherein, at least one groove is formed on the substrate, and the functional surface of the first chip is embedded in the groove upwards. The embedded first chip and the surface of the substrate form a plane which is close to the surface, an insulating layer is formed on the plane, at least one rewiring layer is formed on the insulating layer, and the second chip is connected on the plane in a flip-chip mode. In this way, the first chip and the second chip buried in the substrate are electrically interconnected through the rewiring layer, so that the plurality of chips are electrically interconnected, and the chip packaging volume is reduced. However, the arrangement of the re-wiring layer increases the process difficulty, thereby increasing the production cost and being unfavorable for improving the process yield.
Disclosure of Invention
The primary technical problem to be solved by the utility model is to provide an integrated chip packaging structure.
Another technical problem to be solved by the present utility model is to provide an electronic product including the integrated chip package structure.
In order to achieve the above purpose, the present utility model adopts the following technical scheme:
according to a first aspect of an embodiment of the present utility model, there is provided an integrated chip package structure, including:
a substrate provided with a groove extending from a surface of the substrate toward an inside of the substrate;
an off-substrate chip located outside the substrate and disposed on a surface of the substrate;
the substrate inner chip is positioned in the groove and is electrically connected with the substrate outer chip;
and the plastic packaging material or the bonding material is positioned on the surface of the substrate and filled between the substrate outer chip and the substrate.
Wherein preferably the size of the recess is larger than the size of the chip in the substrate to accommodate the chip in the substrate.
Preferably, the size of the chip outside the substrate is larger than that of the groove, and the chip outside the substrate spans two opposite sides of the groove.
Preferably, the substrate at least comprises a surface metal layer, and the surface metal layer is positioned on the surface of the substrate and is connected with the chip outside the substrate.
Preferably, the substrate further comprises an inner metal layer, wherein the inner metal layer is located in the substrate, is connected with the surface metal layer through a metal through hole, is exposed at the bottom surface of the groove, and is connected with the substrate inner chip.
Wherein preferably the intra-substrate chip is mounted to the extra-substrate chip, the extra-substrate chip being electrically connected to the substrate.
Preferably, the plastic package material or the adhesive material is formed in the groove to cover the chip in the substrate.
Wherein preferably, the integrated chip packaging structure further comprises a mounting adhesive; the back surface of the chip in the substrate is coplanar with the surface of the substrate, and the mounting adhesive is adhered to the back surface of the chip in the substrate and the surface of the substrate; or the mounting adhesive is adhered to the back surface of the chip in the substrate and the bottom surface of the groove.
Preferably, the grooves penetrate through the surface and the back of the substrate.
According to a second aspect of the embodiments of the present utility model, an electronic product is provided, which includes the above integrated chip package structure.
Compared with the prior art, the integrated chip packaging structure provided by the utility model realizes multi-chip interconnection based on the substrate slotting design, can improve the signal transmission speed between chips, and has simple process and high yield; and a rewiring layer is not required to be added, so that the cost is low, and the packaging size is small.
Drawings
FIG. 1 is a schematic diagram of an integrated chip package structure according to a first embodiment of the present utility model;
FIG. 2 is a schematic diagram of an integrated chip package structure according to a second embodiment of the present utility model;
FIG. 3 is a schematic diagram of an integrated chip package structure according to a third embodiment of the present utility model;
FIG. 4 is a schematic diagram of an integrated chip package structure according to a fourth embodiment of the present utility model;
FIG. 5 is a schematic diagram of an integrated chip package structure according to a fifth embodiment of the present utility model;
FIG. 6 is a schematic diagram of an integrated chip package structure according to a sixth embodiment of the utility model;
FIG. 7 is a schematic diagram of an integrated chip package structure according to a seventh embodiment of the utility model;
fig. 8 is a schematic diagram of an integrated chip package structure according to an eighth embodiment of the utility model.
Detailed Description
The technical contents of the present utility model will be described in detail with reference to the accompanying drawings and specific examples.
First embodiment:
as shown in fig. 1, a first embodiment of the present utility model discloses an integrated chip package structure, which at least includes an external chip 1, an internal chip 2, a substrate 3 and a molding material 4. The molding compound 4 encapsulates the substrate outer die 1 and the substrate inner die 2 and fills the recess 30.
A groove 30 is formed on the substrate 3 using a grooving process. The recess 30 extends from the substrate surface toward the substrate interior. The recess 30 has a size larger than the size of the intra-substrate chip 2 so that the intra-substrate chip 2 can be placed into the recess 30.
The substrate 3 comprises at least two metal layers, namely a surface metal layer 31 and an inner metal layer 32, connected by means of metal vias 33. Wherein the surface metal layer 31 is located on the surface of the substrate 3 adjacent to the recess 30, exposed for soldering with the off-board interconnect structure 11. The inner metal layer 32 is located inside the substrate 3 and exposed at the bottom surface of the recess 30 for soldering with the in-board interconnect structure 21. That is, the surface metal layer 31 is located on the surface of the substrate 3 and connects the off-substrate chip 1; the inner metal layer 32 is located inside the substrate 3, and is connected to the surface metal layer 31 by metal vias, exposed at the bottom surface of the recess 30, and connected to the substrate inner chip 2. On the basis, the substrate outer chip 1 and the substrate inner chip 2 are respectively and electrically connected with the outside through the substrate.
The off-substrate chip 1 is larger in size than the recess 30, may span opposite sides of the recess 30, and is connected to the surface metal layer 31 by the off-board interconnect structure 11. In other words, the projection of the off-substrate chip 1 onto the substrate 3 covers the surface metal layer 31 and the grooves 30. The upper surface of the chip 2 in the substrate soldered in the recess 30 is not higher than the surface of the substrate.
In the integrated chip package structure provided in the present embodiment, the substrate inner chip 2 is connected to the inner metal layer 32 through the in-board interconnect structure 21; and then connected to the surface metal layer 31 through the metal via hole 33; finally, the connection is realized with the off-board chip 1 through the off-board interconnection structure 11, so that the two chips are packaged together. The connecting path of the two is shorter, the performance is better, the packaging process is simple, and the cost is lower.
Second embodiment:
the second embodiment of the present utility model is similar to the first embodiment, but the package is formed to protect the two chips by using a dispensing process instead of a molding process, as shown in fig. 2.
Specifically, the second embodiment of the present utility model discloses an integrated chip package structure, which at least comprises an external chip 1, an internal chip 2, a substrate 3 and an adhesive material 6. The adhesive 6 covers the surfaces of the substrate outer chip 1, the substrate inner chip 2, and the substrate 3 facing the substrate outer chip 1, and fills in the grooves 30. Therefore, the present embodiment covers the chip in the substrate with the adhesive material 6 instead of the molding material 4.
Third embodiment:
as shown in fig. 3, the third embodiment of the present utility model is different from the first embodiment in that: the off-board interconnection structure between the off-board chip 1 and the substrate 3 is a wire bond structure, not a solder ball; and a paste adhesive 50 is provided between the substrate outer chip 1 and the substrate inner chip 2. Since the intra-substrate chip 2 is soldered into the groove 30, the back surface of the intra-substrate chip 2 is coplanar with the surface of the substrate 3, the paste adhesive 50 can be adhered to the surface of the substrate 3 and the back surface of the intra-substrate chip 2 using a conventional mounting process.
The upper surface of the mounting paste 50 is as large as the projection of the outline of the off-board chip 1 on the substrate 3 so as to completely mount the bottom surface of the off-board chip 1 to the surface of the substrate 3. And, the back surface of the chip 2 in the substrate is attached to the lower surface of the mounting paste 50. Thus, the substrate inner chip 2 plays a supporting role for the substrate outer chip 1.
Filling the grooves 30 by using a dispensing process to protect the chip 2 in the substrate; the chip 1 outside the substrate is protected by a plastic package process.
Fourth embodiment:
as shown in fig. 4, the fourth embodiment of the present utility model is different from the first embodiment in that: the intra-substrate chip 2 is mounted on the extra-substrate chip 1 by SMT (surface mount technology) using solder balls. Specifically, the substrate inner chip 2 is mounted to the central region of the substrate outer chip 1 using the SMT technique, and then the substrate outer chip 1 is flipped over and mounted on the substrate 3 using the SMT technique.
In this embodiment, the substrate inner chip 2 is located in the groove 30 and is filled with the molding material together with the substrate outer chip 1. And the substrate inner chip is mounted on the substrate outer chip, and the substrate outer chip is electrically connected with the substrate.
Fifth embodiment:
as shown in fig. 5, the fifth embodiment of the present utility model is similar to the fourth embodiment except that the substrate inner chip 2 and the substrate outer chip 1 are simultaneously filled and protected by a dispensing process instead of a molding process. Therefore, the grooves 30 on the substrate 3 are filled with materials used in the dispensing process; the materials used in the dispensing process are also filled between the chip 1 outside the substrate and the substrate 3. In this way, the adhesive material 6 fills the grooves 30 on the substrate 3 and between the off-substrate chip 1 and the substrate 3.
Sixth embodiment:
as shown in fig. 6, a sixth embodiment of the present utility model is similar to the fourth embodiment, except that: the bottom of the groove 30 is provided with a mounting adhesive 50, and the back surface of the chip 2 in the substrate is mounted in the groove 30, so that the chip 2 in the substrate is supported by the substrate 3, and is favorable for bearing the die pressing during plastic packaging.
Therefore, not only the chip 2 but also the paste 50 are provided in the recess 30 on the substrate 3. The molding compound 4 fills in between the recess 30 and the off-substrate chip 1 and the substrate 3.
Seventh embodiment:
as shown in fig. 7, the seventh embodiment of the present utility model is similar to the sixth embodiment except that the dispensing process is used instead of the molding process. Therefore, not only the chip 2 but also the paste 50 are provided in the recess 30 on the substrate 3. The adhesive material 6 fills in between the recess 30 and the off-substrate chip 1 and the substrate 3.
Eighth embodiment:
as shown in fig. 8, the eighth embodiment of the present utility model is similar to the fourth embodiment, except that: the grooves 30A penetrate the front and rear surfaces of the substrate 3A. In this way, the molding material 4 fills the entire surface of the substrate 3 and the inside of the recess 30A of the substrate 3A.
Compared with the prior art, the integrated chip packaging structure provided by the utility model realizes multi-chip interconnection based on the substrate slotting design, can improve the signal transmission speed between chips, and has simple process and high yield; and a rewiring layer is not required to be added, so that the cost is low, and the packaging size is small.
The integrated chip package structure and the electronic product provided by the utility model are described in detail above. Any obvious modifications to the present utility model, without departing from the spirit thereof, would constitute an infringement of the patent rights of the utility model and would take on corresponding legal liabilities.
Claims (11)
1. An integrated chip package structure, comprising:
a substrate provided with a groove extending from a surface of the substrate toward an inside of the substrate;
an off-substrate chip located outside the substrate and disposed on a surface of the substrate;
the substrate inner chip is positioned in the groove and is electrically connected with the substrate outer chip;
and the plastic packaging material or the bonding material is positioned on the surface of the substrate and filled between the substrate outer chip and the substrate.
2. The integrated chip package structure of claim 1, wherein the recess has a size greater than a size of the chip-in-substrate to accommodate the chip-in-substrate.
3. The integrated chip package of claim 1, wherein the off-substrate chip is larger in size than the recess and spans opposite sides of the recess.
4. The integrated chip package structure of claim 1, wherein the substrate comprises at least a surface metal layer, the surface metal layer being located on a surface of the substrate and connecting the off-substrate chip.
5. The integrated chip package of claim 4, wherein the substrate further comprises an inner metal layer; the inner metal layer is positioned in the substrate, is connected with the surface metal layer by utilizing a metal through hole, is exposed at the bottom surface of the groove and is connected with the chip in the substrate.
6. The integrated chip package of claim 3, wherein the intra-substrate chip is mounted to an extra-substrate chip, the extra-substrate chip being electrically connected to the substrate.
7. The integrated chip package structure of claim 3, wherein the molding compound or adhesive material is formed in the recess to encapsulate the chip in the substrate.
8. The integrated chip package of claim 3, further comprising a paste; the back surface of the chip in the substrate is coplanar with the surface of the substrate, and the mounting adhesive is adhered to the back surface of the chip in the substrate and the surface of the substrate.
9. The integrated chip package structure of claim 3, further comprising a paste adhesive attached to the back surface of the chip and the bottom surface of the recess in the substrate.
10. The integrated chip package of claim 3, wherein the recess extends through the front and back surfaces of the substrate.
11. An electronic product, characterized in that it comprises the integrated chip package structure according to any one of claims 1 to 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320234262.9U CN219677250U (en) | 2023-02-16 | 2023-02-16 | Integrated chip packaging structure and electronic product |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320234262.9U CN219677250U (en) | 2023-02-16 | 2023-02-16 | Integrated chip packaging structure and electronic product |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219677250U true CN219677250U (en) | 2023-09-12 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202320234262.9U Active CN219677250U (en) | 2023-02-16 | 2023-02-16 | Integrated chip packaging structure and electronic product |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219677250U (en) |
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2023
- 2023-02-16 CN CN202320234262.9U patent/CN219677250U/en active Active
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