TWI823201B - Chip interconnection method, interconnection device and method for forming packaging piece - Google Patents

Abstract

The invention provides a chip interconnection method, an interconnection device and a method for forming a packaging piece. The chip interconnection method comprises the steps of arranging a first chip and a second chip on the surface of a carrier, wherein a plurality of first bumps are formed on the upper surface of the first chip, a plurality of second bumps are formed on the upper surface of the second chip, and the contact surface of the first bump is smaller than that of the second bump; attaching an interconnection device to partial upper surfaces of the first chip and the second chip, and forming a plurality of first bonding pads for bonding to the plurality of first bumps and a plurality of second bonding pads for bonding to the plurality of second bumps on one side surface of the interconnection device, wherein the plurality of first bonding pads of the interconnection device are aligned and bonded to the plurality of first bumps, so that the plurality of second bonding pads and the plurality of second bumps of the interconnection device are self-aligned and jointed. By means of the method, the problem that alignment joint is difficult to achieve due to errors is solved.

Description

Chip interconnection methods, interconnection devices, and methods of forming packages

The invention belongs to the field of semiconductors, and specifically relates to wafer interconnection methods, interconnection devices and methods of forming packages.

This section is intended to provide background or context for embodiments of the invention set forth in the claimed scope. The description herein is not admitted to be prior art by inclusion in this section.

With the advent of the era of artificial intelligence, the development trend of semiconductor integrated circuits is to have more functions and faster computing speeds. Due to "Moore's Law", if we simply use SOC integration of large wafers to meet this development trend, it will undoubtedly make circuit design more and more difficult and manufacturing costs more and more expensive. A more practical solution is to use heterogeneous integration technology of multiple small chips to complete the purpose of functional integration. Based on this, the current important task for high-end packaging is to develop high-efficiency, high-density multi-chip interconnection technology to form the physical layer functional blocks of the chip through direct connection between bare wafers, thereby replacing the SOC integration of large wafers. , achieving low cost and high degree of freedom, and having the same functionality.

In the existing multi-wafer interconnection technology, installation errors inevitably occur during the packaging process of semiconductor wafers, making it difficult to achieve alignment and bonding between the multi-wafer and interconnection devices.

In view of the problems existing in the above-mentioned prior art, a chip interconnection method, an interconnection device, and a method of forming a package are proposed. Using this method, device, and package, the above problems can be solved.

The present invention provides the following solutions.

In a first aspect, a wafer interconnection method is provided, including: arranging a first wafer and a second wafer on a carrier surface, wherein a plurality of first bumps are formed on the upper surface of the first wafer, and a plurality of first bumps are formed on the upper surface of the second wafer. A plurality of second bumps, the contact surface of the first bump is smaller than the second bump; an interconnection device is attached to part of the upper surface of the first wafer and the second wafer, and one side surface of the interconnection device is formed with a surface for bonding to a plurality of a plurality of first pads for the first bumps and a plurality of second pads for bonding to the plurality of second bumps, wherein the plurality of first pads of the interconnect device are aligned for bonding to the plurality of first bumps , so that the plurality of second pads and the plurality of second bumps of the interconnection device can achieve self-aligned bonding.

In some possible implementations, the plurality of first bumps on the first wafer are a plurality of high-density bumps, and the plurality of second bumps on the second wafer are a plurality of low-density bumps.

In some possible implementations, a fan-out circuit is formed between a plurality of first pads and a plurality of second pads of the interconnection device, so that the first wafers included in each group of wafers can be electrically connected through the interconnection device. to the second wafer.

In some possible implementations, the interconnect device is formed as an interconnect device having vertical interconnect vias.

In some possible implementations, the interconnect components are formed as passive components or active components.

In a second aspect, an interconnection device is provided. A plurality of first bonding pads and a plurality of second bonding pads are formed on one side surface of the interconnection device, wherein the plurality of first bonding pads are used for bonding to a first wafer, and a plurality of third bonding pads are formed on one side surface of the interconnection device. The two bonding pads are used for bonding to the second wafer; a fan-out circuit is formed between the plurality of first bonding pads and the plurality of second bonding pads of the interconnection device for realizing the plurality of first bonding pads and the plurality of second bonding pads. electrical connections between disks.

In some possible implementations, the interconnect device is formed as an interconnect device having vertical interconnect vias.

In some possible implementations, the interconnect components are formed as passive components or active components.

In some possible implementations, the interconnect device uses a semiconductor material, including one or more of the following: silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), and gallium nitride (GaN).

In some possible implementations, the interconnection device uses inorganic materials, including one or more of the following: glass and ceramics.

In some possible implementations, the interconnection device uses a packaging substrate material, including one or more of the following: printed circuit substrate (PCB), plastic encapsulation substrate (EMC), and flexible circuit substrate.

In some possible implementations, the interconnection device uses a metal substrate material, including one or more of the following: copper, aluminum.

In some possible implementations, the interconnect device has the functions of integrated circuits, microelectromechanical systems (MEMS), optoelectronic components, and passive components (IPD).

A third party provides a method for forming a package, including: providing a carrier and at least one group of wafers, wherein each group of wafers at least includes a first wafer and a second wafer; Mounted upward on the surface of the carrier, wherein the upper surface of the first wafer has first bumps, and the upper surface of the second wafer has second bumps; the interconnection device is attached to each group of wafers using the method of the first aspect Include part of the upper surface of the first wafer and the second wafer, so that the first wafer included in each group of wafers can be electrically connected to the second wafer through the interconnection device; forming a plastic sealing layer around the first wafer and the second wafer , wherein the first wafer, the second wafer and the interconnection device are embedded in the plastic encapsulation layer; a thinning process is performed on the side surface of the plastic encapsulation layer away from the carrier to expose the first bumps of the first wafer and the second bumps of the second wafer. Bumps; forming third bumps on a side surface of the plastic sealing layer where the first bumps and second bumps are exposed; and removing the carrier.

In some possible implementations, the number of wafer groups is greater than 1, and the method further includes: after removing the carrier, cutting the formed package to obtain a plurality of unit packages, wherein each unit package includes a group of wafers.

At least one of the above technical solutions adopted in the embodiments of the present application can achieve the following beneficial effects: It can be understood that during the packaging process of semiconductor wafers, installation errors are unavoidable. In this embodiment, the second bumps have larger contact The area has a larger tolerance space for errors. By first accurately aligning and bonding the first bumps and the first pads, multiple second pads of the interconnect device can be self-aligned and bonded to have a larger tolerance space for errors. on multiple second bumps. Avoid the problem of difficult alignment and jointing due to errors.

It should be understood that the above description is only an overview of the technical solution of the present invention, so that the technical means of the present invention can be understood more clearly, so that the technical means of the present invention can be implemented according to the content of the description. In order to make the above and other objects, features and advantages of the present invention more obvious and understandable, specific embodiments of the present invention are illustrated below.

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a thorough understanding of the disclosure, and to fully convey the scope of the disclosure to those skilled in the art.

The following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, attaching the interconnection device 13 to the upper surfaces of the first wafer 11 and the second wafer 12 may include an embodiment in which the first wafer 11 , the second wafer 12 and the interconnection device 13 are formed in direct contact, and may also be This includes embodiments in which additional components may be formed between the first wafer 11 , the second wafer 12 and the interconnection device 13 , so that the first wafer 11 , the second wafer 12 and the interconnection device 13 may not be in direct contact. Furthermore, the present invention may repeat reference numbers and/or characters in various embodiments. This repetition is for simplicity and clarity and does not by itself indicate a relationship between the various embodiments and/or configurations discussed.

It will be understood that terms such as "comprising" or "having" are intended to indicate the presence of features, numbers, steps, acts, parts, portions or combinations thereof disclosed in this specification and are not intended to exclude one or more other features , the possibility of existence of digits, steps, actions, parts, parts or combinations thereof.

Moreover, for convenience of description, spatially relative terms such as "under", "below", "lower", "above", "above", etc. may be used herein to describe the The relationship of one element or part to another (or other) elements or parts. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In addition, it should be noted that, without conflict, the embodiments and features in the embodiments of the present invention can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

FIG. 1 is a schematic flowchart of a method 100 for forming a package according to an embodiment of the present application. As shown in Figure 1, the method 100 may include steps 101 to 102.

Step 101: Place the first wafer and the second wafer on the surface of the carrier.

Referring to FIG. 2A , the first wafer 11 and the second wafer 12 can be installed face-up on the surface of the carrier 10 according to the preset wafer spacing or the preset wafer placement position. The upper surface of the first wafer 11 has first bumps 21, and the upper surface of the second wafer 12 has second bumps 22. The bumps can also be called chip pins, and the side surface of the wafer with the chip pins is called It is the front side, and the side surface opposite to the front side is called the back side. For example, in some embodiments, the first bump 21 and the second bump 22 may be formed as solder bumps made of conductive materials, including Cu, Ag, Au, etc. or their alloys, and may also include other Material. For example, in some embodiments, two or more wafers may be coupled to carrier 10 using an automated machine, such as a packaging machine, or manually. In some embodiments, an adhesive film (not shown) or a die attach film (not shown) may be used to couple the back sides of the first wafer 11 and the second wafer 12 to either side of the carrier 10 such that the first wafer 11 and the front side of the second wafer 12 are shown outward away from the carrier 10 , which in a semiconductor package may also be referred to as face-up.

Referring to Figure 3A, a schematic top view of the first wafer 11 and the second wafer 12 is shown. In this embodiment, the first wafer 11 and the second wafer 12 are arranged side by side and spaced apart on the carrier surface, and the first edge area of the first wafer and the second edge area of the second wafer are distributed between the first wafer and the second wafer. on both sides of the gap. The first edge area of the first wafer 11 includes a plurality of first bumps 21 , and the second edge area of the second wafer includes a plurality of second bumps 22 . The contact surface of the first bump 21 is smaller than the second bump 22 .

It can be understood that during the packaging process of semiconductor wafers, mounting errors are unavoidable. In step 101, when the first wafer 11 and the second wafer 12 are installed on one side surface of the carrier 10, a certain degree of installation spacing error may occur. For example, the actual wafer spacing between the first wafer 11 and the second wafer 12 is closer or further than the preset wafer spacing designed in advance. For another example, the pre-designed wafer placement position is that the first wafer 11 and the second wafer 12 are placed side by side and parallel. However, during the actual placement process, the first wafer 11 and the second wafer 12 are not placed completely parallel. However, there is an angular error. Installation errors such as this inevitably exist during the wafer placement process.

Step 102: Attach interconnection devices to portions of upper surfaces of the first wafer and the second wafer.

Referring to FIG. 3B , a plurality of first bonding pads 131 and a plurality of second bonding pads 132 are formed on one side surface of the interconnection device 13 , and the plurality of first bonding pads 131 are used for bonding to the first bonding pads 131 formed on the upper surface of the first wafer 11 . The plurality of first bumps 21 and the plurality of second pads 132 are used for bonding to the plurality of second bumps 22 formed on the upper surface of the second wafer 12 .

In this embodiment, the interconnect device 13 is adapted to be attached over the first edge region of the first wafer and the second edge region of the second wafer across the gap between the first wafer and the second wafer. The plurality of first bonding pads 131 distributed on one side surface of the interconnection device 13 are used for mutual bonding with the plurality of first bumps 21 included in the first edge area, and the plurality of distributed second bonding pads 132 are used for bonding with the second edge area. The area contains a plurality of second protrusions 22 that are joined to each other. It should be understood that the pad positions of the plurality of first pads 131 and the plurality of second pads 132 in the interconnection device are determined by the preset wafer placement positions and the bump distribution positions on the first wafer 11 and the second wafer 12 And certain. For example, when the wafer spacing between the first wafer 11 and the second wafer 12 determined in the wafer design is relatively wide, the first wafer 11 and the second wafer 12 shown in FIG. 3A need to be designed to be wider. The interconnection device 13 shown in FIG. 3B is also designed to be wider according to the wafer pitch. Specifically, the width between the first pad area and the second pad area in the interconnection device 13 is wider. In other words, in an ideal situation, that is, in the absence of the above-mentioned installation error, the interconnection device 13 can be attached above the first wafer 11 and the second wafer 12 , and the plurality of first pads 131 in the interconnection device 13 The plurality of second bonding pads 132 can be accurately bonded to corresponding bumps on the first wafer and the second wafer at the same time.

Because in step 101, installation errors are unavoidable. In this embodiment, the specific installation steps of attaching the interconnection device 13 to the upper surfaces of the first wafer 11 and the second wafer 12 are: aligning and bonding the plurality of first pads of the interconnection device 13 to the plurality of first bumps. , so that the plurality of second pads 132 of the interconnection device 13 are self-aligned and bonded to the plurality of second bumps 22 of the second wafer. In other words, the plurality of first bumps 21 and the first solder joints are aligned and bonded. The pad 131 serves as a reference so that the plurality of second bonding pads 132 of the interconnection device 13 are self-aligned and bonded to the plurality of second bumps based on the device's own tension.

Referring to FIG. 3C , in this embodiment, by first accurately aligning the first bump 21 and the first pad 131 , the alignment bonding between the first bump 21 and the first pad 131 can be achieved. After the first pads 131 and the plurality of first bumps 21 are bonded to each other, the actual placement position of the interconnection device has been determined. At this time, the second bump 22 has a larger accommodation error due to its larger contact area. Based on the self-tension of the interconnection device 13, the plurality of second pads 132 can be self-aligned and joined to have a larger accommodation error. on multiple second convex points in the space. As a result, alignment and bonding between the plurality of first bumps 21 and the plurality of first pads 131 and automatic alignment and bonding between the plurality of second bumps 22 and the plurality of second pads 132 can be achieved. Avoid the problem of difficult alignment and jointing due to errors.

In some embodiments, the first bump 21 and the first pad 131 may have the same or similar shape and size of contact surfaces, thereby facilitating precise alignment between the first bump 21 and the first pad 131 . Accurate. This avoids or reduces an additional increase in the alignment error between the second bump 22 and the second pad 132 caused by the alignment error between the first bump 21 and the first pad 131 .

In some embodiments, referring to FIG. 3A , the plurality of first bumps 21 of the first wafer 11 are a plurality of high-density bumps, and the plurality of second bumps 22 of the second wafer 12 are a plurality of low-density bumps. Therefore, the high-density first bumps 21 and the first pads 131 can achieve alignment bonding, while the low-density first bumps 22 have a larger room for error accommodation due to their larger contact area, thereby avoiding errors due to errors. resulting in difficulty in alignment and jointing.

In some embodiments, referring to FIG. 3B , a fan-out circuit 133 is formed between the plurality of first pads 131 and the plurality of second pads 132 of the interconnection device 13 , and the fan-out circuit 133 is used for The connected set of first pads and second pads are electrically connected, so that after the interconnection device 13 is attached to the first wafer 11 and the second wafer 12 , the first wafer 11 is passed through the interconnection device 13 Can be electrically connected to the second chip 12 .

In some other embodiments, any other type of interconnection circuit may also be formed between the plurality of first pads 131 and the plurality of second pads 132 of the interconnection device 13 , as long as the interconnection circuit can implement any one or more The electrical connection between each first pad 131 and any one or more second pads 132 is sufficient.

In some embodiments, the contact surface of the first pad 131 is smaller than the contact surface of the second pad 132 , whereby the second pad 132 has a larger room for error tolerance due to its larger contact area. After the bonding pads 131 and the first bumps 21 are aligned and bonded, the plurality of second bonding pads 132 of the interconnection device 13 with a greater tolerance space for errors can be self-aligned and bonded to the plurality of second bonding pads 132 with a greater tolerance space for errors. On the second bump. The error tolerance is further improved.

The embodiment of the present application also provides an interconnection device, and FIG. 3B shows a schematic structural diagram of the interconnection device 13.

Referring to FIG. 3 , a plurality of first bonding pads 131 and a plurality of second bonding pads 132 are formed on one side surface of the interconnection device 13 . The plurality of first bonding pads 131 are used for bonding to the first wafer, and the plurality of second bonding pads 132 are used for bonding to the first wafer. The two bonding pads 132 are used for bonding to the second wafer; a fan-out circuit 133 is formed between the plurality of first bonding pads 131 and the plurality of second bonding pads 132 of the interconnection device 13 for realizing the plurality of first bonding pads and electrical connections between the plurality of second pads.

In some possible implementations, the interconnect device is formed as an interconnect device having vertical interconnect vias.

In some possible implementations, the interconnect components are formed as passive components or active components.

In some possible implementations, the interconnect device uses a semiconductor material, including one or more of the following: silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), and gallium nitride (GaN).

In some possible implementations, the interconnection device uses inorganic materials, including one or more of the following: glass and ceramics.

In some possible implementations, the interconnection device uses a packaging substrate material, including one or more of the following: printed circuit substrate (PCB), plastic encapsulation substrate (EMC), and flexible circuit substrate.

In some possible implementations, the interconnection device uses a metal substrate material, including one or more of the following: copper, aluminum.

In some possible implementations, the interconnect device has the functions of integrated circuits, microelectromechanical systems (MEMS), optoelectronic components, and passive components (IPD). Embodiments of the present application also provide a method of forming a package. 2A-2E show schematic cross-sectional views of intermediate stages in the process according to an embodiment of the present application.

The method includes: providing a carrier 10 and at least one group of wafers, wherein each group of wafers at least includes a first wafer 11 and a second wafer 12; referring to FIG. 2A, facing the first wafer 11 and the second wafer 12 included in each group of wafers. The upper surface of the first chip 11 has first bumps 21 and the upper surface of the second chip 12 has second bumps 22; the interconnection device 13 is attached using the method as in the above embodiment. Connected to part of the upper surface of the first wafer 11 and the second wafer 12 included in each group of wafers, so that the first wafer 11 included in each group of wafers can be electrically connected to the second wafer 12 through the interconnection device 13; see Figure 2B, A plastic sealing layer 30 is formed around the first wafer 11 and the second wafer 12 , in which the first wafer 11 , the second wafer 12 and the interconnection device 13 are embedded in the plastic sealing layer 30 ; see FIG. 2C , when the plastic sealing layer 30 is away from the carrier 10 One side of the surface is thinned to expose the first bumps 21 of the first wafer 11 and the second bumps 22 of the second wafer 12; see FIG. 2D, the first bumps 21 and 22 are exposed on the plastic layer 30. One side surface of the second bump 22 forms a third bump 40; and, referring to FIG. 2E, the carrier 10 is removed.

In a possible implementation, the number of the above-mentioned wafer groups is greater than 1, and the method further includes: after removing the carrier 10, cutting the formed package to obtain a plurality of unit packages, wherein each unit package includes a group of wafers. . This enables large-scale packaging.

The wafer interconnection methods and interconnection devices provided by the embodiments of the present application can also be used in semiconductor packages in the form of wafer stacks. For example, referring to Figure 4, a carrier 10 and a multi-layer wafer can be provided; Referring to Figure 4, the first wafer 11 and the second wafer 12 included in the first layer of wafers can be mounted face up on the surface of the carrier 10; using Figure 1 The illustrated wafer interconnection method attaches the interconnection device 13 to a portion of the upper surface of the first wafer 11 and the second wafer 12 included in the first layer of wafer, so that the first wafer 11 included in the first layer of wafer can pass through the interconnection device 13 Electrically connected to the second chip 12; install the third chip 14 and the fourth chip 15 included in the second layer of chips face up on the upper surfaces of the first chip 11 and the second chip 12, and distribute them on the interconnection device 13 On both sides of the wafer, the interconnection device 16 is attached to part of the upper surface of the third wafer 14 and the fourth wafer 15 included in the second layer wafer using the wafer interconnection method as shown in Figure 1, so that the second layer wafer includes the third wafer 14 and the fourth wafer 15. The third chip 14 can be electrically connected to the fourth chip 15 through the interconnection device 16 and simultaneously connected to the interconnection device 13 . Through the interconnection devices 13 and 16, the first wafer 11 and the second wafer 12 included in the first layer of wafers and the third wafer 14 and the fourth wafer 15 included in the second layer of wafers can be electrically connected. As a result, interconnection devices can be used to achieve electrical connections between multi-layer wafers.

Although the spirit and principles of the invention have been described with reference to a number of specific embodiments, it should be understood that the invention is not limited to the specific embodiments disclosed, nor does the division into aspects mean that features in these aspects cannot be combined. Benefit, this division is only for convenience of expression. The invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

10: Carrier 11:First chip 12:Second chip 13, 16: Interconnect devices 131:First pad 132: Second pad 133: Fan-out circuit 14:Third chip 15:The fourth chip 21:The first bump 22: The second picture point 30:Plastic sealing layer 40: The third bump

The advantages and benefits described herein, as well as other advantages and benefits, will be apparent to those of ordinary skill in the art from reading the following detailed description of the exemplary embodiments. The drawings are for the purpose of illustrating exemplary embodiments only and are not to be considered limiting of the invention. Furthermore, the same reference numerals are used throughout the drawings to designate the same components. In the attached picture:

In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.

[Fig. 1] is a schematic flowchart of a method of forming a package according to an embodiment of the present invention; [Figures 2A to 2E] are schematic cross-sectional views of an intermediate stage in the process of forming a package according to an embodiment of the present invention; [Figures 3A to 3C] are schematic diagrams of the process of chip interconnection according to another embodiment of the present invention; [Fig. 4] is a schematic structural diagram of a stacked chip package using interconnect devices according to an embodiment of the present invention.

Step 101: Place the first wafer and the second wafer on the surface of the carrier

Step 102: Attaching interconnect devices to portions of upper surfaces of the first and second wafers

Claims (14)

A wafer interconnection method, characterized by including: arranging a first wafer and a second wafer on a carrier surface, wherein a plurality of first bumps are formed on the upper surface of the first wafer, and a plurality of first bumps are formed on the upper surface of the second wafer. A plurality of second bumps are formed on the surface, and the contact surface of the first bumps is smaller than the second bumps; an interconnection device is attached to part of the upper surface of the first wafer and the second wafer, so A side surface of the interconnection device is formed with a plurality of first pads for bonding to the plurality of first bumps and a plurality of second pads for bonding to the plurality of second bumps, wherein, Alignment bonding of the plurality of first pads of the interconnect device to the plurality of first bumps such that a plurality of second pads of the interconnect device are self-aligned and bonded to the second A plurality of second bumps on the wafer. The method according to claim 1, wherein the plurality of first bumps on the first wafer are a plurality of high-density bumps, and the plurality of second bumps on the second wafer are Multiple low density bumps. The method according to claim 1, characterized in that fan-out circuits are formed between a plurality of first pads and a plurality of second pads of the interconnection device, so that each group of wafers includes The first wafer can be electrically connected to the second wafer through the interconnection device. The method according to any one of claims 1-3, characterized in that the interconnection device is formed as an interconnection device having vertical interconnection vias. The method according to any one of claims 1-3, characterized in that the interconnection device is formed as a passive device or an active device. An interconnection device characterized by: A plurality of first bonding pads and a plurality of second bonding pads are formed on one side surface of the interconnection device, wherein the plurality of first bonding pads are used for bonding to the first wafer, and the plurality of second bonding pads for bonding to the second wafer; a fan-out circuit for fan-out in the horizontal direction is formed between the plurality of first pads and the plurality of second pads of the interconnection device for realizing the The electrical connection between the plurality of first pads and the plurality of second pads, wherein the interconnection device is placed in the package before plastic sealing of the package; wherein the interconnection device adopts Metal substrate materials include one or more of the following: copper, aluminum. The interconnection device according to claim 6, characterized in that the interconnection device is formed as an interconnection device having vertical interconnection vias. The interconnection device according to claim 6, characterized in that the interconnection device is formed as a passive device or an active device. The interconnection device according to claim 6, characterized in that the interconnection device uses a semiconductor material, including one or more of the following: silicon, silicon carbide, gallium arsenide, and gallium nitride. The interconnection device according to claim 6, characterized in that the interconnection device adopts inorganic materials, including one or more of the following: glass and ceramics. The interconnection device according to claim 6, characterized in that the interconnection device adopts a packaging substrate material, including one or more of the following: printed circuit substrate, plastic packaging substrate, and flexible circuit substrate. The interconnection device according to claim 6, characterized in that the interconnection device has the functions of integrated circuits, microelectromechanical systems, optoelectronic components and passive components. A method of forming a package, characterized in that it includes: providing a carrier and at least one group of wafers, wherein each group of wafers at least includes a first wafer and a second wafer; Two wafers are mounted face-up on the surface of the carrier, wherein the upper surface of the first wafer has first bumps, and the upper surface of the second wafer has second bumps; using any one of claims 1-5 The method described attaches an interconnection device to a portion of the upper surface of the first wafer and the second wafer included in each group of wafers, so that the first wafer included in each group of wafers can electrically conduct electricity through the interconnection device. Sexually connected to the second wafer; forming a plastic encapsulation layer around the first wafer and the second wafer, wherein the first wafer, the second wafer and the interconnection device are embedded in the plastic encapsulation layer ; Perform a thinning process on the side surface of the plastic sealing layer away from the carrier to expose the first bumps of the first wafer and the second bumps of the second wafer; when the plastic sealing layer is exposed forming a third bump on one side surface of the first bump and the second bump; and removing the carrier. A method of forming a package according to claim 13, characterized in that the number of wafer groups is greater than 1, and the method further includes: after removing the carrier, cutting the formed package to obtain a plurality of Cell packages, wherein each said cell package contains a set of wafers.