KR102665955B1 - A method for interconnecting chips, a interconnecting device and a method of forming pakages - Google Patents

A method for interconnecting chips, a interconnecting device and a method of forming pakages Download PDF

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Publication number
KR102665955B1
KR102665955B1 KR1020210171478A KR20210171478A KR102665955B1 KR 102665955 B1 KR102665955 B1 KR 102665955B1 KR 1020210171478 A KR1020210171478 A KR 1020210171478A KR 20210171478 A KR20210171478 A KR 20210171478A KR 102665955 B1 KR102665955 B1 KR 102665955B1
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South Korea
Prior art keywords
chip
interconnection
bumps
pads
interconnection element
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KR1020210171478A
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Korean (ko)
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KR20220079468A (en
Inventor
리 웨이핑
Original Assignee
상하이 이부 세미컨덕터 컴퍼니 리미티드
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Publication of KR20220079468A publication Critical patent/KR20220079468A/en
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Publication of KR102665955B1 publication Critical patent/KR102665955B1/en

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    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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  • Engineering & Computer Science (AREA)
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Abstract

본 발명은 칩 상호연결 방법, 상호연결 소자 및 패키지 형성 방법을 제공하며, 상기 칩 상호연결 방법은, 상부 표면에 접촉면이 제2 범프보다 작은 복수의 제1 범프가 형성된 제1 칩과 상부 표면에 복수의 제2 범프가 형성된 제2 칩을 캐리어 표면에 설치하는 단계; 복수의 제1 범프에 본딩되기 위한 복수의 제1 패드 및 복수의 제2 범프에 본딩되기 위한 복수의 제2 패드가 일측 표면에 형성된 상호연결 소자를 제1 칩과 제2 칩의 일부 상부 표면에 부착하는 단계를 포함하며, 여기서 상호연결 소자의 복수의 제1 패드를 복수의 제1 범프에 정렬시켜 본딩함으로써, 상호연결 소자의 복수의 제2 패드와 복수의 제2 범프의 자기정렬 본딩을 구현한다. 상기 방법을 이용하여, 오차로 인해 정렬 본딩이 어려운 문제를 피할 수 있다. The present invention provides a chip interconnection method, an interconnection element, and a package formation method, wherein the chip interconnection method includes a first chip having a plurality of first bumps formed on the upper surface and a contact surface smaller than the second bump, and an upper surface. Installing a second chip on which a plurality of second bumps are formed on the surface of the carrier; An interconnection element having a plurality of first pads for bonding to a plurality of first bumps and a plurality of second pads for bonding to a plurality of second bumps formed on one surface is placed on a portion of the upper surface of the first chip and the second chip. A step of attaching, wherein the plurality of first pads of the interconnection element are aligned and bonded to the plurality of first bumps, thereby implementing self-aligned bonding of the plurality of second pads and the plurality of second bumps of the interconnection element. do. Using the above method, the problem of difficult alignment bonding due to errors can be avoided.

Description

칩 상호연결 방법, 상호연결 소자 및 패키지 형성 방법{A method for interconnecting chips, a interconnecting device and a method of forming pakages} {A method for interconnecting chips, a interconnecting device and a method of forming packages}

본 발명은 반도체 분야에 속하며, 구체적으로는 칩 상호연결 방법, 상호연결 소자 및 패키지 형성 방법에 관한 것이다.The present invention belongs to the field of semiconductors, and specifically relates to chip interconnection methods, interconnection elements, and package formation methods.

본 부분은 청구항에 진술된 본 발명의 실시방식에 대해 배경 또는 맥락을 제공하기 위한 것이다. 여기에 기술된 내용이 본 부분에 포함되었다고 해서 종래 기술로 인정되는 것은 아니다.This section is intended to provide background or context for the practice of the invention as set forth in the claims. The inclusion of the content described herein in this part does not mean that it is recognized as prior art.

인공지능 시대가 도래함에 따라, 반도체 집적회로의 발전은 기능은 갈수록 많아지고 계산속도는 갈수록 빨라지는 추세이다. "무어의 법칙"으로 인해, 단순히 대형 칩의 SOC 집적으로 이러한 발전 추세를 충족시킨다면, 회로 설계의 난이도는 점점 더 높아지고, 제조비용은 더욱 비싸질 것이 틀림없다. 보다 실제적인 해결방안은 복수의 소형 칩의 이종 집적화 기술을 이용하여 기능을 집적시키는 목적을 완수하는 것이다. 이를 바탕으로, 현재 하이엔드 패키징의 중요 임무는 고효율, 고밀도 멀티칩 상호연결 기술을 발전시키는 것이며, 베어칩 사이의 직접적인 연결을 통해 칩의 물리계층 기능 블록을 형성하여, 대형 칩의 SOC 집적을 대체함으로써, 저비용 및 높은 자유도를 구현하면서도 동일한 기능성을 갖추도록 하는 것이다.With the advent of the artificial intelligence era, the development of semiconductor integrated circuits is trending towards increasing functions and faster calculation speeds. Due to "Moore's Law", if this development trend is met simply by SOC integration on large chips, the difficulty of circuit design will become increasingly higher and the manufacturing cost will inevitably become more expensive. A more practical solution is to achieve the purpose of integrating functions using heterogeneous integration technology of multiple small chips. Based on this, the important task of current high-end packaging is to develop high-efficiency, high-density multi-chip interconnection technology, and form the physical layer functional block of the chip through direct connection between bare chips, replacing the SOC integration of large chips. By doing so, it achieves low cost and high degree of freedom while maintaining the same functionality.

종래의 멀티칩 상호연결 기술에서는 반도체 칩의 패키징 과정 중의 실장 오차가 불가피하게 존재하므로, 멀티칩과 상호연결 소자 간의 정렬 본딩을 구현하기 어렵다.In conventional multichip interconnection technology, placement errors inevitably exist during the packaging process of semiconductor chips, making it difficult to implement alignment bonding between multichips and interconnection elements.

상기 종래 기술에 존재하는 문제점에 대해, 칩 상호연결 방법, 상호연결 소자 및 패키지 형성방법을 제안하며, 이러한 방법, 소자 및 패키지를 이용하여 상기 문제를 해결할 수 있다.In response to the problems existing in the prior art, a chip interconnection method, an interconnection element, and a package formation method are proposed, and the above problems can be solved by using these methods, elements, and packages.

본 발명은 이하 방안을 제공한다.The present invention provides the following solution.

첫 번째 측면으로, 칩 상호연결 방법을 제공하며, 이는 상부 표면에 접촉면이 제2 범프보다 작은 복수의 제1 범프가 형성된 제1 칩과 상부 표면에 복수의 제2 범프가 형성된 제2 칩을 캐리어 표면에 설치하는 단계; 복수의 제1 범프에 본딩되기 위한 복수의 제1 패드 및 복수의 제2 범프에 본딩되기 위한 복수의 제2 패드가 일측 표면에 형성된 상호연결 소자를 제1 칩과 제2 칩의 일부 상부 표면에 부착하는 단계를 포함하며, 여기서 상호연결 소자의 복수의 제1 패드를 복수의 제1 범프에 정렬시켜 본딩함으로써, 상호연결 소자의 복수의 제2 패드와 복수의 제2 범프의 자기정렬(self alignment) 본딩을 구현한다.In a first aspect, a chip interconnection method is provided, which includes a first chip having a plurality of first bumps formed on the upper surface and a contact surface smaller than the second bump, and a second chip having a plurality of second bumps formed on the upper surface of the carrier. installing on a surface; An interconnection element having a plurality of first pads for bonding to a plurality of first bumps and a plurality of second pads for bonding to a plurality of second bumps formed on one surface is placed on a portion of the upper surface of the first chip and the second chip. A step of attaching, wherein the plurality of first pads of the interconnection element are aligned and bonded to the plurality of first bumps, thereby self-aligning the plurality of second pads of the interconnection element and the plurality of second bumps. ) Implement bonding.

일부 가능한 실시방식에서, 제1 칩의 복수의 제1 범프는 복수의 고밀도 범프이고, 제2 칩의 복수의 제2 범프는 복수의 저밀도 범프이다.In some possible implementations, the first plurality of bumps on the first chip are a plurality of high density bumps and the second plurality of bumps on the second chip are a plurality of low density bumps.

일부 가능한 실시방식에서, 각 그룹의 칩에 포함된 제1 칩이 상호연결 소자를 통해 제2 칩에 전기적으로 연결될 수 있도록, 상호연결 소자의 복수의 제1 패드와 복수의 제2 패드 사이에 팬아웃 회로를 형성한다. In some possible implementations, a fan is provided between the plurality of first pads and the plurality of second pads of the interconnection elements such that the first chips included in each group of chips can be electrically connected to the second chips through the interconnection elements. Forms an out circuit.

일부 가능한 실시방식에서, 상호연결 소자는 수직 상호연결 관통 비아를 구비한 상호연결 소자로 형성된다.In some possible implementations, the interconnection elements are formed as interconnection elements with vertical interconnection through vias.

일부 가능한 실시방식에서, 상호연결 소자는 수동소자 또는 능동소자로 형성된다.In some possible implementations, the interconnection elements are formed as passive or active elements.

두 번째 측면으로, 일측 표면에 제1 칩에 본딩되기 위한 복수의 제1 패드와 제2 칩에 본딩되기 위한 복수의 제2 패드가 형성된 상호연결 소자를 제공하며; 상호연결 소자의 복수의 제1 패드와 복수의 제2 패드 사이에, 복수의 제1 패드와 복수의 제2 패드 사이의 전기적인 연결을 구현하기 위한 팬아웃 회로가 형성된다.In a second aspect, an interconnection element is provided on one surface of which a plurality of first pads for bonding to a first chip and a plurality of second pads for bonding to a second chip are formed; A fan-out circuit is formed between the plurality of first pads and the plurality of second pads of the interconnection element to implement electrical connection between the plurality of first pads and the plurality of second pads.

일부 가능한 실시방식에서, 상호연결 소자는 수직 상호연결 관통 비아를 구비한 상호연결 소자로 형성된다.In some possible implementations, the interconnection elements are formed as interconnection elements with vertical interconnection through vias.

일부 가능한 실시방식에서, 상호연결 소자는 수동소자 또는 능동소자로 형성된다.In some possible implementations, the interconnection elements are formed as passive or active elements.

일부 가능한 실시방식에서, 상호연결 소자는 실리콘(Si), 탄화규소(SiC), 비소화 갈륨(GaAs), 질화 갈륨(GaN) 중의 하나 이상을 포함하는 반도체 소재를 채택한다.In some possible implementations, the interconnection elements employ semiconductor materials including one or more of silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), and gallium nitride (GaN).

일부 가능한 실시방식에서, 상호연결 소자는 유리, 세라믹 중의 하나 이상을 포함하는 무기재료를 채택한다.In some possible implementations, the interconnection elements employ inorganic materials including one or more of glass, ceramics.

일부 가능한 실시방식에서, 상호연결 소자는 인쇄회로기판(PCB), 몰드 기판(EMC), 연성회로기판 중의 하나 이상을 포함하는 패키지 기판 소재를 채택한다.In some possible implementations, the interconnection elements employ packaged substrate materials including one or more of printed circuit boards (PCBs), molded boards (EMCs), and flexible circuit boards.

일부 가능한 실시방식에서, 상호연결 소자는 구리, 알루미늄 중의 하나 이상을 포함하는 금속 기판 소재를 채택한다.In some possible implementations, the interconnection elements employ a metal substrate material comprising one or more of copper and aluminum.

일부 가능한 실시방식에서, 상호연결 소자는 부가적으로 집적회로, 미세전자기계시스템(MEMS), 광전자 소자 및 수동 소자(IPD)의 기능을 갖는다. In some possible implementations, the interconnect devices additionally have the functionality of integrated circuits, microelectromechanical systems (MEMS), optoelectronic devices, and passive devices (IPDs).

세 번째 측면으로, 패키지 형성 방법을 제공하며, 이는 캐리어 및, 각각 적어도 제1 칩과 제2 칩을 포함하는 적어도 한 그룹의 칩을 제공하는 단계; 각 그룹의 칩에 포함된, 상부 표면에 제1 범프를 구비한 제1 칩과 상부 표면에 제2 범프를 구비한 제2 칩을 정면이 위를 향하도록 캐리어 표면에 설치하는 단계; 첫 번째 측면의 방법을 이용하여 각 그룹의 칩에 포함된 제1 칩이 상호연결 소자를 통해 제2 칩에 전기적으로 연결될 수 있도록, 상호연결 소자를 각 그룹의 칩에 포함된 제1 칩과 제2 칩의 일부 상부 표면에 부착하는 단계; 제1 칩과 제2 칩의 주위에 몰딩층을 형성하여, 제1 칩, 제2 칩과 상호연결 소자가 몰딩층 내에 감입되도록 하는 단계; 몰딩층의 캐리어에서 먼 일측 표면에 박화 처리를 수행하여, 제1 칩의 제1 범프와 제2 칩의 제2 범프를 노출시키는 단계; 몰딩층의 제1 범프와 제2 범프가 노출된 일측 표면에 제3 범프를 형성하는 단계; 및, 캐리어를 제거하는 단계를 포함한다. In a third aspect, a method of forming a package is provided, comprising providing a carrier and at least one group of chips each including at least a first chip and a second chip; Installing a first chip with a first bump on an upper surface and a second chip with a second bump on an upper surface included in each group of chips on the carrier surface with the front facing upward; Using the method of the first aspect, the interconnection element is connected to the first chip and the second chip included in each group of chips so that the first chip included in each group of chips can be electrically connected to the second chip through the interconnection element. 2 Attaching to some upper surface of the chip; forming a molding layer around the first chip and the second chip so that the first chip, the second chip, and the interconnection elements are inserted into the molding layer; performing a thinning treatment on a surface of the molding layer farthest from the carrier to expose the first bump of the first chip and the second bump of the second chip; forming a third bump on one surface of the molding layer where the first and second bumps are exposed; and removing the carrier.

일부 가능한 실시방식에서, 칩 그룹의 수량은 1보다 크며, 방법은 캐리어를 제거한 후, 형성된 패키지에 대해 절단을 수행하여, 복수의 유닛 패키지를 획득하는 단계를 더 포함하며, 각 유닛 패키지는 한 그룹의 칩을 포함한다.In some possible implementations, the quantity of chip groups is greater than 1, and the method further includes removing the carrier and then performing cutting on the formed package to obtain a plurality of unit packages, each unit package being one group. Includes chips of

본 출원의 실시예는 상기 적어도 하나의 기술방안을 적용하여 다음과 같은 유익한 효과를 얻을 수 있다: 반도체 칩을 패키징하는 과정에서, 실장 오차가 불가피하게 존재한다는 것을 이해할 수 있다. 본 실시예에서, 제2 범프는 더 큰 접촉 면적으로 인해 더 큰 오차 허용 공간을 지니므로, 먼저 제1 범프와 제1 패드를 정확하게 정렬시켜 본딩함으로써, 이를 통해 상호연결 소자의 복수의 제2 패드가 더 큰 오차 허용 공간을 지닌 복수의 제2 범프로 자기정렬되어 본딩되도록 할 수 있으며, 오차로 인해 정렬 본딩이 어려운 문제를 피할 수 있다.The embodiments of the present application can achieve the following beneficial effects by applying the at least one technical solution above: It can be understood that in the process of packaging a semiconductor chip, mounting errors inevitably exist. In this embodiment, since the second bump has a larger error tolerance due to its larger contact area, the first bump and the first pad are first accurately aligned and bonded, thereby forming a plurality of second pads of the interconnection element. can be self-aligned and bonded with a plurality of second bumps with a larger error tolerance space, and problems in which alignment bonding is difficult due to errors can be avoided.

상기 설명은 단지 본 발명의 기술수단을 보다 명확하게 이해하고 명세서의 내용에 따라 실시할 수 있도록 본 발명의 기술방안에 대해 개략적으로 기술한 것에 불과하다는 점을 이해하여야 한다. 본 발명의 상기 및 기타 목적, 특징과 장점이 더욱 명확하고 쉽게 이해될 수 있도록, 이하 본 발명의 구체적인 실시방식을 특별히 예시를 들어 설명한다.It should be understood that the above description is merely a rough description of the technical solution of the present invention so that the technical means of the present invention can be more clearly understood and implemented according to the contents of the specification. In order that the above and other objects, features and advantages of the present invention can be more clearly and easily understood, specific implementation methods of the present invention will be described below with particular examples.

이하 예시적인 실시예의 상세한 설명을 통해, 당업계의 보통의 기술자라면 본문의 상기 장점과 이점 및 기타 장점과 이점을 명백히 이해하게 될 것이다. 도면은 단지 실시예를 예시적으로 나타내기 위한 목적일 뿐이며, 본 발명을 제한하는 것으로 여겨서는 안 된다. 또한 전체 도면에서, 동일한 부호는 동일한 부재를 나타낸다. 도면에서,
도 1은 본 발명의 일 실시예에 따른 반도체 패키지 형성 방법의 흐름도이다.
도 2a 내지 도 2e는 본 발명의 일 실시예에 따라 패키지를 형성하는 과정 중의 중간 단계의 단면 설명도이다.
도 3a 내지 도 3c는 본 발명의 다른 일 실시예에 따라 칩을 상호 연결하는 과정 중의 설명도이다.
도 4는 본 발명의 일 실시예에 따른 상호연결 소자를 사용하는 적층된 칩 패키지의 구조 설명도이다.
도면에서, 동일하거나 대응되는 부호는 동일하거나 또는 대응되는 부분을 나타낸다.Through the detailed description of the exemplary embodiments below, those skilled in the art will clearly understand the above and other advantages and advantages of the text. The drawings are merely for illustrative purposes and should not be construed as limiting the present invention. Also, throughout the drawings, like symbols represent like members. In the drawing,
1 is a flowchart of a method of forming a semiconductor package according to an embodiment of the present invention.
2A to 2E are cross-sectional views illustrating an intermediate step in the process of forming a package according to an embodiment of the present invention.
3A to 3C are diagrams illustrating the process of interconnecting chips according to another embodiment of the present invention.
Figure 4 is a structural diagram of a stacked chip package using an interconnection element according to an embodiment of the present invention.
In the drawings, identical or corresponding symbols indicate identical or corresponding parts.

이하 첨부도면을 참조하여 본 공개의 예시적 실시예를 보다 상세히 기술하고자 한다. 비록 도면에서 본 공개의 예시적인 실시예를 나타내었으나, 각종 형식으로 본 공개를 구현할 수 있으므로 여기에 기술된 실시예로 한정해서는 안됨을 이해하여야 한다. 반대로, 이러한 실시예는 단지 본 공개를 보다 철저히 이해할 수 있도록 하고, 또한 본 공개의 범위를 당업계의 기술자에게 완벽하게 전달하기 위한 것에 불과하다. Hereinafter, exemplary embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. Although the drawings show exemplary embodiments of the present disclosure, it should be understood that the disclosure may be implemented in various forms and should not be limited to the embodiments described herein. On the contrary, these embodiments are merely intended to provide a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

이하 공개 내용은 본 발명의 상이한 특징을 구현하기 위한 다양한 상이한 실시예 또는 구현예를 제공한다. 이하 본 발명을 단순화하기 위하여 어셈블리와 배치의 구체적인 구현예를 기술한다. 물론, 이는 단지 구현예일뿐이며, 본 발명을 제한하고자 하는 것이 아니다. 예를 들어, 이하 기재에서, 상호연결 소자(13)를 제1 칩(11)과 제2 칩(12)의 상부 표면에 부착하는 단계는 제1 칩(11), 제2 칩(12)과 상호연결 소자(13)를 직접 접촉시켜 형성되는 실시예를 포함할 수도 있고, 제1 칩(11), 제2 칩(12)과 상호연결 소자(13) 사이에 별도의 부재를 형성하여, 제1 칩(11), 제2 칩(12)과 상호연결 소자(13)가 직접적으로 접촉되지 않도록 하는 실시예를 포함할 수도 있다. 또한, 본 발명은 각 실시예에서 부호 및/또는 문자 부호를 반복적으로 참고할 수 있다. 상기 반복은 단순성 및 명확성의 목적을 위한 것이며, 또한 그 자체는 논의되는 각 실시예 및/또는 구성 간의 관계를 나타내는 것이 아니다. The following disclosure provides various different embodiments or implementations for implementing different features of the invention. In order to simplify the present invention, specific examples of assembly and arrangement are described below. Of course, this is just an implementation example and is not intended to limit the invention. For example, in the following description, the step of attaching the interconnection element 13 to the upper surfaces of the first chip 11 and the second chip 12 includes the first chip 11, the second chip 12, and An embodiment may be formed by directly contacting the interconnection elements 13, and a separate member may be formed between the first chip 11, the second chip 12, and the interconnection elements 13, An embodiment may be included in which the first chip 11, the second chip 12, and the interconnection element 13 are not directly contacted. Additionally, the present invention may repeatedly refer to symbols and/or letter symbols in each embodiment. The above repetition is for purposes of simplicity and clarity and does not by itself indicate a relationship between each embodiment and/or configuration discussed.

이해하여야 할 점은, "포함하다" 또는 "구비하다" 등의 용어는 본 명세서에 공개된 특징, 숫자, 단계, 행위, 부재, 부분 또는 이들의 조합이 존재한다는 것을 지시하기 위한 것이지, 하나 또는 복수의 기타 특징, 숫자, 단계, 행위, 부재, 부분 또는 이들의 조합이 존재할 가능성을 배제하고자 하는 것이 아니다. It should be understood that terms such as "comprise" or "comprising" are intended to indicate the presence of features, numbers, steps, acts, members, parts, or combinations thereof disclosed herein, but are not intended to indicate the presence of one or It is not intended to exclude the possibility that a plurality of other features, numbers, steps, actions, members, parts, or combinations thereof may exist.

또한, 설명의 편의를 위하여, "~의 아래", "~하부에", "하부", "~의 위에", "상부" 등 공간 상대적인 용어를 사용하여 도시된 바와 같은 하나의 소자 또는 부재와 다른(또는 다른 일부) 소자 또는 부재의 관계를 기술할 수 있다. 도시된 방위 이외에, 공간 상대적 용어는 소자를 사용하거나 조작 시의 상이한 방위를 포함하기 위한 것이다. 소자는 기타 방식으로 방향을 정할 수 있으며(90도 회전 또는 다른 방위에서), 본문에서 사용되는 공간 상대적인 기술용어 역시 상응하게 해석될 수 있다. In addition, for convenience of explanation, spatial relative terms such as “below”, “at the bottom”, “lower part”, “above”, “upper”, etc. are used to describe an element or member as shown. It can describe relationships between other (or some other) elements or members. In addition to the orientations shown, spatially relative terms are intended to encompass other orientations when using or operating the device. The elements may be oriented in other ways (rotated by 90 degrees or in other orientations), and the spatially relative technical terms used in the text may be interpreted accordingly.

또한 충돌이 없는 한, 본 발명 중의 실시예 및 실시예 중의 특징은 서로 조합 가능하다는 점을 더 설명해둔다. 이하 첨부도면을 참조하고 실시예를 결합하여 본 발명에 대해 상세히 설명한다.Additionally, it will be further explained that the embodiments and features of the embodiments of the present invention can be combined with each other as long as there is no conflict. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings and combining embodiments.

도 1은 본 출원의 일 실시예에 따른 패키지 형성 방법(100)의 흐름 설명도이다. 도 1에 도시된 바와 같이, 상기 방법(100)은 단계 101 내지 102를 포함한다.Figure 1 is a flow diagram of a package forming method 100 according to an embodiment of the present application. As shown in Figure 1, the method 100 includes steps 101-102.

단계 101: 제1 칩과 제2 칩을 캐리어 표면에 설치하는 단계.Step 101: Installing the first chip and the second chip on the carrier surface.

도 2a를 참조하면, 미리 설계해 놓은 사전 설정 칩 간격 또는 사전 설정 칩 배치 위치에 따라 제1 칩(11)과 제2 칩(12)의 정면이 위를 향하도록 하여 캐리어(10)의 표면에 설치할 수 있다. 제1 칩(11)의 상부 표면은 제1 범프(21)를 구비하고, 제2 칩(12)의 상부 표면은 제2 범프(22)를 구비한다. 범프는 칩 핀(chip pin)이라고도 칭할 수 있으며, 칩 핀을 구비한 측 표면을 칩의 정면이라 칭하고, 정면과 반대되는 측의 표면을 배면이라 칭한다. 예를 들어, 일부 실시예에서, 제1 범프(21)와 제2 범프(22)는 전도성 소재로 제작되는 솔더 범프로 형성될 수 있으며, 전도성 소재는 Cu, Ag, Au 등 또는 이들의 합금을 포함할 수도 있고, 기타 소재를 포함할 수도 있다. 예를 들어, 일부 실시예에서, 예컨대 패키징 기기와 같은 자동화 기기를 사용하거나 또는 수동으로 2개 또는 복수의 칩을 캐리어(10)에 연결할 수 있다. 일부 실시예에서, 접착 필름(미도시) 또는 칩 부착 필름(die attach film)(미도시)을 사용하여 제1 칩(11)과 제2 칩(12)의 배면을 캐리어(10)의 임의의 일 측면에 결합시킴으로써, 제1 칩(11)과 제2 칩(12)의 정면이 캐리어(10)에서 먼 바깥쪽으로 보여지게 할 수 있으며, 반도체 패키지에서, 이를 페이스 업(face-up)이라고도 칭한다.Referring to FIG. 2A, the first chip 11 and the second chip 12 are placed on the surface of the carrier 10 with the front faces facing upward according to the preset chip spacing or preset chip arrangement position. Can be installed. The upper surface of the first chip 11 is provided with a first bump 21 and the upper surface of the second chip 12 is provided with a second bump 22 . A bump may also be called a chip pin, and the surface on the side with the chip pin is called the front side of the chip, and the surface on the side opposite to the front side is called the back side. For example, in some embodiments, the first bump 21 and the second bump 22 may be formed of solder bumps made of a conductive material, the conductive material being Cu, Ag, Au, etc., or alloys thereof. It may include other materials. For example, in some embodiments, two or more chips may be connected to the carrier 10 manually or using automated equipment, such as a packaging machine. In some embodiments, an adhesive film (not shown) or a die attach film (not shown) is used to attach the back surfaces of the first chip 11 and the second chip 12 to any part of the carrier 10. By combining them on one side, the front of the first chip 11 and the second chip 12 can be seen outward away from the carrier 10, and in a semiconductor package, this is also called face-up. .

도 3a를 참조하면, 제1 칩(11)과 제2 칩(12)의 평면도(top view)이다. 본 실시예에서, 제1 칩(11)과 제2 칩(12)은 캐리어 표면에 간격을 두고 나란히 배열되며, 제1 칩의 제1 가장자리 영역과 제2 칩의 제2 가장자리 영역은 제1 칩과 제2 칩 사이의 간극의 양측에 분포된다. 제1 칩(11)의 제1 가장자리 영역은 복수의 제1 범프(21)를 포함하고, 제2 칩의 제2 가장자리 영역은 복수의 제2 범프(22)를 포함한다. 여기서, 제1 범프(21)의 접촉면은 제2 범프(22)의 접촉면보다 작다.Referring to FIG. 3A, it is a top view of the first chip 11 and the second chip 12. In this embodiment, the first chip 11 and the second chip 12 are arranged side by side with an interval on the carrier surface, and the first edge area of the first chip and the second edge area of the second chip are and is distributed on both sides of the gap between the second chip. The first edge area of the first chip 11 includes a plurality of first bumps 21, and the second edge area of the second chip includes a plurality of second bumps 22. Here, the contact surface of the first bump 21 is smaller than the contact surface of the second bump 22.

반도체 칩의 패키징 과정에서, 실장 오차가 불가피하게 존재한다는 것을 이해할 수 있을 것이다. 단계 101에서, 제1 칩(11)과 제2 칩(12)을 캐리어(10)의 일측 표면에 실장 시, 일정 정도의 실장 간격 오차가 발생할 수 있다. 예를 들어, 제1 칩(11)과 제2 칩(12) 사이의 실제 칩 간격은 사전에 설계된 사전 설정 칩 간격보다 가깝거나 멀 수 있다. 또한 예를 들어, 사전에 설계된 칩 배치 위치는 제1 칩(11)과 제2 칩(12)이 나란히 평행하게 배치되도록 하는 것이나, 실제 배치 과정에서, 제1 칩(11)과 제2 칩(12)은 완전히 평행하게 배치될 수 있는 것이 아니라 각도의 오차가 존재한다. 칩 배치 과정에서 이러한 실장 오차는 피하기 어렵다. You will understand that in the packaging process of semiconductor chips, placement errors inevitably exist. In step 101, when the first chip 11 and the second chip 12 are mounted on one surface of the carrier 10, a certain amount of mounting spacing error may occur. For example, the actual chip spacing between the first chip 11 and the second chip 12 may be closer or farther than a preset chip spacing designed in advance. Also, for example, the pre-designed chip placement position is such that the first chip 11 and the second chip 12 are arranged parallel to each other, but in the actual arrangement process, the first chip 11 and the second chip ( 12) cannot be placed completely parallel and there is an error in the angle. It is difficult to avoid such placement errors during the chip placement process.

단계 102: 상호연결 소자를 제1 칩과 제2 칩의 일부 상부 표면에 부착하는 단계.Step 102: Attaching interconnection elements to some upper surfaces of the first and second chips.

도 3b를 참조하면, 상호연결 소자(13)의 일측 표면에 복수의 제1 패드(131)와 복수의 제2 패드(132)가 형성된다. 복수의 제1 패드(131)는 제1 칩(11) 상부 표면에 형성된 복수의 제1 범프(21)에 본딩되기 위한 것이고, 복수의 제2 패드(132)는 제2 칩(12) 상부 표면에 형성된 복수의 제2 범프(22)에 본딩되기 위한 것이다.Referring to FIG. 3B, a plurality of first pads 131 and a plurality of second pads 132 are formed on one surface of the interconnection element 13. The plurality of first pads 131 are for bonding to the plurality of first bumps 21 formed on the upper surface of the first chip 11, and the plurality of second pads 132 are on the upper surface of the second chip 12. It is for bonding to the plurality of second bumps 22 formed in .

본 실시예에서, 상호연결 소자(13)는 제1 칩과 제2 칩 사이의 간격을 가로질러 제1 칩의 제1 가장자리 영역과 제2 칩의 제2 가장자리 영역 상부에 부착되기 위한 것이다. 상호연결 소자(13)의 일측 표면에 분포되는 복수의 제1 패드(131)는 제1 가장자리 영역에 포함되는 복수의 제1 범프(21)와 서로 본딩되기 위한 것이고, 분포되는 복수의 제2 패드(132)는 제2 가장자리 영역에 포함되는 복수의 제2 범프(22)와 서로 본딩되기 위한 것이다. 상호연결 소자 중의 복수의 제1 패드(131)와 복수의 제2 패드(132)의 패드 위치는 미리 설정된 칩 배치 위치 및 제1 칩(11), 제2 칩(12) 상의 범프 분포 위치에 의해 결정된다는 점을 이해하여야 한다. 예를 들어, 칩 설계 시 확정된 제1 칩(11)과 제2 칩(12) 사이의 칩 간격이 비교적 넓을 경우, 도 3a에 도시된 제1 칩(11)과 제2 칩(12)은 설계된 비교적 넓은 칩 간격에 따라 배치해야 하고, 도 3b에 도시된 상호연결 소자(13) 역시 마찬가지로 더 넓게 설계되어야 한다. 구체적으로, 상호연결 소자(13) 중 제1 패드 영역과 제2 패드 영역 사이의 폭이 더 넓다. 다시 말해, 이상적인 상황에서, 즉 상기 실장 오차가 없는 경우, 상호연결 소자(13)는 제1 칩(11)과 제2 칩(12)의 상부에 부착될 수 있으며, 상호연결 소자(13) 중의 복수의 제1 패드(131)와 복수의 제2 패드(132)가 제1 칩과 제2 칩 상부의 대응되는 범프에 동시에 정확하게 본딩될 수 있다. In this embodiment, the interconnection element 13 is for attaching across the gap between the first chip and the second chip and on top of the first edge region of the first chip and the second edge region of the second chip. A plurality of first pads 131 distributed on one surface of the interconnection element 13 are for bonding to each other with a plurality of first bumps 21 included in the first edge area, and a plurality of second pads distributed Reference numeral 132 is for bonding to the plurality of second bumps 22 included in the second edge area. The pad positions of the plurality of first pads 131 and the plurality of second pads 132 in the interconnection elements are determined by the preset chip arrangement position and the bump distribution position on the first chip 11 and the second chip 12. You must understand that it is decided. For example, if the chip gap between the first chip 11 and the second chip 12 determined during chip design is relatively wide, the first chip 11 and the second chip 12 shown in FIG. 3A are It must be arranged according to the designed relatively wide chip spacing, and the interconnection element 13 shown in FIG. 3B must also be designed to be wider as well. Specifically, the width between the first pad area and the second pad area of the interconnection element 13 is wider. In other words, in an ideal situation, that is, when there is no mounting error, the interconnection element 13 can be attached to the top of the first chip 11 and the second chip 12, and one of the interconnection elements 13 A plurality of first pads 131 and a plurality of second pads 132 can be accurately bonded to corresponding bumps on the top of the first chip and the second chip at the same time.

단계 101에서, 실장 오차를 피하기 어렵기 때문에, 본 실시예에서 상호연결 소자(13)를 제1 칩(11)과 제2 칩(12)의 상부 표면에 부착하는 구체적인 실장 단계는, 상호연결 소자(13)의 복수의 제1 패드를 복수의 제1 범프에 정렬시켜 본딩함으로써, 상호연결 소자(13)의 복수의 제2 패드(132)가 제2 칩의 복수의 제2 범프(22)에 자기정렬되어 본딩되도록 하는 것이다. 다시 말해, 이미 정렬되어 본딩된 복수의 제1 범프(21)와 제1 패드(131)를 참고 기준으로 삼아, 상호연결 소자(13)의 복수의 제2 패드(132)는 소자 자체의 장력에 따라 복수의 제2 범프로 자기정렬되어 본딩된다. In step 101, since it is difficult to avoid mounting errors, the specific mounting step of attaching the interconnection element 13 to the upper surfaces of the first chip 11 and the second chip 12 in this embodiment is, By aligning and bonding the plurality of first pads of (13) to the plurality of first bumps, the plurality of second pads 132 of the interconnection element 13 are connected to the plurality of second bumps 22 of the second chip. This is to ensure self-alignment and bonding. In other words, using the plurality of first bumps 21 and first pads 131 that are already aligned and bonded as a reference standard, the plurality of second pads 132 of the interconnection element 13 are adjusted to the tension of the element itself. Accordingly, it is self-aligned and bonded with a plurality of second bumps.

도 3c를 참조하면, 본 실시예에서, 먼저 제1 범프(21)와 제1 패드(131)를 정확하게 정렬시킴으로써, 제1 범프(21)와 제1 패드(131) 사이의 정렬 본딩을 구현할 수 있으며, 상호연결 소자의 복수의 제1 패드(131)와 복수의 제1 범프(21)가 서로 본딩된 후에는 상호연결 소자의 실제 배치 위치가 이미 확정되게 된다. 이때 제2 범프(22)는 접촉 면적이 더 크므로 더 큰 오차 허용 공간을 지니며, 상호연결 소자(13) 자체의 장력에 따라, 복수의 제2 패드(132)가 더 큰 오차 허용 공간을 지닌 복수의 제2 범프로 자기정렬되어 본딩될 수 있다. 따라서, 복수의 제1 범프(21)와 복수의 제1 패드(131) 사이의 정렬 본딩, 및 복수의 제2 범프(22)와 복수의 제2 패드(132) 사이의 자기정렬 본딩을 구현할 수 있어, 오차로 인해 정렬 본딩이 어려운 문제를 피할 수 있다.Referring to FIG. 3C, in this embodiment, alignment bonding between the first bump 21 and the first pad 131 can be implemented by first accurately aligning the first bump 21 and the first pad 131. After the plurality of first pads 131 and the plurality of first bumps 21 of the interconnection element are bonded to each other, the actual arrangement position of the interconnection element is already determined. At this time, the second bump 22 has a larger error tolerance space because the contact area is larger, and depending on the tension of the interconnection element 13 itself, the plurality of second pads 132 have a larger error tolerance space. It can be self-aligned and bonded with a plurality of second bumps. Therefore, alignment bonding between the plurality of first bumps 21 and the plurality of first pads 131 and self-aligned bonding between the plurality of second bumps 22 and the plurality of second pads 132 can be implemented. Therefore, it is possible to avoid problems with alignment bonding difficulties due to errors.

일부 실시방안에서, 제1 범프(21)와 제1 패드(131)는 동일하거나 유사한 형상, 크기의 접촉면을 가질 수 있어, 제1 범프(21)와 제1 패드(131) 사이의 정확한 정렬을 용이하게 할 수 있고, 제1 범프(21)와 제1 패드(131) 사이의 정렬 오차로 인해 제2 범프(22)와 제2 패드(132) 사이에 추가로 발생되는 정렬 오차의 증가를 피하거나 감소시킬 수 있다. In some implementations, the first bump 21 and the first pad 131 may have contact surfaces of the same or similar shape and size to ensure accurate alignment between the first bump 21 and the first pad 131. This can be done easily, and an increase in the alignment error that is additionally generated between the second bump 22 and the second pad 132 due to the alignment error between the first bump 21 and the first pad 131 is avoided. It can be reduced or reduced.

일부 실시방식에서, 도 3a를 참조하면, 제1 칩(11)의 복수의 제1 범프(21)는 복수의 고밀도 범프이고, 제2 칩(12)의 복수의 제2 범프(22)는 복수의 저밀도 범프이다. 따라서, 고밀도 제1 범프(21)와 제1 패드(131)는 정렬 본딩을 구현할 수 있는 반면, 저밀도 제1 범프(22)는 접촉 면적이 더 크기 때문에 더욱 큰 오차 허용 공간을 지니므로, 오차로 인해 정렬 본딩이 어려운 문제를 피할 수 있다.In some implementations, referring to FIG. 3A, the plurality of first bumps 21 of the first chip 11 are a plurality of high-density bumps, and the plurality of second bumps 22 of the second chip 12 are a plurality of high-density bumps. is a low-density bump. Accordingly, the high-density first bump 21 and the first pad 131 can implement alignment bonding, while the low-density first bump 22 has a larger error tolerance due to its larger contact area, so the error This avoids problems with difficult alignment bonding.

일부 실시방식에서, 도 3b를 참조하면, 상호연결 소자(13)의 복수의 제1 패드(131)와 복수의 제2 패드(132) 사이에 팬아웃(fan-out) 회로(133)가 형성되며, 팬아웃 회로(133)는 연결되는 한 그룹의 제1 패드와 제2 패드 사이를 전기적으로 연결시켜, 상호연결 소자(13)가 제1 칩(11)과 제2 칩(11)에 부착된 후, 제1 칩(11)이 상호연결 소자(13)를 통해 제2 칩(12)에 전기적으로 연결될 수 있도록 하기 위한 것이다. In some implementations, referring to FIG. 3B, a fan-out circuit 133 is formed between the plurality of first pads 131 and the plurality of second pads 132 of the interconnection element 13. The fan-out circuit 133 electrically connects a group of first and second pads, so that the interconnection element 13 is attached to the first chip 11 and the second chip 11. This is so that the first chip 11 can be electrically connected to the second chip 12 through the interconnection element 13.

일부 다른 실시방식에서, 상호연결 소자(13)의 복수의 제1 패드(131)와 복수의 제2 패드(132) 사이는 다른 임의의 유형의 상호연결 회로를 형성할 수도 있으며, 상기 상호연결 회로가 어느 하나 또는 복수의 제1 패드(131)와 어느 하나 또는 복수의 제2 패드(132) 사이의 전기적인 연결을 구현할 수 있기만 하면 된다.In some other embodiments, any other type of interconnection circuit may be formed between the plurality of first pads 131 and the plurality of second pads 132 of the interconnection element 13, wherein the interconnection circuit All that is required is to be able to implement an electrical connection between one or more first pads 131 and one or more second pads 132.

일부 실시방식에서, 제1 패드(131)의 접촉면은 제2 패드(132)의 접촉면보다 작다. 따라서, 제2 패드(132)는 접촉 면적이 더 크기 때문에 더 큰 오차 허용 공간을 지니며, 제1 패드(131)와 제1 범프(21)가 정렬되어 본딩된 후, 상호연결 소자(13)의 더 큰 오차 허용 공간을 지닌 복수의 제2 패드(132)는 더 큰 오차 허용 공간을 지닌 복수의 제2 범프로 자기정렬되어 본딩될 수 있어, 오차 허용도가 더욱 향상된다.In some implementations, the contact surface of the first pad 131 is smaller than the contact surface of the second pad 132. Accordingly, the second pad 132 has a larger error tolerance space because the contact area is larger, and after the first pad 131 and the first bump 21 are aligned and bonded, the interconnection element 13 The plurality of second pads 132 having a larger error tolerance space can be self-aligned and bonded to a plurality of second bumps having a larger error tolerance space, thereby further improving error tolerance.

본 출원의 실시예는 상호연결 소자를 더 제공하며, 도 3b는 상기 상호연결 소자(13)의 구조 설명도이다. The embodiment of the present application further provides an interconnection element, and FIG. 3B is a structural diagram of the interconnection element 13.

도 3을 참조하면, 상기 상호연결 소자(13)의 일측 표면에 복수의 제1 패드(131)와 복수의 제2 패드(132)가 형성되며, 여기서, 복수의 제1 패드(131)는 제1 칩에 본딩되기 위한 것이고, 복수의 제2 패드(132)는 제2 칩에 본딩되기 위한 것이며; 상호연결 소자(13)의 복수의 제1 패드(131)와 복수의 제2 패드(132) 사이에 복수의 제1 패드와 복수의 제2 패드 사이의 전기적인 연결을 구현하기 위한 팬아웃 회로(133)가 형성된다.Referring to FIG. 3, a plurality of first pads 131 and a plurality of second pads 132 are formed on one surface of the interconnection element 13, where the plurality of first pads 131 are One is for bonding to a chip, and the plurality of second pads 132 are for bonding to a second chip; A fan-out circuit for implementing electrical connection between the plurality of first pads 131 and the plurality of second pads 132 of the interconnection element 13 ( 133) is formed.

일부 가능한 실시방식에서, 상호연결 소자는 수직 상호연결 관통 비아를 구비한 상호연결 소자로 형성된다.In some possible implementations, the interconnection elements are formed as interconnection elements with vertical interconnection through vias.

일부 가능한 실시방식에서, 상호연결 소자는 수동 소자 또는 능동 소자로 형성된다.In some possible implementations, the interconnection elements are formed as passive or active elements.

일부 가능한 실시방식에서, 상호연결 소자는 실리콘(Si), 탄화규소(SiC), 비소화 갈륨(GaAs), 질화 갈륨(GaN) 중의 하나 이상을 포함하는 반도체 소재를 채택한다.In some possible implementations, the interconnection elements employ semiconductor materials including one or more of silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), and gallium nitride (GaN).

일부 가능한 실시방식에서, 상호연결 소자는 유리, 세라믹 중의 하나 이상을 포함하는 무기재료를 채택한다.In some possible implementations, the interconnection elements employ inorganic materials including one or more of glass, ceramics.

일부 가능한 실시방식에서, 상호연결 소자는 인쇄회로기판(PCB), 몰드 기판(EMC), 연성회로기판 중의 하나 이상을 포함하는 패키지 기판 소재를 채택한다.In some possible implementations, the interconnection elements employ packaged substrate materials including one or more of printed circuit boards (PCBs), molded boards (EMCs), and flexible circuit boards.

일부 가능한 실시방식에서, 상호연결 소자는 구리, 알루미늄 중의 하나 이상을 포함하는 금속 기판 소재를 채택한다.In some possible implementations, the interconnection elements employ a metal substrate material comprising one or more of copper and aluminum.

일부 가능한 실시방식에서, 상호연결 소자는 부가적으로 집적회로, 미세전자기계시스템(MEMS), 광전자 소자 및 수동 소자(IPD)의 기능을 갖는다. 본 출원의 실시예는 패키지 형성 방법을 더 제공하며, 도 2a-도2e는 본 출원의 일 실시예의 과정 중의 중간 단계의 단면 설명도이다.In some possible implementations, the interconnect devices additionally have the functionality of integrated circuits, microelectromechanical systems (MEMS), optoelectronic devices, and passive devices (IPDs). An embodiment of the present application further provides a package forming method, and Figures 2A-2E are cross-sectional diagrams of intermediate steps in the process of an embodiment of the present application.

상기 방법은, 캐리어(10) 및 적어도 제1 칩(11)과 제2 칩(12)을 포함하는 적어도 한 그룹의 칩을 제공하는 단계; 도 2a를 참조하면, 각 그룹의 칩에 포함된, 상부 표면에 제1 범프(21)를 구비한 제1 칩(11)과 상부 표면에 제2 범프(22)를 구비한 제2 칩(12)을 정면이 위를 향하도록 캐리어(10)의 표면에 설치하는 단계; 상기 실시예와 같은 방법을 이용하여 각 그룹의 칩에 포함된 제1 칩(11)이 상호연결 소자(13)를 통해 제2 칩(12)에 전기적으로 연결될 수 있도록 상호연결 소자(13)를 각 그룹의 칩에 포함된 제1 칩(11)과 제2 칩(12)의 일부 상부 표면에 부착하는 단계; 도 2b를 참조하면, 제1 칩(11)과 제2 칩(12)의 주위에 몰딩층(30)을 형성하여, 제1 칩(11), 제2 칩(12)과 상호연결 소자(13)가 몰딩층(30) 내에 감입되도록 하는 단계; 도 2c를 참조하면, 몰딩층(30)의 캐리어(10)에서 먼 일측 표면에 대해 박화 처리를 수행하여, 제1 칩(11)의 제1 범프(21)와 제2 칩(12)의 제2 범프(22)를 노출시키는 단계; 도 2d를 참조하면, 몰딩층(30)의 제1 범프(21)와 제2 범프(22)가 노출된 일측 표면에 제3 범프(40)를 형성하는 단계; 및 도 2e를 참조하면, 캐리어(10)를 제거하는 단계를 포함한다. The method includes providing a carrier (10) and at least one group of chips comprising at least a first chip (11) and a second chip (12); Referring to FIG. 2A, each group of chips includes a first chip 11 with a first bump 21 on its upper surface and a second chip 12 with a second bump 22 on its upper surface. ) on the surface of the carrier 10 with the front facing upward; Using the same method as the above embodiment, the interconnection element 13 is installed so that the first chip 11 included in each group of chips can be electrically connected to the second chip 12 through the interconnection element 13. Attaching to some upper surfaces of the first chip 11 and the second chip 12 included in each group of chips; Referring to FIG. 2B, a molding layer 30 is formed around the first chip 11 and the second chip 12, so that the first chip 11, the second chip 12, and the interconnection element 13 ) is inserted into the molding layer 30; Referring to FIG. 2C, a thinning process is performed on one surface of the molding layer 30 that is far from the carrier 10, so that the first bump 21 of the first chip 11 and the first bump 21 of the second chip 12 are formed. 2 exposing the bump 22; Referring to FIG. 2D, forming a third bump 40 on one surface of the molding layer 30 where the first bump 21 and the second bump 22 are exposed; and, with reference to Figure 2E, removing the carrier 10.

일 가능한 실시방식에서, 상기 칩 그룹의 수량은 1보다 크며, 방법은 캐리어(10)를 제거한 후, 형성된 패키지에 대해 절단을 수행하여 복수의 유닛 패키지를 획득하는 단계를 더 포함하며, 여기서 각 유닛 패키지는 한 그룹의 칩을 포함한다. 이에 따라 대규모 패키징을 구현할 수 있다.In one possible embodiment, the quantity of the chip group is greater than 1, and the method further includes removing the carrier 10 and then performing cutting on the formed package to obtain a plurality of unit packages, wherein each unit A package contains a group of chips. Accordingly, large-scale packaging can be implemented.

본 출원의 실시예가 제공하는 칩 상호연결 방법과 상호연결 소자는 칩 스택 형식의 반도체 패키지에도 마찬가지로 응용될 수 있다. 예를 들어, 도 4를 참조하면, 캐리어(10)와 다층 칩을 제공할 수 있으며; 도 4를 참조하면, 제1 층의 칩에 포함된 제1 칩(11)과 제2 칩(12)을 정면이 위를 향하도록 캐리어(10)의 표면에 실장할 수 있고; 도 1에 도시된 칩 상호연결 방법을 이용하여 제1 층의 칩에 포함된 제1 칩(11)이 상호연결 소자(13)를 통해 제2 칩(12)에 전기적으로 연결될 수 있도록, 상호연결 소자(13)를 제1 층의 칩에 포함된 제1 칩(11)과 제2 칩(12)의 일부 상부 표면에 부착하며; 제2 층의 칩에 포함된 제3 칩(14)과 제4 칩(15)을 정면이 위를 향하도록 제1 칩(11)과 제2 칩(12)의 상부 표면에 실장하고, 상호연결 소자(13)의 양측에 분포시킨 후, 도 1에 도시된 칩 상호연결 방법을 이용하여, 제2 층의 칩에 포함된 제3 칩(14)이 상호연결 소자(16)를 통해 제4 칩(15)에 전기적으로 연결될 수 있도록, 상호연결 소자(16)를 제2 층의 칩에 포함된 제3 칩(14)과 제4 칩(15)의 일부 상부 표면에 부착함과 동시에, 상호연결 소자(13)에 연결할 수 있다. 상호연결 소자(13, 16)를 통해, 제1 층의 칩에 포함된 제1 칩(11), 제2 칩(12) 및 제2 층의 칩에 포함된 제3 칩(14), 제4 칩(15) 모두 전기적인 연결을 구현할 수 있으며, 이에 따라, 상호연결 소자를 이용한 다층 칩 간의 전기적인 연결을 구현할 수 있다. The chip interconnection method and interconnection elements provided by the embodiments of the present application can also be applied to chip stack-type semiconductor packages. For example, referring to Figure 4, a carrier 10 and a multilayer chip may be provided; Referring to FIG. 4, the first chip 11 and the second chip 12 included in the first layer of chips can be mounted on the surface of the carrier 10 with the front facing upward; Interconnection is performed so that the first chip 11 included in the chip of the first layer can be electrically connected to the second chip 12 through the interconnection element 13 using the chip interconnection method shown in FIG. Attaching the element 13 to some upper surfaces of the first chip 11 and the second chip 12 included in the first layer of chips; The third chip 14 and the fourth chip 15 included in the second layer of chips are mounted on the upper surfaces of the first chip 11 and the second chip 12 with the front faces facing upward, and are interconnected. After distribution on both sides of the element 13, using the chip interconnection method shown in FIG. 1, the third chip 14 included in the chip of the second layer is connected to the fourth chip through the interconnection element 16. Interconnection elements 16 are attached to some upper surfaces of the third chip 14 and the fourth chip 15 included in the second layer of chips so as to be electrically connected to (15), and at the same time, It can be connected to element 13. Through the interconnection elements 13 and 16, the first chip 11, the second chip 12 included in the chip of the first layer, and the third chip 14 and the fourth chip included in the chip of the second layer. All of the chips 15 can implement electrical connections, and thus, electrical connections between multilayer chips using interconnection elements can be implemented.

비록 일부 구체적인 실시방식을 참고하여 본 발명의 정신과 원리를 기술하였으나, 본 발명은 공개된 구체적인 실시방식에 한정되지 않고, 각 측면에 대한 구분 역시 이익을 위해 이러한 측면 중의 특징을 조합할 수 없음을 의미하는 것이 아니며, 이러한 구분은 단지 표현의 편의를 위한 것임을 이해하여야 한다. 본 발명의 취지는 첨부된 청구항의 정신과 범위 내에 포함되는 각종 수정과 등가의 배치를 포괄하고자 하는데 있다.Although the spirit and principles of the present invention have been described with reference to some specific implementation methods, the present invention is not limited to the disclosed specific implementation methods, and the division of each aspect also means that the features of these aspects cannot be combined for benefit. It should be understood that this distinction is merely for convenience of expression. The purpose of the present invention is to encompass various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims (15)

칩 상호연결 방법에 있어서,
상부 표면에 접촉면이 제2 범프보다 작은 복수의 제1 범프가 형성된 제1 칩과 상부 표면에 복수의 제2 범프가 형성된 제2 칩을 캐리어 표면에 설치하는 단계; 및
상기 복수의 제1 범프에 본딩되기 위한 복수의 제1 패드 및 상기 복수의 제2 범프에 본딩되기 위한 복수의 제2 패드가 일측 표면에 형성된 제1 상호연결 소자를 상기 제1 칩과 상기 제2 칩의 일부 상부 표면에 부착하는 단계;
제3 칩을 상기 제1 칩 상부 표면에 실장하고, 제4 칩을 상기 제2 칩 상부 표면에 실장함으로써 상기 제3 칩과 상기 제4 칩을 상기 제1 상호연결 소자의 양측에 분포시키는 단계;
상기 제3 칩과 상기 제4 칩의 일부 상부 표면 및 상기 제1 상호연결 소자의 상부 표면에 제2 상호연결 소자를 부착하는 단계를 포함하고,
상기 제1 상호연결 소자의 복수의 상기 제1 패드를 복수의 상기 제1 범프에 정렬시켜 본딩함으로써, 상기 제1 상호연결 소자의 복수의 상기 제2 패드가 상기 제2 칩의 복수의 상기 제2 범프에 자기정렬되어 본딩되도록 하고,
상기 제1 칩, 상기 제2 칩, 상기 제3 칩 및 상기 제4 칩은 상기 제1 상호연결 소자 및 상기 제2 상호연결 소자를 통해 서로 전기적으로 연결되는 것을 특징으로 하는, 칩 상호연결 방법.In the chip interconnection method,
Installing a first chip having a plurality of first bumps formed on the upper surface and a contact surface smaller than the second bumps and a second chip having a plurality of second bumps formed on the upper surface on the carrier surface; and
A first interconnection element having a plurality of first pads for bonding to the plurality of first bumps and a plurality of second pads for bonding to the plurality of second bumps formed on one surface is connected to the first chip and the second bump. Attaching to some upper surface of the chip;
distributing the third chip and the fourth chip on both sides of the first interconnection element by mounting a third chip on the upper surface of the first chip and mounting a fourth chip on the upper surface of the second chip;
Attaching a second interconnection element to a portion of the top surfaces of the third and fourth chips and to the top surface of the first interconnection element;
By aligning and bonding the plurality of first pads of the first interconnection element to the plurality of first bumps, the plurality of second pads of the first interconnection element are aligned with the plurality of second pads of the second chip. Self-align and bond to the bump,
The chip interconnection method, characterized in that the first chip, the second chip, the third chip, and the fourth chip are electrically connected to each other through the first interconnection element and the second interconnection element. 제1항에 있어서,
상기 제1 칩의 복수의 상기 제1 범프는 복수의 고밀도 범프이고, 상기 제2 칩의 복수의 상기 제2 범프는 복수의 저밀도 범프인 것을 특징으로 하는, 칩 상호연결 방법.According to paragraph 1,
The method of interconnecting chips, wherein the plurality of first bumps of the first chip are a plurality of high-density bumps, and the plurality of second bumps of the second chip are a plurality of low-density bumps. 제1항에 있어서,
각 그룹의 칩에 포함된 상기 제1 칩이 상기 제1 상호연결 소자를 통해 상기 제2 칩에 전기적으로 연결될 수 있도록, 상기 제1 상호연결 소자의 복수의 상기 제1 패드와 복수의 상기 제2 패드 사이에 팬아웃 회로를 형성하는 것을 특징으로 하는, 칩 상호연결 방법.According to paragraph 1,
The plurality of first pads and the plurality of second pads of the first interconnection element allow the first chip included in each group of chips to be electrically connected to the second chip through the first interconnection element. A method of chip interconnection, characterized by forming a fan-out circuit between pads. 제1항에 있어서,
상기 제1 상호연결 소자는 수직 상호연결 관통 비아를 구비하는 상호연결 소자로 형성되는 것을 특징으로 하는, 칩 상호연결 방법.According to paragraph 1,
A method of chip interconnection, characterized in that the first interconnection element is formed as an interconnection element having a vertical interconnection through via. 제1항에 있어서,
상기 제1 상호연결 소자는 수동 소자 또는 능동 소자로 형성되는 것을 특징으로 하는, 칩 상호연결 방법.According to paragraph 1,
A method of chip interconnection, characterized in that the first interconnection element is formed as a passive element or an active element. 삭제delete 삭제delete 삭제delete 제1항 내지 제3항 중의 어느 한 항에 있어서,
상기 제1 상호연결 소자는 실리콘(Si), 탄화규소(SiC), 비소화 갈륨(GaAs), 질화 갈륨(GaN) 중의 하나 이상을 포함하는 반도체 소재를 채택하는 것을 특징으로 하는, 칩 상호연결 방법.According to any one of claims 1 to 3,
A chip interconnection method, wherein the first interconnection element adopts a semiconductor material containing one or more of silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), and gallium nitride (GaN). . 제1항 내지 제3항 중의 어느 한 항에 있어서,
상기 제1 상호연결 소자는 유리, 세라믹 중의 하나 이상을 포함하는 무기재료를 채택하는 것을 특징으로 하는, 칩 상호연결 방법.According to any one of claims 1 to 3,
A chip interconnection method, characterized in that the first interconnection element adopts an inorganic material including at least one of glass and ceramic. 제1항 내지 제3항 중의 어느 한 항에 있어서,
상기 제1 상호연결 소자는 인쇄회로기판(PCB), 몰드 기판(EMC), 연성회로기판 중의 하나 이상을 포함하는 패키지 기판 소재를 채택하는 것을 특징으로 하는, 칩 상호연결 방법.According to any one of claims 1 to 3,
A chip interconnection method, characterized in that the first interconnection element adopts a package substrate material including one or more of a printed circuit board (PCB), a molded substrate (EMC), and a flexible circuit board. 제1항 내지 제3항 중의 어느 한 항에 있어서,
상기 제1 상호연결 소자는 구리, 알루미늄 중의 하나 이상을 포함하는 금속 기판 소재를 채택하는 것을 특징으로 하는, 칩 상호연결 방법.According to any one of claims 1 to 3,
A chip interconnection method, characterized in that the first interconnection element adopts a metal substrate material containing at least one of copper and aluminum. 제1항 내지 제3항 중의 어느 한 항에 있어서,
상기 제1 상호연결 소자는 부가적으로 집적회로, 미세전자기계시스템(MEMS), 광전자소자 및 수동소자(IPD)의 기능을 갖는 것을 특징으로 하는, 칩 상호연결 방법.According to any one of claims 1 to 3,
A method of chip interconnection, characterized in that the first interconnection device additionally has the functions of an integrated circuit, microelectromechanical system (MEMS), optoelectronic device, and passive device (IPD). 삭제delete 삭제delete
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